.num_of_queues = 512,
.max_tfd_queue_size = 256,
.wd_timeout = IWL_LONG_WD_TIMEOUT,
- .max_event_log_size = 512,
.shadow_reg_enable = true,
.pcie_l1_allowed = true,
.smem_offset = IWL_22000_SMEM_OFFSET,
.num_of_queues = 31,
.max_tfd_queue_size = 256,
.wd_timeout = IWL_LONG_WD_TIMEOUT,
- .max_event_log_size = 512,
.shadow_reg_enable = true,
.pcie_l1_allowed = true,
.apmg_wake_up_wa = true,
.num_of_queues = 31,
.max_tfd_queue_size = 256,
.wd_timeout = IWL_LONG_WD_TIMEOUT,
- .max_event_log_size = 512,
.shadow_reg_enable = true,
.pcie_l1_allowed = true,
.nvm_hw_section_num = 10,
.num_of_queues = 31,
.max_tfd_queue_size = 256,
.wd_timeout = IWL_LONG_WD_TIMEOUT,
- .max_event_log_size = 512,
.shadow_reg_enable = true,
.pcie_l1_allowed = true,
.smem_offset = IWL9000_SMEM_OFFSET,
.num_of_queues = 512,
.max_tfd_queue_size = 65536,
.wd_timeout = IWL_LONG_WD_TIMEOUT,
- .max_event_log_size = 512,
.shadow_reg_enable = true,
.pcie_l1_allowed = true,
.smem_offset = IWL_AX210_SMEM_OFFSET,
.num_of_queues = 512,
.max_tfd_queue_size = 65536,
.wd_timeout = IWL_LONG_WD_TIMEOUT,
- .max_event_log_size = 512,
.shadow_reg_enable = true,
.pcie_l1_allowed = true,
.smem_offset = IWL_BZ_SMEM_OFFSET,
.num_of_queues = 512,
.max_tfd_queue_size = 65536,
.wd_timeout = IWL_LONG_WD_TIMEOUT,
- .max_event_log_size = 512,
.shadow_reg_enable = true,
.pcie_l1_allowed = true,
.smem_offset = IWL_DR_SMEM_OFFSET,
.num_of_queues = 512,
.max_tfd_queue_size = 65536,
.wd_timeout = IWL_LONG_WD_TIMEOUT,
- .max_event_log_size = 512,
.shadow_reg_enable = true,
.pcie_l1_allowed = true,
.smem_offset = IWL_SC_SMEM_OFFSET,