return spinand_write_reg_op(spinand, W25N0XJW_SR4, sr4);
}
+/*
+ * SDR dual and quad I/O operations over 104MHz require the HS bit to
+ * enable a few more dummy cycles.
+ */
+static bool w25n0xjw_op_needs_hs(const struct spi_mem_op *op)
+{
+ if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
+ return false;
+ else if (op->cmd.buswidth != 1 || op->addr.buswidth == 1)
+ return false;
+ else if (op->max_freq && op->max_freq <= 104 * HZ_PER_MHZ)
+ return false;
+
+ return true;
+}
+
static int w25n0xjw_hs_cfg(struct spinand_device *spinand,
enum spinand_bus_interface iface)
{
const struct spi_mem_op *op;
- bool hs;
if (iface != SSDR)
return -EOPNOTSUPP;
- /*
- * SDR dual and quad I/O operations over 104MHz require the HS bit to
- * enable a few more dummy cycles.
- */
op = spinand->op_templates->read_cache;
- if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
- hs = false;
- else if (op->cmd.buswidth != 1 || op->addr.buswidth == 1)
- hs = false;
- else if (op->max_freq && op->max_freq <= 104 * HZ_PER_MHZ)
- hs = false;
- else
- hs = true;
- return w25n0xjw_set_sr4_hs(spinand, hs);
+ return w25n0xjw_set_sr4_hs(spinand, w25n0xjw_op_needs_hs(op));
}
static int w35n0xjw_write_vcr(struct spinand_device *spinand, u8 reg, u8 val)