drm/i915/dp: Cache max common lane count

Cache the maximum common lane count together with the common link
rates.

This is safe because the cached value is updated:
- during driver probe, before the connector is registered and can be
  used for mode validation or modesetting
- during resume, before output HW state readout can query it
- during connector detection, right after updating the sink/link
  capabilities

Caching the value allows detecting max common lane count changes in
a follow-up change and keeps the tracking of max common lane count
aligned with that of common rates.

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20260522160514.2628249-4-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ac865b6557b65df651f01de600c835db1e00f182..13ce37a71b68bd9548ea5a8c4c2346e3aeff1b29 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1823,6 +1823,7 @@ struct intel_dp {
        /* intersection of source and sink rates */
        int num_common_rates;
        int common_rates[DP_MAX_SUPPORTED_RATES];
+       int max_common_lane_count;
        struct {
                /* TODO: move the rest of link specific fields to here */
                bool active;

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e9eee452dc36f8e9bd5a6e60d806131d96439404..1a6d00852eb1336c5a701af7bd67bea0a0046149 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -363,7 +363,7 @@ int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
 }
 
 /* Theoretical max between source and sink */
-int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
+static void intel_dp_set_max_common_lane_count(struct intel_dp *intel_dp)
 {
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
        int source_max = intel_dp_max_source_lane_count(dig_port);
@@ -374,7 +374,12 @@ int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
        if (lttpr_max)
                sink_max = min(sink_max, lttpr_max);
 
-       return min3(source_max, sink_max, lane_max);
+       intel_dp->max_common_lane_count = min3(source_max, sink_max, lane_max);
+}
+
+int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
+{
+       return intel_dp->max_common_lane_count;
 }
 
 static int forced_lane_count(struct intel_dp *intel_dp)
@@ -810,6 +815,7 @@ static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 static void intel_dp_set_common_link_params(struct intel_dp *intel_dp)
 {
        intel_dp_set_common_rates(intel_dp);
+       intel_dp_set_max_common_lane_count(intel_dp);
        intel_dp_link_config_init(intel_dp);
 }