media: qcom: camss: Fix RDI streaming for CSID 340

Fix streaming from CSIDn RDI1 and RDI2 to VFEn RDI1 and RDI2. A pattern we
have replicated throughout CAMSS where we use the VC number to populate
both the VC fields and port fields of the CSID means that in practice only
VC = 0 on CSIDn:RDI0 to VFEn:RDI0 works.

Fix that for CSID 340 by separating VC and port. Fix to VC zero as a bugfix
we will look to properly populate the VC field with follow on patches
later.

Fixes: f0fc808a466a ("media: qcom: camss: Add CSID 340 support")
Cc: stable@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>

diff --git a/drivers/media/platform/qcom/camss/camss-csid-340.c b/drivers/media/platform/qcom/camss/camss-csid-340.c
index 2b50f9b96a34e3152f3daf00534f9f40d6bed1c0..0231985746edff9c32c5627a5cb089898ff6a2a8 100644 (file)
--- a/drivers/media/platform/qcom/camss/camss-csid-340.c
+++ b/drivers/media/platform/qcom/camss/camss-csid-340.c
@@ -74,9 +74,9 @@ static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
        writel_relaxed(!!enable, csid->base + CSID_RDI_CTRL(rdi));
 }
 
-static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 vc)
+static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 port, u8 vc)
 {
-       struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
+       struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + port];
        const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
                                                                   csid->res->formats->nformats,
                                                                   input_format->code);
@@ -88,14 +88,14 @@ static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8
         * the four least significant bits of the five bit VC
         * bitfield to generate an internal CID value.
         *
-        * CSID_RDI_CFG0(vc)
+        * CSID_RDI_CFG0(port)
         * DT_ID : 28:27
         * VC    : 26:22
         * DT    : 21:16
         *
         * CID   : VC 3:0 << 2 | DT_ID 1:0
         */
-       dt_id = vc & 0x03;
+       dt_id = port & 0x03;
 
        val = CSID_RDI_CFG0_DECODE_FORMAT_NOP; /* only for RDI path */
        val |= FIELD_PREP(CSID_RDI_CFG0_DT_MASK, format->data_type);
@@ -105,10 +105,11 @@ static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8
        if (enable)
                val |= CSID_RDI_CFG0_ENABLE;
 
-       dev_dbg(csid->camss->dev, "CSID%u: Stream %s (dt:0x%x vc=%u)\n",
-               csid->id, enable ? "enable" : "disable", format->data_type, vc);
+       dev_dbg(csid->camss->dev, "CSID%u: Stream %s (dt:0x%x port=%u vc=%u)\n",
+               csid->id, enable ? "enable" : "disable", format->data_type,
+               port, vc);
 
-       writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
+       writel_relaxed(val, csid->base + CSID_RDI_CFG0(port));
 }
 
 static void csid_configure_stream(struct csid_device *csid, u8 enable)
@@ -117,9 +118,10 @@ static void csid_configure_stream(struct csid_device *csid, u8 enable)
 
        __csid_configure_rx(csid, &csid->phy);
 
+       /* Loop through all enabled ports and configure a stream for each */
        for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++) {
                if (csid->phy.en_vc & BIT(i)) {
-                       __csid_configure_rdi_stream(csid, enable, i);
+                       __csid_configure_rdi_stream(csid, enable, i, 0);
                        __csid_ctrl_rdi(csid, enable, i);
                }
        }