]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/amdgpu: deduplicate ring preempt ib function
authorLeonardo Cesar <leonardocesar@usp.br>
Tue, 28 Apr 2026 23:19:44 +0000 (20:19 -0300)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 5 May 2026 13:56:29 +0000 (09:56 -0400)
The ring preemption function is identical for both gfx_v11_0 and
gfx_v12_0. This patch refactors the code by moving the core logic
into a generic function inside amdgpu_gfx.c to reduce code
duplication and simplify future maintenance.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leonardo Cesar <leonardocesar@usp.br>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

index b8ca876694ff802cc073904f132b3ea48cd0f915..515cc4a2aeb4d24d91cf27114c53ea1f703ceb5e 100644 (file)
@@ -2686,3 +2686,54 @@ void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev)
 #endif
 }
 
+int amdgpu_gfx_ring_preempt_ib(struct amdgpu_ring *ring)
+{
+       struct amdgpu_device *adev = ring->adev;
+       struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
+       struct amdgpu_ring *kiq_ring = &kiq->ring;
+       unsigned long flags;
+       int i;
+
+       if (adev->enable_mes)
+               return -EINVAL;
+
+       if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
+               return -EINVAL;
+
+       spin_lock_irqsave(&kiq->ring_lock, flags);
+
+       if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
+               spin_unlock_irqrestore(&kiq->ring_lock, flags);
+               return -ENOMEM;
+       }
+
+       /* assert preemption condition */
+       amdgpu_ring_set_preempt_cond_exec(ring, false);
+
+       /* assert IB preemption, emit the trailing fence */
+       kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
+                                       ring->trail_fence_gpu_addr,
+                                       ++ring->trail_seq);
+       amdgpu_ring_commit(kiq_ring);
+
+       spin_unlock_irqrestore(&kiq->ring_lock, flags);
+
+       /* poll the trailing fence */
+       for (i = 0; i < adev->usec_timeout; i++) {
+               if (ring->trail_seq ==
+                       le32_to_cpu(*(ring->trail_fence_cpu_addr)))
+                       break;
+               udelay(1);
+       }
+
+       /* deassert preemption condition */
+    amdgpu_ring_set_preempt_cond_exec(ring, true);
+
+       if (i >= adev->usec_timeout) {
+               DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
index a0cf0a3b41dafd9d39a2ef2569b4061d7ecf99c5..77050f9884f20173411f5686c298a511ffff4ed3 100644 (file)
@@ -664,6 +664,8 @@ void amdgpu_gfx_csb_preamble_end(u32 *buffer, u32 count);
 void amdgpu_debugfs_gfx_sched_mask_init(struct amdgpu_device *adev);
 void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev);
 
+int amdgpu_gfx_ring_preempt_ib(struct amdgpu_ring *ring);
+
 static inline const char *amdgpu_gfx_compute_mode_desc(int mode)
 {
        switch (mode) {
index 2c6f1e25ca145ee300f11cfcec2797066ddf3538..fabdbbd0abb7cb493c55e80c6f4c5e13d9dc7fd4 100644 (file)
@@ -6232,56 +6232,6 @@ static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring,
        ring->set_q_mode_offs = offs;
 }
 
-static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring)
-{
-       int i, r = 0;
-       struct amdgpu_device *adev = ring->adev;
-       struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
-       struct amdgpu_ring *kiq_ring = &kiq->ring;
-       unsigned long flags;
-
-       if (adev->enable_mes)
-               return -EINVAL;
-
-       if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
-               return -EINVAL;
-
-       spin_lock_irqsave(&kiq->ring_lock, flags);
-
-       if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
-               spin_unlock_irqrestore(&kiq->ring_lock, flags);
-               return -ENOMEM;
-       }
-
-       /* assert preemption condition */
-       amdgpu_ring_set_preempt_cond_exec(ring, false);
-
-       /* assert IB preemption, emit the trailing fence */
-       kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
-                                  ring->trail_fence_gpu_addr,
-                                  ++ring->trail_seq);
-       amdgpu_ring_commit(kiq_ring);
-
-       spin_unlock_irqrestore(&kiq->ring_lock, flags);
-
-       /* poll the trailing fence */
-       for (i = 0; i < adev->usec_timeout; i++) {
-               if (ring->trail_seq ==
-                   le32_to_cpu(*(ring->trail_fence_cpu_addr)))
-                       break;
-               udelay(1);
-       }
-
-       if (i >= adev->usec_timeout) {
-               r = -EINVAL;
-               DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
-       }
-
-       /* deassert preemption condition */
-       amdgpu_ring_set_preempt_cond_exec(ring, true);
-       return r;
-}
-
 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
 {
        struct amdgpu_device *adev = ring->adev;
@@ -7313,7 +7263,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
        .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl,
        .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow,
        .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec,
-       .preempt_ib = gfx_v11_0_ring_preempt_ib,
+       .preempt_ib = amdgpu_gfx_ring_preempt_ib,
        .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl,
        .emit_wreg = gfx_v11_0_ring_emit_wreg,
        .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
index 6baac533a2e68fb04f3d7fcabce9cf5c84b3237d..b866a944f878650dd01973aca266003e4085db89 100644 (file)
@@ -4616,56 +4616,6 @@ static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
        return ret;
 }
 
-static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring)
-{
-       int i, r = 0;
-       struct amdgpu_device *adev = ring->adev;
-       struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
-       struct amdgpu_ring *kiq_ring = &kiq->ring;
-       unsigned long flags;
-
-       if (adev->enable_mes)
-               return -EINVAL;
-
-       if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
-               return -EINVAL;
-
-       spin_lock_irqsave(&kiq->ring_lock, flags);
-
-       if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
-               spin_unlock_irqrestore(&kiq->ring_lock, flags);
-               return -ENOMEM;
-       }
-
-       /* assert preemption condition */
-       amdgpu_ring_set_preempt_cond_exec(ring, false);
-
-       /* assert IB preemption, emit the trailing fence */
-       kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
-                                  ring->trail_fence_gpu_addr,
-                                  ++ring->trail_seq);
-       amdgpu_ring_commit(kiq_ring);
-
-       spin_unlock_irqrestore(&kiq->ring_lock, flags);
-
-       /* poll the trailing fence */
-       for (i = 0; i < adev->usec_timeout; i++) {
-               if (ring->trail_seq ==
-                   le32_to_cpu(*(ring->trail_fence_cpu_addr)))
-                       break;
-               udelay(1);
-       }
-
-       if (i >= adev->usec_timeout) {
-               r = -EINVAL;
-               DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
-       }
-
-       /* deassert preemption condition */
-       amdgpu_ring_set_preempt_cond_exec(ring, true);
-       return r;
-}
-
 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
                                     uint32_t reg_val_offs)
 {
@@ -5536,7 +5486,7 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = {
        .pad_ib = amdgpu_ring_generic_pad_ib,
        .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl,
        .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec,
-       .preempt_ib = gfx_v12_0_ring_preempt_ib,
+       .preempt_ib = amdgpu_gfx_ring_preempt_ib,
        .emit_wreg = gfx_v12_0_ring_emit_wreg,
        .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
        .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,