drm/msm/adreno: write reserved UBWC-related bits

On the latest A8xx Adreno chips several of the bits in the UBWC-related
registers are now hardwired to 1. Currently the driver doesn't write
them because there is no side-effect. In the preparation for the
refactoring in the next patch, write '1' to those bits anyway.

Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/726504/
Link: https://lore.kernel.org/r/20260520-ubwc-rework-v5-15-72f2749bc807@oss.qualcomm.com

diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
index 53def136e0fc58e065f67fa3f63fb4c883c98a4f..7a6223ddd8cf6793108db180756ff8b158834a1d 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
@@ -288,6 +288,8 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu)
        switch (ubwc_version) {
        case UBWC_6_0:
                yuvnotcomptofc = true;
+               amsbc = true;
+               rgb565_predicator = true;
                break;
        case UBWC_5_0:
                amsbc = true;