mtd: spinand: winbond: Add support for continuous reads on W25NxxJW

As for the W35NxxJW family, add support for W25N{01,02}JW continuous
read support. Similar operations require to be done, such as setting a
specific bit in a configuration register, and providing a set of read
variants without the address cycles.

As read from cache variants are badly supported by SPI memory
controllers, we create a new set of read from cache templates with a
fake address cycle and just enough dummy cycles. There are two
unsupported configurations (which would require 4.5 dummy bytes), so we
just do not provide them.

The same extra value in the ECC is possible as with the W35NxxJW family,
so we reference the same helper to retrieve the ECC status.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
All variants have been validated on a Nuvoton MA35D1 platform.

diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
index a73a35adbf08b6f51649c06dc929090c5f483519..9b78c1e6cbc9d2ebb93c4054a7568c4e9a227374 100644 (file)
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -46,6 +46,62 @@
                   SPI_MEM_OP_DATA_IN(len, buf, 1),                     \
                   SPI_MEM_OP_MAX_FREQ(freq))
 
+#define WINBOND_CONT_READ_FROM_CACHE_1S_1D_1D_OP(ndummy, buf, len, freq) \
+       SPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1),                             \
+                  SPI_MEM_DTR_OP_ADDR(2, 0, 1),                        \
+                  SPI_MEM_DTR_OP_DUMMY(ndummy, 1),                     \
+                  SPI_MEM_DTR_OP_DATA_IN(len, buf, 1),                 \
+                  SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_1S_2S_OP(ndummy, buf, len, freq) \
+       SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1),                             \
+                  SPI_MEM_OP_ADDR(1, 0, 1),                            \
+                  SPI_MEM_OP_DUMMY(ndummy - 1, 1),                     \
+                  SPI_MEM_OP_DATA_IN(len, buf, 2),                     \
+                  SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_2S_2S_OP(ndummy, buf, len, freq) \
+       SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1),                             \
+                  SPI_MEM_OP_ADDR(1, 0, 2),                            \
+                  SPI_MEM_OP_DUMMY(ndummy - 1, 2),                     \
+                  SPI_MEM_OP_DATA_IN(len, buf, 2),                     \
+                  SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_2D_2D_OP(ndummy, buf, len, freq) \
+       SPI_MEM_OP(SPI_MEM_OP_CMD(0xbd, 1),                             \
+                  SPI_MEM_DTR_OP_ADDR(1, 0, 2),                        \
+                  SPI_MEM_DTR_OP_DUMMY(ndummy - 1, 2),                 \
+                  SPI_MEM_DTR_OP_DATA_IN(len, buf, 2),                 \
+                  SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_1S_4S_OP(ndummy, buf, len, freq) \
+       SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1),                             \
+                  SPI_MEM_OP_ADDR(1, 0, 1),                            \
+                  SPI_MEM_OP_DUMMY(ndummy - 1, 1),                     \
+                  SPI_MEM_OP_DATA_IN(len, buf, 4),                     \
+                  SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_1D_4D_OP(ndummy, buf, len, freq) \
+       SPI_MEM_OP(SPI_MEM_OP_CMD(0x6d, 1),                             \
+                  SPI_MEM_DTR_OP_ADDR(1, 0, 1),                        \
+                  SPI_MEM_DTR_OP_DUMMY(ndummy - 1, 1),                 \
+                  SPI_MEM_DTR_OP_DATA_IN(len, buf, 4),                 \
+                  SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_4S_4S_OP(ndummy, buf, len, freq) \
+       SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1),                             \
+                  SPI_MEM_OP_ADDR(1, 0, 4),                            \
+                  SPI_MEM_OP_DUMMY(ndummy - 1, 4),                     \
+                  SPI_MEM_OP_DATA_IN(len, buf, 4),                     \
+                  SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_4D_4D_OP(ndummy, buf, len, freq) \
+       SPI_MEM_OP(SPI_MEM_OP_CMD(0xed, 1),                             \
+                  SPI_MEM_DTR_OP_ADDR(1, 0, 4),                        \
+                  SPI_MEM_DTR_OP_DUMMY(ndummy - 1, 4),                 \
+                  SPI_MEM_DTR_OP_DATA_IN(len, buf, 4),                 \
+                  SPI_MEM_OP_MAX_FREQ(freq))
+
 #define WINBOND_CONT_READ_FROM_CACHE_1S_1S_8S_OP(ndummy, buf, len, freq) \
        SPI_MEM_OP(SPI_MEM_OP_CMD(0x8b, 1),                             \
                   SPI_MEM_OP_ADDR(1, 0, 1),                            \
@@ -133,6 +189,20 @@ static SPINAND_OP_VARIANTS(read_cache_dual_quad_dtr_variants,
                SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0, 0),
                SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0, 54 * HZ_PER_MHZ));
 
+static SPINAND_OP_VARIANTS(cont_read_cache_dual_quad_dtr_variants,
+               WINBOND_CONT_READ_FROM_CACHE_1S_4D_4D_OP(11, NULL, 0, 80 * HZ_PER_MHZ),
+               WINBOND_CONT_READ_FROM_CACHE_1S_1D_4D_OP(5, NULL, 0, 80 * HZ_PER_MHZ),
+               WINBOND_CONT_READ_FROM_CACHE_1S_4S_4S_OP(7, NULL, 0, 0),
+               WINBOND_CONT_READ_FROM_CACHE_1S_4S_4S_OP(6, NULL, 0, 104 * HZ_PER_MHZ),
+               WINBOND_CONT_READ_FROM_CACHE_1S_1S_4S_OP(4, NULL, 0, 0),
+               WINBOND_CONT_READ_FROM_CACHE_1S_2D_2D_OP(6, NULL, 0, 80 * HZ_PER_MHZ),
+               /* The 1S_1D_2D variant would require 4.5 dummy bytes, this is not possible */
+               WINBOND_CONT_READ_FROM_CACHE_1S_2S_2S_OP(5, NULL, 0, 0),
+               WINBOND_CONT_READ_FROM_CACHE_1S_2S_2S_OP(4, NULL, 0, 104 * HZ_PER_MHZ),
+               WINBOND_CONT_READ_FROM_CACHE_1S_1S_2S_OP(4, NULL, 0, 0),
+               /* The 1S_1D_1D variant would require 4.5 dummy bytes, this is not possible */
+               WINBOND_CONT_READ_FROM_CACHE_FAST_1S_1S_1S_OP(4, NULL, 0, 0));
+
 static SPINAND_OP_VARIANTS(read_cache_variants,
                SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(0, 2, NULL, 0, 0),
                SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(0, 1, NULL, 0, 0),
@@ -445,11 +515,25 @@ static int w25n0xjw_hs_cfg(struct spinand_device *spinand,
        if (iface != SSDR)
                return -EOPNOTSUPP;
 
+       /*
+        * At this stage, we do not yet know the continuous read template, nor
+        * if there is going to be one. Let's assume the continuous read
+        * template will be selected with the same heuristics as the buffered
+        * read variant, as there cannot be a HS configuration mismatch between
+        * them.
+        */
        op = spinand->op_templates->read_cache;
 
        return w25n0xjw_set_sr4_hs(spinand, w25n0xjw_op_needs_hs(op));
 }
 
+static int w25n0xjw_set_cont_read(struct spinand_device *spinand, bool enable)
+{
+       u8 mask = enable ? 0 : WINBOND_CFG_BUF_READ;
+
+       return spinand_upd_cfg(spinand, WINBOND_CFG_BUF_READ, mask);
+}
+
 static int w35n0xjw_write_vcr(struct spinand_device *spinand, u8 reg, u8 val)
 {
        struct spi_mem_op op = SPINAND_OP(spinand, winbond_write_vcr,
@@ -580,12 +664,14 @@ static const struct spinand_info winbond_spinand_table[] = {
                     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbc, 0x21),
                     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
                     NAND_ECCREQ(1, 512),
-                    SPINAND_INFO_OP_VARIANTS(&read_cache_dual_quad_dtr_variants,
-                                             &write_cache_variants,
-                                             &update_cache_variants),
+                    SPINAND_INFO_OP_VARIANTS_WITH_CONT(&read_cache_dual_quad_dtr_variants,
+                                                       &write_cache_variants,
+                                                       &update_cache_variants,
+                                                       &cont_read_cache_dual_quad_dtr_variants),
                     SPINAND_HAS_QE_BIT,
-                    SPINAND_ECCINFO(&w25n01jw_ooblayout, NULL),
-                    SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg)),
+                    SPINAND_ECCINFO(&w25n01jw_ooblayout, w25w35nxxjw_ecc_get_status),
+                    SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg),
+                    SPINAND_CONT_READ(w25n0xjw_set_cont_read)),
        SPINAND_INFO("W25N01KV", /* 3.3V */
                     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
                     NAND_MEMORG(1, 2048, 96, 64, 1024, 20, 1, 1, 1),
@@ -624,12 +710,14 @@ static const struct spinand_info winbond_spinand_table[] = {
                     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbf, 0x22),
                     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 2, 1),
                     NAND_ECCREQ(1, 512),
-                    SPINAND_INFO_OP_VARIANTS(&read_cache_dual_quad_dtr_variants,
-                                             &write_cache_variants,
-                                             &update_cache_variants),
+                    SPINAND_INFO_OP_VARIANTS_WITH_CONT(&read_cache_dual_quad_dtr_variants,
+                                                       &write_cache_variants,
+                                                       &update_cache_variants,
+                                                       &cont_read_cache_dual_quad_dtr_variants),
                     SPINAND_HAS_QE_BIT,
-                    SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
-                    SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg)),
+                    SPINAND_ECCINFO(&w25m02gv_ooblayout, w25w35nxxjw_ecc_get_status),
+                    SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg),
+                    SPINAND_CONT_READ(w25n0xjw_set_cont_read)),
        SPINAND_INFO("W25N02KV", /* 3.3V */
                     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
                     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),