]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/intel/display: Add support for pipe background color (v4)
authorMaarten Lankhorst <dev@lankhorst.se>
Tue, 5 May 2026 20:01:34 +0000 (22:01 +0200)
committerMaarten Lankhorst <dev@lankhorst.se>
Fri, 22 May 2026 14:10:30 +0000 (16:10 +0200)
Gen9 platforms allow CRTC's to be programmed with a background/canvas
color below the programmable planes.  Let's expose this as a property to
allow userspace to program a desired value.

This patch is based on earlier work by Chandra Konduru and Matt Roper.
Between 2018 and now, intel/display has changed so much that another
rewrite was necessary.

v2:
 - Set initial background color (black) via proper helper function (Bob)
 - Fix debugfs output
 - General rebasing
v3 (Maarten):
 - Rebase on top of recent changes.
v4 (Maarten):
 - Complete rewrite based on the solution that went upstream, and
   on the new intel color management features.

Cc: Chandra Konduru <chandra.konduru@intel.com>
Cc: dri-devel@lists.freedesktop.org
Co-developed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://patch.msgid.link/20260505200133.636584-2-dev@lankhorst.se
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
drivers/gpu/drm/i915/display/intel_color.c
drivers/gpu/drm/i915/display/intel_color.h
drivers/gpu/drm/i915/display/intel_crtc.c
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/display/intel_display_debugfs.c
drivers/gpu/drm/i915/display/intel_display_types.h
drivers/gpu/drm/i915/display/intel_modeset_setup.c

index 3bfe09d81a4c09cd00cd3b2b5d25361d2068051d..7ef870cd9a169ad3f9b015f05bb1aa5f46854df8 100644 (file)
@@ -1102,19 +1102,37 @@ static void skl_get_config(struct intel_crtc_state *crtc_state)
 {
        struct intel_display *display = to_intel_display(crtc_state);
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+       u32 color;
 
        crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);
        crtc_state->csc_mode = ilk_read_csc_mode(crtc);
 
+       color = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));
        if (DISPLAY_VER(display) < 35) {
-               u32 tmp = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));
-
-               if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
+               if (color & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
                        crtc_state->gamma_enable = true;
 
-               if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
+               if (color & SKL_BOTTOM_COLOR_CSC_ENABLE)
                        crtc_state->csc_enable = true;
        }
+
+       crtc_state->hw.background_color = color & GENMASK(29, 0);
+}
+
+u32 intel_color_background_color_drm_to_hw(u64 drm_background_color)
+{
+       return (DRM_ARGB64_GETR_BPC(drm_background_color, 10) << 20) |
+              (DRM_ARGB64_GETG_BPC(drm_background_color, 10) << 10) |
+              (DRM_ARGB64_GETB_BPC(drm_background_color, 10));
+}
+
+u64 intel_color_background_color_hw_to_drm(u32 hw_background_color)
+{
+       u16 r = (hw_background_color >> 20) & 0x3ff;
+       u16 g = (hw_background_color >> 10) & 0x3ff;
+       u16 b = hw_background_color & 0x3ff;
+
+       return DRM_ARGB64_PREP_BPC(0x3ff, r, g, b, 10);
 }
 
 static void skl_color_commit_arm(struct intel_dsb *dsb,
@@ -1123,16 +1141,11 @@ static void skl_color_commit_arm(struct intel_dsb *dsb,
        struct intel_display *display = to_intel_display(crtc_state);
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        enum pipe pipe = crtc->pipe;
-       u32 val = 0;
+       u32 val = crtc_state->hw.background_color;
 
        if (crtc_state->has_psr)
                ilk_load_csc_matrix(dsb, crtc_state);
 
-       /*
-        * We don't (yet) allow userspace to control the pipe background color,
-        * so force it to black, but apply pipe gamma and CSC appropriately
-        * so that its handling will match how we program our planes.
-        */
        if (crtc_state->gamma_enable)
                val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
        if (crtc_state->csc_enable)
@@ -1151,11 +1164,7 @@ static void icl_color_commit_arm(struct intel_dsb *dsb,
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        enum pipe pipe = crtc->pipe;
 
-       /*
-        * We don't (yet) allow userspace to control the pipe background color,
-        * so force it to black.
-        */
-       intel_de_write_dsb(display, dsb, SKL_BOTTOM_COLOR(pipe), 0);
+       intel_de_write_dsb(display, dsb, SKL_BOTTOM_COLOR(pipe), crtc_state->hw.background_color);
 
        intel_de_write_dsb(display, dsb, GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
 
@@ -2107,9 +2116,15 @@ int intel_color_check(struct intel_atomic_state *state,
         * May need to update pipe gamma enable bits
         * when C8 planes are getting enabled/disabled.
         */
-       if (!old_crtc_state->c8_planes != !new_crtc_state->c8_planes)
+       if (!old_crtc_state->c8_planes != !new_crtc_state->c8_planes ||
+           old_crtc_state->hw.background_color != new_crtc_state->hw.background_color)
                new_crtc_state->uapi.color_mgmt_changed = true;
 
+       if (DRM_ARGB64_GETA(new_crtc_state->uapi.background_color) != 0xffff) {
+               drm_dbg_kms(display->drm, "New background not completely opaque\n");
+               return -EINVAL;
+       }
+
        if (!intel_crtc_needs_color_update(new_crtc_state))
                return 0;
 
index c21b9bdf7bb8a2f43ab2a025874917b2da01c4ab..f3963a8d1239fbae1f598bdba82d0fc7d0049572 100644 (file)
@@ -47,4 +47,7 @@ void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
 void intel_color_plane_commit_arm(struct intel_dsb *dsb,
                                  const struct intel_plane_state *plane_state);
 bool intel_color_crtc_has_3dlut(struct intel_display *display, enum pipe pipe);
+u32 intel_color_background_color_drm_to_hw(u64 drm_background_color);
+u64 intel_color_background_color_hw_to_drm(u32 hw_background_color);
+
 #endif /* __INTEL_COLOR_H__ */
index 03de219f7a645a339fa4cb4399a83a491d719115..b7600cecafc859184dd94e188a5bcc5a8ca8526e 100644 (file)
@@ -7,6 +7,7 @@
 #include <linux/slab.h>
 
 #include <drm/drm_atomic_helper.h>
+#include <drm/drm_blend.h>
 #include <drm/drm_fourcc.h>
 #include <drm/drm_plane.h>
 #include <drm/drm_print.h>
@@ -405,6 +406,9 @@ static int __intel_crtc_init(struct intel_display *display, enum pipe pipe)
                                                BIT(DRM_SCALING_FILTER_DEFAULT) |
                                                BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
 
+       if (DISPLAY_VER(display) >= 9)
+               drm_crtc_attach_background_color_property(&crtc->base);
+
        intel_color_crtc_init(crtc);
        intel_drrs_crtc_init(crtc);
        intel_crtc_crc_init(crtc);
index 757a78c75bbffdde00283f50bf589e659cd90223..6c8935f69db18e2cf1760359d0a1abb575e8f560 100644 (file)
@@ -4505,6 +4505,8 @@ intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
                                  crtc_state->uapi.gamma_lut);
        drm_property_replace_blob(&crtc_state->hw.ctm,
                                  crtc_state->uapi.ctm);
+       crtc_state->hw.background_color =
+               intel_color_background_color_drm_to_hw(crtc_state->uapi.background_color);
 }
 
 static void
@@ -4544,6 +4546,7 @@ copy_joiner_crtc_state_nomodeset(struct intel_atomic_state *state,
                                  primary_crtc_state->hw.gamma_lut);
        drm_property_replace_blob(&secondary_crtc_state->hw.ctm,
                                  primary_crtc_state->hw.ctm);
+       secondary_crtc_state->hw.background_color = primary_crtc_state->hw.background_color;
 
        secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed;
 }
@@ -5360,6 +5363,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
                else
                        PIPE_CONF_CHECK_X(csc_mode);
                PIPE_CONF_CHECK_BOOL(gamma_enable);
+
+               PIPE_CONF_CHECK_X(hw.background_color);
                PIPE_CONF_CHECK_BOOL(csc_enable);
                PIPE_CONF_CHECK_BOOL(wgc_enable);
 
index 81bef000a4e3e344ff97cbcd8e494482c43a0b5d..3d6f36773ad8a10605150435559f35d783dfd9f1 100644 (file)
@@ -572,6 +572,12 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
 
        intel_scaler_info(m, crtc);
 
+       if (DISPLAY_VER(display) >= 9) {
+               u32 background = crtc_state->hw.background_color;
+
+               seq_printf(m, "\tbackground color (10bpc XRGB2101010): %08x\n", background);
+       }
+
        if (crtc_state->joiner_pipes)
                seq_printf(m, "\tLinked to 0x%x pipes as a %s\n",
                           crtc_state->joiner_pipes,
index f44be5c689aefb20db9570e0553e8d6b632b9118..1c0c32c4e43a50a509a1ea0e0e5f5d2ee43c10be 100644 (file)
@@ -1035,6 +1035,7 @@ struct intel_crtc_state {
                /* logical state of LUTs */
                struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
                struct drm_display_mode mode, pipe_mode, adjusted_mode;
+               u32 background_color;
                enum drm_scaling_filter scaling_filter;
                u8 sharpness_strength;
        } hw;
index e88082c8caace86b01652ca9b9f162dcc00c1005..0c9775eabdf02a53672a2796430a82782c30a497 100644 (file)
@@ -334,6 +334,8 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state
        crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
        crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
        crtc_state->uapi.sharpness_strength = crtc_state->hw.sharpness_strength;
+       crtc_state->uapi.background_color =
+               intel_color_background_color_hw_to_drm(crtc_state->hw.background_color);
 
        if (DISPLAY_INFO(display)->color.degamma_lut_size) {
                /* assume 1:1 mapping */