]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/amdgpu: only use working sdma schedulers for ttm
authorPierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Thu, 8 Jan 2026 16:03:30 +0000 (17:03 +0100)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 17 Apr 2026 19:41:12 +0000 (15:41 -0400)
It's possible that some sdma instances aren't working so we shouldn't try
to use them from TTM. To achieve this, delay the call to
amdgpu_sdma_set_buffer_funcs_scheds after the rings have been tested, and
then use the 'ready' property to decide if a sched should be used or not.

Note that currently it's not doing much, because if the ring helper fails
for any ring, the whole sdma block init fails.

---
v5: check buffer_funcs_enabled from amdgpu_ttm_access_memory_sdma
---

Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
12 files changed:
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
drivers/gpu/drm/amd/amdgpu/si_dma.c

index 24c7b0b48418bd5e0cdcd190d7b8433648e07e76..4513095e3ebedec496f08f6fb13257bddf781829 100644 (file)
@@ -1560,7 +1560,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,
        if (!adev->mman.sdma_access_ptr)
                return -EACCES;
 
-       if (!drm_dev_enter(adev_to_drm(adev), &idx))
+       if (!adev->mman.buffer_funcs_enabled || !drm_dev_enter(adev_to_drm(adev), &idx))
                return -ENODEV;
 
        if (write)
@@ -2300,8 +2300,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
        if (enable) {
                struct drm_gpu_scheduler *sched;
 
-               if (!adev->mman.num_buffer_funcs_scheds ||
-                   !adev->mman.buffer_funcs_scheds[0]->ready) {
+               if (!adev->mman.num_buffer_funcs_scheds) {
                        dev_warn(adev->dev, "Not enabling DMA transfers for in kernel use");
                        return;
                }
@@ -2683,16 +2682,26 @@ void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev,
 {
        struct drm_gpu_scheduler *sched;
        struct amdgpu_vmhub *hub;
-       int i;
+       int i, n;
 
        adev->mman.buffer_funcs = buffer_funcs;
 
-       for (i = 0; i < adev->sdma.num_instances; i++) {
+       for (i = 0, n = 0; i < adev->sdma.num_instances; i++) {
                if (adev->sdma.has_page_queue)
                        sched = &adev->sdma.instance[i].page.sched;
                else
                        sched = &adev->sdma.instance[i].ring.sched;
-               adev->mman.buffer_funcs_scheds[i] = sched;
+
+               if (!sched->ready)
+                       continue;
+
+               adev->mman.buffer_funcs_scheds[n++] = sched;
+       }
+
+       if (n == 0) {
+               adev->mman.num_buffer_funcs_scheds = 0;
+               drm_warn(&adev->ddev, "No working sdma ring available\n");
+               return;
        }
 
        /* Navi1x's workaround requires us to limit to a single SDMA sched
@@ -2700,7 +2709,7 @@ void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev,
         */
        hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
        adev->mman.num_buffer_funcs_scheds = hub->sdma_invalidation_workaround ?
-               1 : adev->sdma.num_instances;
+               1 : n;
 }
 
 #if defined(CONFIG_DEBUG_FS)
index 26276dcfd458e57a5b42aed537f3241c052615cf..120da838ac282f499e2403d87f014efdc6b85df1 100644 (file)
@@ -939,7 +939,6 @@ static int cik_sdma_early_init(struct amdgpu_ip_block *ip_block)
 
        cik_sdma_set_ring_funcs(adev);
        cik_sdma_set_irq_funcs(adev);
-       cik_sdma_set_buffer_funcs(adev);
        amdgpu_sdma_set_vm_pte_scheds(adev, &cik_sdma_vm_pte_funcs);
 
        return 0;
@@ -1000,8 +999,15 @@ static int cik_sdma_sw_fini(struct amdgpu_ip_block *ip_block)
 static int cik_sdma_hw_init(struct amdgpu_ip_block *ip_block)
 {
        struct amdgpu_device *adev = ip_block->adev;
+       int r;
+
+       r = cik_sdma_start(adev);
+       if (r)
+               return r;
+
+       cik_sdma_set_buffer_funcs(adev);
 
-       return cik_sdma_start(adev);
+       return 0;
 }
 
 static int cik_sdma_hw_fini(struct amdgpu_ip_block *ip_block)
index c6a059ca59e5bd1cbedae0c8294450f16d9d61d9..93ec52c1f3678340b9c5757a2d1ff23a3f5b29ce 100644 (file)
@@ -828,7 +828,6 @@ static int sdma_v2_4_early_init(struct amdgpu_ip_block *ip_block)
                return r;
 
        sdma_v2_4_set_ring_funcs(adev);
-       sdma_v2_4_set_buffer_funcs(adev);
        amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v2_4_vm_pte_funcs);
        sdma_v2_4_set_irq_funcs(adev);
 
@@ -898,7 +897,9 @@ static int sdma_v2_4_hw_init(struct amdgpu_ip_block *ip_block)
        if (r)
                return r;
 
-       return r;
+       sdma_v2_4_set_buffer_funcs(adev);
+
+       return 0;
 }
 
 static int sdma_v2_4_hw_fini(struct amdgpu_ip_block *ip_block)
index cb516a25210d87fb9c44f2e6f712cb8359e8b9dc..3fde9be7469004f596cc3c4c9e3c7fbdadbf27ab 100644 (file)
@@ -1108,7 +1108,6 @@ static int sdma_v3_0_early_init(struct amdgpu_ip_block *ip_block)
                return r;
 
        sdma_v3_0_set_ring_funcs(adev);
-       sdma_v3_0_set_buffer_funcs(adev);
        amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v3_0_vm_pte_funcs);
        sdma_v3_0_set_irq_funcs(adev);
 
@@ -1184,7 +1183,9 @@ static int sdma_v3_0_hw_init(struct amdgpu_ip_block *ip_block)
        if (r)
                return r;
 
-       return r;
+       sdma_v3_0_set_buffer_funcs(adev);
+
+       return 0;
 }
 
 static int sdma_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)
index d56be26f216bb099a36a8d245214f72d52645690..8a2a4e61867e94688f8fe7bbddc606123e46d4aa 100644 (file)
@@ -1775,7 +1775,6 @@ static int sdma_v4_0_early_init(struct amdgpu_ip_block *ip_block)
                adev->sdma.has_page_queue = true;
 
        sdma_v4_0_set_ring_funcs(adev);
-       sdma_v4_0_set_buffer_funcs(adev);
        amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_0_vm_pte_funcs);
        sdma_v4_0_set_irq_funcs(adev);
        sdma_v4_0_set_ras_funcs(adev);
@@ -1961,6 +1960,7 @@ static int sdma_v4_0_sw_fini(struct amdgpu_ip_block *ip_block)
 static int sdma_v4_0_hw_init(struct amdgpu_ip_block *ip_block)
 {
        struct amdgpu_device *adev = ip_block->adev;
+       int r;
 
        if (adev->flags & AMD_IS_APU)
                amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false, 0);
@@ -1968,7 +1968,12 @@ static int sdma_v4_0_hw_init(struct amdgpu_ip_block *ip_block)
        if (!amdgpu_sriov_vf(adev))
                sdma_v4_0_init_golden_registers(adev);
 
-       return sdma_v4_0_start(adev);
+       r = sdma_v4_0_start(adev);
+       if (r)
+               return r;
+       sdma_v4_0_set_buffer_funcs(adev);
+
+       return 0;
 }
 
 static int sdma_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)
index 67e9697301b47da6675d2f29a9e23801b3bb3aa3..88428b88e00fc08be372cc55ac99fdc6de5c5157 100644 (file)
@@ -1368,7 +1368,6 @@ static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block)
                adev->sdma.has_page_queue = true;
 
        sdma_v4_4_2_set_ring_funcs(adev);
-       sdma_v4_4_2_set_buffer_funcs(adev);
        amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_4_2_vm_pte_funcs);
        sdma_v4_4_2_set_irq_funcs(adev);
        sdma_v4_4_2_set_ras_funcs(adev);
@@ -1568,8 +1567,11 @@ static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block)
                sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
 
        r = sdma_v4_4_2_inst_start(adev, inst_mask, false);
+       if (r)
+               return r;
+       sdma_v4_4_2_set_buffer_funcs(adev);
 
-       return r;
+       return 0;
 }
 
 static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block)
index 86f5eb784d572335b82944f1660e896453592cb3..fa02907217e08f4075eb8777a16105be65e0c166 100644 (file)
@@ -1373,7 +1373,6 @@ static int sdma_v5_0_early_init(struct amdgpu_ip_block *ip_block)
                return r;
 
        sdma_v5_0_set_ring_funcs(adev);
-       sdma_v5_0_set_buffer_funcs(adev);
        amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v5_0_vm_pte_funcs);
        sdma_v5_0_set_irq_funcs(adev);
        sdma_v5_0_set_mqd_funcs(adev);
@@ -1472,8 +1471,11 @@ static int sdma_v5_0_hw_init(struct amdgpu_ip_block *ip_block)
        sdma_v5_0_init_golden_registers(adev);
 
        r = sdma_v5_0_start(adev);
+       if (r)
+               return r;
+       sdma_v5_0_set_buffer_funcs(adev);
 
-       return r;
+       return 0;
 }
 
 static int sdma_v5_0_hw_fini(struct amdgpu_ip_block *ip_block)
index 3fec838374b2373681d72d30778ba16a3d9ebbc3..f6ecbc524c9b7aced7993b731e6f0a3ba438703e 100644 (file)
@@ -1264,7 +1264,6 @@ static int sdma_v5_2_early_init(struct amdgpu_ip_block *ip_block)
                return r;
 
        sdma_v5_2_set_ring_funcs(adev);
-       sdma_v5_2_set_buffer_funcs(adev);
        amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v5_2_vm_pte_funcs);
        sdma_v5_2_set_irq_funcs(adev);
        sdma_v5_2_set_mqd_funcs(adev);
@@ -1385,8 +1384,14 @@ static int sdma_v5_2_sw_fini(struct amdgpu_ip_block *ip_block)
 static int sdma_v5_2_hw_init(struct amdgpu_ip_block *ip_block)
 {
        struct amdgpu_device *adev = ip_block->adev;
+       int r;
 
-       return sdma_v5_2_start(adev);
+       r = sdma_v5_2_start(adev);
+       if (r)
+               return r;
+       sdma_v5_2_set_buffer_funcs(adev);
+
+       return 0;
 }
 
 static int sdma_v5_2_hw_fini(struct amdgpu_ip_block *ip_block)
index eaf5b4656df155e0ba5100d4c924b06c94a9aecf..de329b76a00ca0cc63579f37b421aaa96e148259 100644 (file)
@@ -1313,7 +1313,6 @@ static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block)
                return r;
 
        sdma_v6_0_set_ring_funcs(adev);
-       sdma_v6_0_set_buffer_funcs(adev);
        amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v6_0_vm_pte_funcs);
        sdma_v6_0_set_irq_funcs(adev);
        sdma_v6_0_set_mqd_funcs(adev);
@@ -1477,6 +1476,7 @@ static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block)
        r = sdma_v6_0_start(adev);
        if (r)
                return r;
+       sdma_v6_0_set_buffer_funcs(adev);
 
        return sdma_v6_0_set_userq_trap_interrupts(adev, true);
 }
index 7161e818bfd616f3e11b13043932277d738e3fea..85d98a0e1bffb1921a5bbb632f6ed66792330cd8 100644 (file)
@@ -1299,7 +1299,6 @@ static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block)
        }
 
        sdma_v7_0_set_ring_funcs(adev);
-       sdma_v7_0_set_buffer_funcs(adev);
        amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v7_0_vm_pte_funcs);
        sdma_v7_0_set_irq_funcs(adev);
        sdma_v7_0_set_mqd_funcs(adev);
@@ -1432,6 +1431,7 @@ static int sdma_v7_0_hw_init(struct amdgpu_ip_block *ip_block)
        r = sdma_v7_0_start(adev);
        if (r)
                return r;
+       sdma_v7_0_set_buffer_funcs(adev);
 
        return sdma_v7_0_set_userq_trap_interrupts(adev, true);
 }
index 4775bbf714a160c1e6dbe1b4aa4105144ec68559..e1c0a4ff0e7ffab09c31a017c0a82e6b2e6d1ef5 100644 (file)
@@ -1287,7 +1287,6 @@ static int sdma_v7_1_early_init(struct amdgpu_ip_block *ip_block)
        }
 
        sdma_v7_1_set_ring_funcs(adev);
-       sdma_v7_1_set_buffer_funcs(adev);
        amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v7_1_vm_pte_funcs);
        sdma_v7_1_set_irq_funcs(adev);
        sdma_v7_1_set_mqd_funcs(adev);
@@ -1386,10 +1385,16 @@ static int sdma_v7_1_hw_init(struct amdgpu_ip_block *ip_block)
 {
        struct amdgpu_device *adev = ip_block->adev;
        uint32_t inst_mask;
+       int r;
 
        inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
 
-       return sdma_v7_1_inst_start(adev, inst_mask);
+       r = sdma_v7_1_inst_start(adev, inst_mask);
+       if (r)
+               return r;
+       sdma_v7_1_set_buffer_funcs(adev);
+
+       return 0;
 }
 
 static int sdma_v7_1_hw_fini(struct amdgpu_ip_block *ip_block)
index 155067c20a0ed067bb50a4dc74eb07437a464af6..549708075eb482c1ac12544a2a31a4fe426a217f 100644 (file)
@@ -487,7 +487,6 @@ static int si_dma_early_init(struct amdgpu_ip_block *ip_block)
        adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 
        si_dma_set_ring_funcs(adev);
-       si_dma_set_buffer_funcs(adev);
        amdgpu_sdma_set_vm_pte_scheds(adev, &si_dma_vm_pte_funcs);
        si_dma_set_irq_funcs(adev);
 
@@ -543,8 +542,14 @@ static int si_dma_sw_fini(struct amdgpu_ip_block *ip_block)
 static int si_dma_hw_init(struct amdgpu_ip_block *ip_block)
 {
        struct amdgpu_device *adev = ip_block->adev;
+       int r;
 
-       return si_dma_start(adev);
+       r = si_dma_start(adev);
+       if (r)
+               return r;
+       si_dma_set_buffer_funcs(adev);
+
+       return 0;
 }
 
 static int si_dma_hw_fini(struct amdgpu_ip_block *ip_block)