drm/amd/display: Delete unimplemented dm_pp_apply_power_level_change_request() (v2)

dm_pp_apply_power_level_change_request() was called from old
DCE clock manager implementations on DCE6, 8, 10, 11.2
but has not been implemented ever since the beginning of DC.

Affected GPUs have been working fine without that implementation
for many years. Let's delete it now.

v2:
- Delete dm_pp_apply_power_level_change_request too

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 11b2ea6edf953114c6b3753fe2d089b94866b32f..17f42201ab8629cb7ce4d330bbd61dd9deb05160 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -417,14 +417,6 @@ bool dm_pp_notify_wm_clock_changes(
        return false;
 }
 
-bool dm_pp_apply_power_level_change_request(
-       const struct dc_context *ctx,
-       struct dm_pp_power_level_change_request *level_change_req)
-{
-       /* TODO: to be implemented */
-       return false;
-}
-
 bool dm_pp_apply_clock_for_voltage_request(
        const struct dc_context *ctx,
        struct dm_pp_clock_for_voltage_req *clock_for_voltage_req)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index 808e24f0e88fd489444266a34c7a96d9560a6927..4ccc6c742d000287a55ad012523bdc8d66c0529e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -431,19 +431,10 @@ static void dce_update_clocks(struct clk_mgr *clk_mgr_base,
                        bool safe_to_lower)
 {
        struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-       struct dm_pp_power_level_change_request level_change_req;
        const int max_disp_clk =
                clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
        int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);
 
-       level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
-       /* get max clock state from PPLIB */
-       if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
-                       || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
-               if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
-                       clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
-       }
-
        if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
                patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk);
                clk_mgr_base->clks.dispclk_khz = patched_disp_clk;

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
index b35a44976477a89b0e26ae80fd84058b2f04e059..d3cd542063db1221ae662dc684d28d98b3930070 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
@@ -257,21 +257,12 @@ static void dce11_update_clocks(struct clk_mgr *clk_mgr_base,
                        bool safe_to_lower)
 {
        struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-       struct dm_pp_power_level_change_request level_change_req;
        int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
 
        /*TODO: W/A for dal3 linux, investigate why this works */
        if (!clk_mgr_dce->dfs_bypass_active)
                patched_disp_clk = patched_disp_clk * 115 / 100;
 
-       level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
-       /* get max clock state from PPLIB */
-       if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
-                       || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
-               if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
-                       clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
-       }
-
        if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
                context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk);
                clk_mgr_base->clks.dispclk_khz = patched_disp_clk;

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
index 1f36ad8a7de462878c250c2bafaf70894a911fc8..48393c69735b674c07d6cbc204a743f68a31f4a0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
@@ -193,21 +193,12 @@ static void dce112_update_clocks(struct clk_mgr *clk_mgr_base,
                        bool safe_to_lower)
 {
        struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-       struct dm_pp_power_level_change_request level_change_req;
        int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
 
        /*TODO: W/A for dal3 linux, investigate why this works */
        if (!clk_mgr_dce->dfs_bypass_active)
                patched_disp_clk = patched_disp_clk * 115 / 100;
 
-       level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
-       /* get max clock state from PPLIB */
-       if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
-                       || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
-               if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
-                       clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
-       }
-
        if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
                patched_disp_clk = dce112_set_clock(clk_mgr_base, patched_disp_clk);
                clk_mgr_base->clks.dispclk_khz = patched_disp_clk;

diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index fbbf9c757b3c362360ca6bfedb0d81c142591058..1395d36bfabe9dce089729f047246bcedf1fd15e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -224,10 +224,6 @@ bool dm_pp_apply_display_requirements(
        const struct dc_context *ctx,
        const struct dm_pp_display_configuration *pp_display_cfg);
 
-bool dm_pp_apply_power_level_change_request(
-       const struct dc_context *ctx,
-       struct dm_pp_power_level_change_request *level_change_req);
-
 bool dm_pp_apply_clock_for_voltage_request(
        const struct dc_context *ctx,
        struct dm_pp_clock_for_voltage_req *clock_for_voltage_req);

diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
index 3b093b8699abd7e73403dba63c4760ed3cd64998..cae3ed6056d6f675476d8b43fbfb53d99f4ae93f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
@@ -246,10 +246,6 @@ enum dm_acpi_display_type {
        AcpiDisplayType_DFP6 = 12
 };
 
-struct dm_pp_power_level_change_request {
-       enum dm_pp_clocks_state power_level;
-};
-
 struct dm_pp_clock_for_voltage_req {
        enum dm_pp_clock_type clk_type;
        uint32_t clocks_in_khz;