mips: cps: Assemble jr.hb with an R2 ISA level

A MIPS allmodconfig built with LLVM can select CPU_MIPS32_R1 together
with MIPS_MT_SMP. In that configuration clang invokes the integrated
assembler with -march=mips32, and the MIPS MT path in cps-vec.S fails
to assemble two jr.hb instructions:

  arch/mips/kernel/cps-vec.S:376:2: error: instruction requires
  a CPU feature not currently enabled

  arch/mips/kernel/cps-vec.S:490:4: error: instruction requires
  a CPU feature not currently enabled

The earlier jr.hb in the same file is already assembled inside a .set
MIPS_ISA_LEVEL_RAW scope. The two failing sites are reached after
popping back to the file's base ISA level, so LLVM correctly rejects
them for an R1 target.

Wrap those jr.hb instructions in the same ISA-level push/pop used by
the working site. This keeps the MT code unchanged while making the
required R2 hazard-branch encoding explicit to the assembler.

Assisted-by: Codex:GPT-5.5
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Reviewed-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 2ae7034a3d5c4ca8df5e0025428880e1fd0bd3dd..70413c816eb0313e16512eefc9d1c7ab5c713632 100644 (file)
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -373,8 +373,11 @@ LEAF(mips_cps_boot_vpes)
        .set    pop
 
        PTR_LA  t1, 1f
+       .set    push
+       .set    MIPS_ISA_LEVEL_RAW
        jr.hb   t1
         nop
+       .set    pop
 1:     mfc0    t1, CP0_MVPCONTROL
        ori     t1, t1, MVPCONTROL_VPC
        mtc0    t1, CP0_MVPCONTROL
@@ -487,8 +490,11 @@ LEAF(mips_cps_boot_vpes)
        li      t0, TCHALT_H
        mtc0    t0, CP0_TCHALT
        PTR_LA  t0, 1f
+       .set    push
+       .set    MIPS_ISA_LEVEL_RAW
 1:     jr.hb   t0
         nop
+       .set    pop
 
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