info->dentist_vco_freq = le32_to_cpu(info_v8->ulDentistVCOFreq) * 10;
info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
- for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
- /* Convert [10KHz] into [KHz] */
- info->disp_clk_voltage[i].max_supported_clk =
- le32_to_cpu(info_v8->sDISPCLK_Voltage[i].
- ulMaximumSupportedCLK) * 10;
- info->disp_clk_voltage[i].voltage_index =
- le32_to_cpu(info_v8->sDISPCLK_Voltage[i].ulVoltageIndex);
- }
-
info->boot_up_req_display_vector =
le32_to_cpu(info_v8->ulBootUpReqDisplayVector);
info->gpu_cap_info =
info->dentist_vco_freq = le32_to_cpu(info_v9->ulDentistVCOFreq) * 10;
info->boot_up_uma_clock = le32_to_cpu(info_v9->ulBootUpUMAClock) * 10;
- for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
- /* Convert [10KHz] into [KHz] */
- info->disp_clk_voltage[i].max_supported_clk =
- le32_to_cpu(info_v9->sDISPCLK_Voltage[i].ulMaximumSupportedCLK) * 10;
- info->disp_clk_voltage[i].voltage_index =
- le32_to_cpu(info_v9->sDISPCLK_Voltage[i].ulVoltageIndex);
- }
-
info->boot_up_req_display_vector =
le32_to_cpu(info_v9->ulBootUpReqDisplayVector);
info->gpu_cap_info = le32_to_cpu(info_v9->ulGPUCapInfo);
}
}
- /* Sort voltage table from low to high*/
- if (result == BP_RESULT_OK) {
- int32_t i;
- int32_t j;
-
- for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
- for (j = i; j > 0; --j) {
- if (
- info->disp_clk_voltage[j].max_supported_clk <
- info->disp_clk_voltage[j-1].max_supported_clk) {
- /* swap j and j - 1*/
- swap(info->disp_clk_voltage[j - 1],
- info->disp_clk_voltage[j]);
- }
- }
- }
-
- }
-
return result;
}
info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10;
info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
- for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
- /* Convert [10KHz] into [KHz] */
- info->disp_clk_voltage[i].max_supported_clk =
- le32_to_cpu(info_v11->sDISPCLK_Voltage[i].
- ulMaximumSupportedCLK) * 10;
- info->disp_clk_voltage[i].voltage_index =
- le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex);
- }
-
info->boot_up_req_display_vector =
le32_to_cpu(info_v11->ulBootUpReqDisplayVector);
info->boot_up_nb_voltage =
struct atom_data_revision revision;
int32_t i;
- int32_t j;
if (!info)
return result;
DC_LOG_BIOS("driver forced fixdpvoltageswing = %d\n", info->ext_disp_conn_info.fixdpvoltageswing);
}
}
- /* Sort voltage table from low to high*/
- for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
- for (j = i; j > 0; --j) {
- if (info->disp_clk_voltage[j].max_supported_clk <
- info->disp_clk_voltage[j-1].max_supported_clk)
- swap(info->disp_clk_voltage[j-1], info->disp_clk_voltage[j]);
- }
- }
return result;
}
#define NUMBER_OF_UCHAR_FOR_GUID 16
#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
#define NUMBER_OF_CSR_M3_ARB 10
-#define NUMBER_OF_DISP_CLK_VOLTAGE 4
#define NUMBER_OF_AVAILABLE_SCLK 5
struct i2c_reg_info {
/* V6 */
struct integrated_info {
- struct clock_voltage_caps {
- /* The Voltage Index indicated by FUSE, same voltage index
- shared with SCLK DPM fuse table */
- uint32_t voltage_index;
- /* Maximum clock supported with specified voltage index */
- uint32_t max_supported_clk; /* in KHz */
- } disp_clk_voltage[NUMBER_OF_DISP_CLK_VOLTAGE];
-
struct display_connection_info {
struct external_display_path {
/* A bit vector to show what devices are supported */