arm64: dts: qcom: lemans-evk-ifp-mezzanine: Enable mdss1 display Port

Enable DP controllers, DPTX0 and DPTX1 alongside
their corresponding PHYs of mdss1 which corresponds to eDP2
and eDP3.

Signed-off-by: Vishnu Saini <vishnu.saini@oss.qualcomm.com>
Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260402095003.3758176-4-quic_mkuntuma@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso
index 268fc6b05d4b40f23a1402b92d4bc8c390ec0706..44bd9b1a17652bfc547b2ba502d53d4b511ef20e 100644 (file)
--- a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso
@@ -11,6 +11,30 @@
 &{/} {
        model = "Qualcomm Technologies, Inc. Lemans-evk IFP Mezzanine";
 
+       dp2-connector {
+               compatible = "dp-connector";
+               label = "eDP2";
+               type = "full-size";
+
+               port {
+                       dp2_connector_in: endpoint {
+                               remote-endpoint = <&mdss1_dp0_out>;
+                       };
+               };
+       };
+
+       dp3-connector {
+               compatible = "dp-connector";
+               label = "eDP3";
+               type = "full-size";
+
+               port {
+                       dp3_connector_in: endpoint {
+                               remote-endpoint = <&mdss1_dp1_out>;
+                       };
+               };
+       };
+
        vreg_0p9: regulator-0v9 {
                compatible = "regulator-fixed";
                regulator-name = "VREG_0P9";
@@ -141,6 +165,44 @@
        };
 };
 
+&mdss1 {
+       status = "okay";
+};
+
+&mdss1_dp0 {
+       pinctrl-0 = <&dp2_hot_plug_det>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
+&mdss1_dp1 {
+       pinctrl-0 = <&dp3_hot_plug_det>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
+&mdss1_dp0_out {
+       data-lanes = <0 1 2 3>;
+       link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+       remote-endpoint = <&dp2_connector_in>;
+};
+
+&mdss1_dp1_out {
+       data-lanes = <0 1 2 3>;
+       link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+       remote-endpoint = <&dp3_connector_in>;
+};
+
+&mdss1_dp0_phy {
+       status = "okay";
+};
+
+&mdss1_dp1_phy {
+       status = "okay";
+};
+
 &pcie0 {
        iommu-map = <0x0 &pcie_smmu 0x0 0x1>,
                    <0x100 &pcie_smmu 0x1 0x1>,
@@ -235,6 +297,18 @@
 };
 
 &tlmm {
+       dp2_hot_plug_det: dp2-hot-plug-det-state {
+               pins = "gpio104";
+               function = "edp2_hot";
+               bias-disable;
+       };
+
+       dp3_hot_plug_det: dp3-hot-plug-det-state {
+               pins = "gpio103";
+               function = "edp3_hot";
+               bias-disable;
+       };
+
        ethernet1_default: ethernet1-default-state {
                ethernet1-mdc-pins {
                        pins = "gpio20";