clk: renesas: r9a08g046: Add I2C clocks and resets

Add I2C{0..3} clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260330132349.149391-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c
index 962094157cab38ba5891c0597a723547f31abe73..ce9503c3cfd1e3baf38bf8950fce9b671fb7d17c 100644 (file)
--- a/drivers/clk/renesas/r9a08g046-cpg.c
+++ b/drivers/clk/renesas/r9a08g046-cpg.c
@@ -262,6 +262,14 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
                                        MSTOP(BUS_PERI_COM, BIT(3))),
        DEF_COUPLED("eth1_rx_i_rmii",   R9A08G046_ETH1_CLK_RX_I_RMII, R9A08G046_CLK_ETHRX11, 0x57c, 13,
                                        MSTOP(BUS_PERI_COM, BIT(3))),
+       DEF_MOD("i2c0_pclk",            R9A08G046_I2C0_PCLK, R9A08G046_CLK_P0, 0x580, 0,
+                                       MSTOP(BUS_MCPU2, BIT(10))),
+       DEF_MOD("i2c1_pclk",            R9A08G046_I2C1_PCLK, R9A08G046_CLK_P0, 0x580, 1,
+                                       MSTOP(BUS_MCPU2, BIT(11))),
+       DEF_MOD("i2c2_pclk",            R9A08G046_I2C2_PCLK, R9A08G046_CLK_P0, 0x580, 2,
+                                       MSTOP(BUS_MCPU2, BIT(12))),
+       DEF_MOD("i2c3_pclk",            R9A08G046_I2C3_PCLK, R9A08G046_CLK_P0, 0x580, 3,
+                                       MSTOP(BUS_MCPU2, BIT(13))),
        DEF_MOD("scif0_clk_pck",        R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584, 0,
                                        MSTOP(BUS_MCPU2, BIT(1))),
        DEF_MOD("scif1_clk_pck",        R9A08G046_SCIF1_CLK_PCK, R9A08G046_CLK_P0, 0x584, 1,
@@ -287,6 +295,10 @@ static const struct rzg2l_reset r9a08g046_resets[] = {
        DEF_RST(R9A08G046_WDT0_PRESETN, 0x848, 0),
        DEF_RST(R9A08G046_ETH0_ARESET_N, 0x87c, 0),
        DEF_RST(R9A08G046_ETH1_ARESET_N, 0x87c, 1),
+       DEF_RST(R9A08G046_I2C0_MRST, 0x880, 0),
+       DEF_RST(R9A08G046_I2C1_MRST, 0x880, 1),
+       DEF_RST(R9A08G046_I2C2_MRST, 0x880, 2),
+       DEF_RST(R9A08G046_I2C3_MRST, 0x880, 3),
        DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0),
        DEF_RST(R9A08G046_SCIF1_RST_SYSTEM_N, 0x884, 1),
        DEF_RST(R9A08G046_SCIF2_RST_SYSTEM_N, 0x884, 2),