dc_fixpt_lt(dc_fixpt_one, mantiss))
mantiss = dc_fixpt_zero;
else
- mantiss = dc_fixpt_shl(mantiss, format->mantissa_bits);
+ mantiss = dc_fixpt_shl(mantiss, (unsigned char)format->mantissa_bits);
*mantissa = dc_fixpt_floor(mantiss);
}
calculate_bandwidth(dceip, vbios, data);
- yclk_lvl = data->y_clk_level;
+ yclk_lvl = (uint8_t)data->y_clk_level;
calcs_output->nbp_state_change_enable =
data->nbp_state_change_enable;
uint32_t bios_0_scratch;
uint32_t device_id_mask = 0;
- bp_params.device_id = get_support_mask_for_device_id(
- DEVICE_TYPE_CRT, engine_id == ENGINE_ID_DACB ? 2 : 1);
+ bp_params.device_id = (uint16_t)get_support_mask_for_device_id(
+ DEVICE_TYPE_CRT, engine_id == ENGINE_ID_DACB ? 2 : 1);
if (bp_params.device_id == ATOM_DEVICE_CRT1_SUPPORT)
device_id_mask = ATOM_S0_CRT1_MASK;
info->ss_id = lvds->ucSS_Id;
{
- uint8_t rr = le16_to_cpu(lvds->usSupportedRefreshRate);
+ uint16_t rr = le16_to_cpu(lvds->usSupportedRefreshRate);
/* Get minimum supported refresh rate*/
if (SUPPORTED_LCD_REFRESHRATE_30Hz & rr)
info->supported_rr.REFRESH_RATE_30HZ = 1;
break;
}
- return count;
+ return (uint8_t)count;
}
static struct graphics_object_id bios_parser_get_connector_id(
return BP_RESULT_BADINPUT;
if (id.type == OBJECT_TYPE_GENERIC) {
- dummy_record.i2c_id = id.id;
+ dummy_record.i2c_id = (uint8_t)id.id;
if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK)
return BP_RESULT_OK;
if (!disp_cntl_tbl)
return BP_RESULT_BADBIOSTABLE;
- *dce_caps = disp_cntl_tbl->display_caps;
+ *dce_caps = (uint8_t)disp_cntl_tbl->display_caps;
return result;
}
if (!disp_cntl_tbl)
return BP_RESULT_BADBIOSTABLE;
- *dce_caps = disp_cntl_tbl->display_caps;
+ *dce_caps = (uint8_t)disp_cntl_tbl->display_caps;
return result;
}
if (!disp_cntl_tbl)
return BP_RESULT_BADBIOSTABLE;
- *dce_caps = disp_cntl_tbl->display_caps;
+ *dce_caps = (uint8_t)disp_cntl_tbl->display_caps;
return result;
}
if (!disp_cntl_tbl)
return BP_RESULT_BADBIOSTABLE;
- *dce_caps = disp_cntl_tbl->display_caps;
+ *dce_caps = (uint8_t)disp_cntl_tbl->display_caps;
return result;
}
if (!disp_cntl_tbl)
return BP_RESULT_BADBIOSTABLE;
- *dce_caps = disp_cntl_tbl->display_caps;
+ *dce_caps = (uint8_t)disp_cntl_tbl->display_caps;
return result;
}
info->ext_disp_conn_info.path[i].channel_mapping.raw =
info_v11->extdispconninfo.path[i].channelmapping;
info->ext_disp_conn_info.path[i].caps =
- le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
+ (unsigned short)le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
}
info->ext_disp_conn_info.checksum =
info_v11->extdispconninfo.checksum;
info->ext_disp_conn_info.path[i].channel_mapping.raw =
info_v2_1->extdispconninfo.path[i].channelmapping;
info->ext_disp_conn_info.path[i].caps =
- le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps);
+ (unsigned short)le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps);
}
info->ext_disp_conn_info.checksum =
info->ext_disp_conn_info.path[i].channel_mapping.raw =
info_v2_2->extdispconninfo.path[i].channelmapping;
info->ext_disp_conn_info.path[i].caps =
- le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps);
+ (unsigned short)le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps);
}
info->ext_disp_conn_info.checksum =
if (pixel_clock_10KHz_in != 0) {
bp_params->adjusted_pixel_clock =
- div_u64(pixel_clk * pixel_clk_10_khz_out,
- pixel_clock_10KHz_in);
+ (uint32_t)div_u64(pixel_clk * pixel_clk_10_khz_out,
+ pixel_clock_10KHz_in);
} else {
bp_params->adjusted_pixel_clock = 0;
BREAK_TO_DEBUGGER();
if (pixel_clk_10_kHz_in != 0) {
bp_params->adjusted_pixel_clock =
- div_u64(pixel_clk * pixel_clk_10_khz_out,
- pixel_clk_10_kHz_in);
+ (uint32_t)div_u64(pixel_clk * pixel_clk_10_khz_out,
+ pixel_clk_10_kHz_in);
} else {
bp_params->adjusted_pixel_clock = 0;
BREAK_TO_DEBUGGER();
!cmd->dc_clock_type_to_atom(bp_params->clock_type, &atom_clock_type))
return BP_RESULT_BADINPUT;
- params.asParam.ucDCEClkSrc = atom_pll_id;
- params.asParam.ucDCEClkType = atom_clock_type;
+ params.asParam.ucDCEClkSrc = (uint8_t)atom_pll_id;
+ params.asParam.ucDCEClkType = (uint8_t)atom_clock_type;
if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) {
if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK)
&atom_clock_type))
return BP_RESULT_BADINPUT;
- params.param.dceclksrc = atom_pll_id;
- params.param.dceclktype = atom_clock_type;
+ params.param.dceclksrc = (uint8_t)atom_pll_id;
+ params.param.dceclktype = (uint8_t)atom_clock_type;
if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) {
if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK)
pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
- pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator;
+ pp_display_cfg->crtc_index = (uint8_t)dc->res_pool->res_cap->num_timing_generator;
for (j = 0; j < context->stream_count; j++) {
int k;
num_cfgs++;
cfg->signal = pipe_ctx->stream->signal;
- cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
+ cfg->pipe_idx = (uint8_t)pipe_ctx->stream_res.tg->inst;
cfg->src_height = stream->src.height;
cfg->src_width = stream->src.width;
cfg->ddi_channel_mapping =
pp_display_cfg->line_time_in_us = 0;
}
- pp_display_cfg->display_count = num_cfgs;
+ pp_display_cfg->display_count = (uint8_t)num_cfgs;
}
void dce11_pplib_apply_display_requirements(
if (!bw_params->wm_table.entries[i].valid)
continue;
- ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
- ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;
+ ranges->reader_wm_sets[num_valid_sets].wm_inst =
+ (uint8_t)bw_params->wm_table.entries[i].wm_inst;
+ ranges->reader_wm_sets[num_valid_sets].wm_type =
+ (uint8_t)bw_params->wm_table.entries[i].wm_type;
/* We will not select WM based on fclk, so leave it as unconstrained */
ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
/* add 1 to make it non-overlapping with next lvl */
ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
- ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
+ ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz =
+ (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
} else {
/* unconstrained for memory retraining */
/* Query SMU for all clock states for a particular clock */
-static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels)
+static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, uint8_t *num_levels)
{
- unsigned int i;
+ uint8_t i;
char *entry_i = (char *)entry_0;
uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
void dcn3_init_clocks(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
- unsigned int num_levels;
+ uint8_t num_levels;
memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
clk_mgr_base->clks.p_state_change_support = true;
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
- dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
+ dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
}
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
if (dc->clk_mgr->dc_mode_softmax_enabled &&
new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
- dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
+ (uint16_t)dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
else
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
- clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
+ (uint16_t)clk_mgr_base->bw_params->clk_table.entries[
+ clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
}
}
/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
if (clk_mgr_base->clks.p_state_change_support &&
(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
- dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
+ dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
dpp_clock_lowered = true;
clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
- dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
+ dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
update_dppclk = true;
}
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
- dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
+ dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
update_dispclk = true;
}
static void dcn3_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
{
- unsigned int i;
+ uint8_t i;
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
if (current_mode) {
if (clk_mgr_base->clks.p_state_change_support)
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
- khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
+ (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
else
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
- clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
+ (uint16_t)clk_mgr_base->bw_params->clk_table.entries[
+ clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
} else {
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
- clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
+ (uint16_t)clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
}
}
return;
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
- clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
+ (uint16_t)clk_mgr_base->bw_params->clk_table.entries[
+ clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
}
static void dcn3_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
if (!clk_mgr->smu_present)
return;
- dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
+ dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz);
}
static void dcn3_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
{
if (!clk_mgr->smu_present)
return;
- dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
+ dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz);
}
/* Get current memclk states, update bounding box */
static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
- unsigned int num_levels;
+ uint8_t num_levels;
if (!clk_mgr->smu_present)
return;
if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
- dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));
+ dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));
}
}
static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table)
{
- int i, num_valid_sets;
+ uint8_t i, num_valid_sets;
num_valid_sets = 0;
if (!bw_params->wm_table.entries[i].valid)
continue;
- table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
- table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
+ (uint8_t)bw_params->wm_table.entries[i].wm_inst;
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
+ (uint8_t)bw_params->wm_table.entries[i].wm_type;
/* We will not select WM based on fclk, so leave it as unconstrained */
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
- bw_params->clk_table.entries[i].dcfclk_mhz;
+ (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
} else {
/* unconstrained for memory retraining */
static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
{
struct dc *dc = clk_mgr_base->ctx->dc;
- int i;
+ uint8_t i;
for (i = 0; i < dc->res_pool->pipe_count; ++i) {
struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table)
{
- int i, num_valid_sets;
+ uint8_t i, num_valid_sets;
num_valid_sets = 0;
if (!bw_params->wm_table.entries[i].valid)
continue;
- table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
- table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
+ (uint8_t)bw_params->wm_table.entries[i].wm_inst;
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
+ (uint8_t)bw_params->wm_table.entries[i].wm_type;
/* We will not select WM based on fclk, so leave it as unconstrained */
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
- bw_params->clk_table.entries[i].dcfclk_mhz;
+ (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
} else {
/* unconstrained for memory retraining */
bool safe_to_lower, bool disable)
{
struct dc *dc = clk_mgr_base->ctx->dc;
- int i;
+ uint8_t i;
for (i = 0; i < dc->res_pool->pipe_count; ++i) {
struct pipe_ctx *pipe = safe_to_lower
static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn314_watermarks *table)
{
- int i, num_valid_sets;
+ uint8_t i, num_valid_sets;
num_valid_sets = 0;
if (!bw_params->wm_table.entries[i].valid)
continue;
- table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
- table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
+ (uint8_t)bw_params->wm_table.entries[i].wm_inst;
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
+ (uint8_t)bw_params->wm_table.entries[i].wm_type;
/* We will not select WM based on fclk, so leave it as unconstrained */
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
- bw_params->clk_table.entries[i].dcfclk_mhz;
+ (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
} else {
/* unconstrained for memory retraining */
static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
{
struct dc *dc = clk_mgr_base->ctx->dc;
- int i;
+ uint8_t i;
for (i = 0; i < dc->res_pool->pipe_count; ++i) {
struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn315_watermarks *table)
{
- int i, num_valid_sets;
+ uint8_t i, num_valid_sets;
num_valid_sets = 0;
if (!bw_params->wm_table.entries[i].valid)
continue;
- table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
- table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
+ (uint8_t)bw_params->wm_table.entries[i].wm_inst;
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
+ (uint8_t)bw_params->wm_table.entries[i].wm_type;
/* We will not select WM based on fclk, so leave it as unconstrained */
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
- bw_params->clk_table.entries[i].dcfclk_mhz;
+ (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
} else {
/* unconstrained for memory retraining */
bool safe_to_lower, bool disable)
{
struct dc *dc = clk_mgr_base->ctx->dc;
- int i;
+ uint8_t i;
for (i = 0; i < dc->res_pool->pipe_count; ++i) {
struct pipe_ctx *pipe = safe_to_lower
static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn316_watermarks *table)
{
- int i, num_valid_sets;
+ uint8_t i, num_valid_sets;
num_valid_sets = 0;
if (!bw_params->wm_table.entries[i].valid)
continue;
- table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
- table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
+ (uint8_t)bw_params->wm_table.entries[i].wm_inst;
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
+ (uint8_t)bw_params->wm_table.entries[i].wm_type;
/* We will not select WM based on fclk, so leave it as unconstrained */
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
- bw_params->clk_table.entries[i].dcfclk_mhz;
+ (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
} else {
/* unconstrained for memory retraining */
static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
unsigned int *num_levels)
{
- unsigned int i;
+ uint8_t i;
char *entry_i = (char *)entry_0;
uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
* floored in Mhz to describe the intended clock.
*/
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK,
- khz_to_mhz_floor(temp_dispclk_khz));
+ (uint16_t)khz_to_mhz_floor(temp_dispclk_khz));
if (dc->debug.override_dispclk_programming) {
REG_GET(DENTIST_DISPCLK_CNTL,
* floored in Mhz to describe the intended clock.
*/
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK,
- khz_to_mhz_floor(clk_mgr->base.clks.dispclk_khz));
+ (uint16_t)khz_to_mhz_floor(clk_mgr->base.clks.dispclk_khz));
if (dc->debug.override_dispclk_programming) {
REG_GET(DENTIST_DISPCLK_CNTL,
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) &&
!dc->work_arounds.clock_update_disable_mask.dcfclk) {
clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
- dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
+ dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
}
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) &&
* frequency.
*/
if (dc->debug.disable_dc_mode_overwrite) {
- dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
- dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
+ dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz);
+ dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz);
} else
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
- dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
+ (uint16_t)dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
} else {
- dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
+ dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz);
}
}
}
!dc->work_arounds.clock_update_disable_mask.uclk) {
if (dc->clk_mgr->dc_mode_softmax_enabled && dc->debug.disable_dc_mode_overwrite)
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
- max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)));
+ (uint16_t)max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk,
+ khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)));
- dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
+ dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
}
if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
* floored in Mhz to describe the intended clock.
*/
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK,
- khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz));
+ (uint16_t)khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz));
update_dppclk = true;
}
should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
/* DCCG requires KHz precision for DTBCLK */
clk_mgr_base->clks.ref_dtbclk_khz =
- dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
+ dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, (uint16_t)khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
}
* floored in Mhz to describe the intended clock.
*/
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK,
- khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz));
+ (uint16_t)khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz));
} else {
/* if clock is being raised, increase refclk before lowering DTO */
if (update_dppclk || update_dispclk)
}
static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
{
- unsigned int i;
+ uint8_t i;
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
if (current_mode) {
if (clk_mgr_base->clks.p_state_change_support)
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
- khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
+ (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
else
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
- clk_mgr_base->bw_params->max_memclk_mhz);
+ (uint16_t)clk_mgr_base->bw_params->max_memclk_mhz);
} else {
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
- clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
+ (uint16_t)clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
}
}
if (!clk_mgr->smu_present)
return;
- dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->max_memclk_mhz);
+ dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)clk_mgr_base->bw_params->max_memclk_mhz);
}
/* Get current memclk states, update bounding box */
clk_mgr_base->bw_params->max_memclk_mhz =
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz;
- clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
+ clk_mgr_base->bw_params->clk_table.num_entries = (uint8_t)(num_levels ? num_levels : 1);
if (clk_mgr->dpm_present && !num_levels)
clk_mgr->dpm_present = false;
if (!clk_mgr->smu_present)
return;
- dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
+ dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz);
}
static void dcn32_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
if (!clk_mgr->smu_present)
return;
- dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
+ dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz);
}
static struct clk_mgr_funcs dcn32_funcs = {
bool safe_to_lower, bool disable)
{
struct dc *dc = clk_mgr_base->ctx->dc;
- int i;
+ uint8_t i;
if (dc->ctx->dce_environment == DCE_ENV_DIAG)
return;
continue;
if (idx > dc_struct->links[i]->link_index)
- idx = dc_struct->links[i]->link_index;
+ idx = (uint8_t)dc_struct->links[i]->link_index;
}
return idx;
static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table)
{
- int i, num_valid_sets;
+ uint8_t i, num_valid_sets;
num_valid_sets = 0;
if (!bw_params->wm_table.entries[i].valid)
continue;
- table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
- table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
+ (uint8_t)bw_params->wm_table.entries[i].wm_inst;
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
+ (uint8_t)bw_params->wm_table.entries[i].wm_type;
/* We will not select WM based on fclk, so leave it as unconstrained */
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
- bw_params->clk_table.entries[i].dcfclk_mhz;
+ (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
} else {
/* unconstrained for memory retraining */
/* if the initial message failed, num_levels will be 0 */
for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) {
- *((unsigned int *)entry_i) = (dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
+ *((unsigned int *)entry_i) = (dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, (uint8_t)i) & 0xFFFF);
entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
}
}
static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr)
{
/* For min clocks use as reported by PM FW and report those as min */
- uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz;
- uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
+ unsigned int min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz;
+ unsigned int min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
/* Set A - Normal - default values */
clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true;
clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
- clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
+ clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = (uint16_t)min_dcfclk_mhz;
clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
- clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
+ clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = (uint16_t)min_uclk_mhz;
clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
/* Set B - Unused on dcn4 */
if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = true;
clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
- clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
+ clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = (uint16_t)min_dcfclk_mhz;
clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_dcfclk = 0xFFFF;
- clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = min_uclk_mhz;
+ clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = (uint16_t)min_uclk_mhz;
clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_uclk = 0xFFFF;
} else {
clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = false;
* clock returned is less than requested, then we will ceil the
* requested value to mhz and call it again.
*/
- int actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_floor(requested_clk_khz));
+ int actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, (uint16_t)khz_to_mhz_floor(requested_clk_khz));
if (actual_clk_khz < requested_clk_khz)
- actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_ceil(requested_clk_khz));
+ actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, (uint16_t)khz_to_mhz_ceil(requested_clk_khz));
return actual_clk_khz;
}
clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {
block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DCFCLK;
- block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz);
+ block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz);
block_sequence[num_steps].params.update_hardmin_params.response = NULL;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
num_steps++;
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {
- block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz);
+ block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz);
block_sequence[num_steps].func = CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK;
num_steps++;
}
/* When idle DPM is enabled, need to send active and idle hardmins separately */
/* CLK_MGR401_UPDATE_ACTIVE_HARDMINS */
if ((update_active_uclk || update_active_fclk) && is_idle_dpm_enabled) {
- block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = active_uclk_mhz;
- block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = active_fclk_mhz;
+ block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)active_uclk_mhz;
+ block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)active_fclk_mhz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_ACTIVE_HARDMINS;
num_steps++;
}
/* CLK_MGR401_UPDATE_IDLE_HARDMINS */
if ((update_idle_uclk || update_idle_fclk) && is_idle_dpm_enabled) {
- block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = idle_uclk_mhz;
- block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = idle_fclk_mhz;
+ block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)idle_uclk_mhz;
+ block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)idle_fclk_mhz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_IDLE_HARDMINS;
num_steps++;
}
/* CLK_MGR401_UPDATE_SUBVP_HARDMINS */
if ((update_subvp_prefetch_dramclk || update_subvp_prefetch_fclk) && is_df_throttle_opt_enabled) {
- block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = subvp_prefetch_dramclk_mhz;
- block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = subvp_prefetch_fclk_mhz;
+ block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)subvp_prefetch_dramclk_mhz;
+ block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)subvp_prefetch_fclk_mhz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_SUBVP_HARDMINS;
num_steps++;
}
if (update_active_uclk || update_idle_uclk) {
if (!is_idle_dpm_enabled) {
block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_UCLK;
- block_sequence[num_steps].params.update_hardmin_params.freq_mhz = active_uclk_mhz;
+ block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)active_uclk_mhz;
block_sequence[num_steps].params.update_hardmin_params.response = NULL;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
num_steps++;
dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DTBCLK)) {
/* DCCG requires KHz precision for DTBCLK */
block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DTBCLK;
- block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz);
+ block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz);
block_sequence[num_steps].params.update_hardmin_params.response = &clk_mgr_base->clks.ref_dtbclk_khz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
num_steps++;
/* collect valid ranges, place in pmfw table */
for (i = 0; i < WM_SET_COUNT; i++)
if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
- table->Watermarks.WatermarkRow[i].WmSetting = i;
+ table->Watermarks.WatermarkRow[i].WmSetting = (uint8_t)i;
table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
}
dcn401_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_watermarks *table)
{
- int i, num_valid_sets;
+ uint8_t i, num_valid_sets;
num_valid_sets = 0;
if (!bw_params->wm_table.entries[i].valid)
continue;
- table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
- table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
+ (uint8_t)bw_params->wm_table.entries[i].wm_inst;
+ table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
+ (uint8_t)bw_params->wm_table.entries[i].wm_type;
/* We will not select WM based on fclk, so leave it as unconstrained */
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
- bw_params->clk_table.entries[i].dcfclk_mhz;
+ (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
} else {
/* unconstrained for memory retraining */
* variants of the same card.
*/
for (i = 0; dc->link_count < connectors_num && i < MAX_LINKS; i++) {
- struct graphics_object_id connector_id = bios->funcs->get_connector_id(bios, i);
+ struct graphics_object_id connector_id = bios->funcs->get_connector_id(bios, (uint8_t)i);
struct link_init_data link_init_params = {0};
struct dc_link *link;
link_init_params.ctx = dc->ctx;
/* next BIOS object table connector */
- link_init_params.connector_index = i;
+ link_init_params.connector_index = (uint8_t)i;
link_init_params.link_index = dc->link_count;
link_init_params.dc = dc;
link = dc->link_srv->create_link(&link_init_params);
struct dc_link *link;
link_init_params.ctx = dc->ctx;
- link_init_params.connector_index = i;
+ link_init_params.connector_index = (uint8_t)i;
link_init_params.link_index = dc->link_count;
link_init_params.dc = dc;
link_init_params.is_dpia_link = true;
/* By default, capture the full frame */
param.windowa_x_start = 0;
param.windowa_y_start = 0;
- param.windowa_x_end = pipe->stream->timing.h_addressable;
- param.windowa_y_end = pipe->stream->timing.v_addressable;
+ param.windowa_x_end = (uint16_t)pipe->stream->timing.h_addressable;
+ param.windowa_y_end = (uint16_t)pipe->stream->timing.v_addressable;
param.windowb_x_start = 0;
param.windowb_y_start = 0;
- param.windowb_x_end = pipe->stream->timing.h_addressable;
- param.windowb_y_end = pipe->stream->timing.v_addressable;
+ param.windowb_x_end = (uint16_t)pipe->stream->timing.h_addressable;
+ param.windowb_y_end = (uint16_t)pipe->stream->timing.v_addressable;
param.crc_poly_mode = crc_poly_mode;
if (crc_window) {
stream_mask |= 1 << i;
}
- return stream_mask;
+ return (uint8_t)stream_mask;
}
void dc_z10_restore(const struct dc *dc)
set[i].stream = stream;
if (status) {
- set[i].plane_count = status->plane_count;
+ set[i].plane_count = (uint8_t)status->plane_count;
for (j = 0; j < status->plane_count; j++)
set[i].plane_states[j] = status->plane_states[j];
}
for (i = 0; i < params->stream_count; i++) {
for (j = 0; j < context->stream_count; j++) {
if (params->streams[i]->stream_id == context->streams[j]->stream_id)
- params->streams[i]->out.otg_offset = context->stream_status[j].primary_otg_inst;
+ params->streams[i]->out.otg_offset = (uint8_t)context->stream_status[j].primary_otg_inst;
if (dc_is_embedded_signal(params->streams[i]->signal)) {
struct dc_stream_status *status = dc_state_get_stream_status(context, params->streams[i]);
for (i = 0; i < dc->res_pool->pipe_count; i++)
if (context->res_ctx.pipe_ctx[i].stream == NULL ||
context->res_ctx.pipe_ctx[i].plane_state == NULL) {
- context->res_ctx.pipe_ctx[i].pipe_idx = i;
+ context->res_ctx.pipe_ctx[i].pipe_idx = (uint8_t)i;
dc->hwss.disable_plane(dc, context, &context->res_ctx.pipe_ctx[i]);
}
surface->flip_immediate =
srf_update->flip_addr->flip_immediate;
surface->time.time_elapsed_in_us[surface->time.index] =
- srf_update->flip_addr->flip_timestamp_in_us -
- surface->time.prev_update_time_in_us;
+ (unsigned int)(srf_update->flip_addr->flip_timestamp_in_us -
+ surface->time.prev_update_time_in_us);
surface->time.prev_update_time_in_us =
- srf_update->flip_addr->flip_timestamp_in_us;
+ (unsigned int)srf_update->flip_addr->flip_timestamp_in_us;
surface->time.index++;
if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
surface->time.index = 0;
else
update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1;
- update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
+ update_dirty_rect->dirty_rect_count = (uint8_t)flip_addr->dirty_rect_count;
memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
sizeof(flip_addr->dirty_rects));
for (j = 0; j < dc->res_pool->pipe_count; j++) {
if (pipe_ctx->plane_state != plane_state)
continue;
- update_dirty_rect->panel_inst = panel_inst;
- update_dirty_rect->pipe_idx = j;
- update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst;
+ update_dirty_rect->panel_inst = (uint8_t)panel_inst;
+ update_dirty_rect->pipe_idx = (uint8_t)j;
+ update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
}
}
else
update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1;
- update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
+ update_dirty_rect->dirty_rect_count = (uint8_t)flip_addr->dirty_rect_count;
memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
sizeof(flip_addr->dirty_rects));
for (j = 0; j < dc->res_pool->pipe_count; j++) {
continue;
if (pipe_ctx->plane_state != plane_state)
continue;
- update_dirty_rect->panel_inst = panel_inst;
- update_dirty_rect->pipe_idx = j;
- update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst;
+ update_dirty_rect->panel_inst = (uint8_t)panel_inst;
+ update_dirty_rect->pipe_idx = (uint8_t)j;
+ update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
dc_dmub_cmd[*dmub_cmd_count].dmub_cmd = cmd;
dc_dmub_cmd[*dmub_cmd_count].wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT;
(*dmub_cmd_count)++;
struct dmub_hw_lock_inst_flags inst_flags = { 0 };
hw_locks.bits.lock_dig = 1;
- inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
+ inst_flags.dig_inst = (uint8_t)top_pipe_to_program->stream_res.tg->inst;
dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
true,
struct dmub_hw_lock_inst_flags inst_flags = { 0 };
hw_locks.bits.lock_dig = 1;
- inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
+ inst_flags.dig_inst = (uint8_t)top_pipe_to_program->stream_res.tg->inst;
dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
false,
else
cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC;
- cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst;
+ cmd.dp_aux_access.aux_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;
cmd.dp_aux_access.aux_control.sw_crc_enabled = 0;
cmd.dp_aux_access.aux_control.timeout = 0;
cmd.dp_aux_access.aux_control.dpaux.address = payload->address;
cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux;
- cmd.dp_aux_access.aux_control.dpaux.length = payload->length;
+ cmd.dp_aux_access.aux_control.dpaux.length = (uint8_t)payload->length;
/* set aux action */
if (payload->i2c_over_aux) {
}
if (pipe_ctx)
- otg_inst = pipe_ctx->stream_res.tg->inst;
+ otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
// before enable smart power OLED, we need to call set pipe for DMUB to set ABM config
if (enable) {
sizeof(struct dmub_rb_cmd_smart_power_oled_enable_data) - sizeof(struct dmub_cmd_header);
cmd.smart_power_oled_enable.header.ret_status = 1;
cmd.smart_power_oled_enable.data.enable = enable;
- cmd.smart_power_oled_enable.data.panel_inst = panel_inst;
+ cmd.smart_power_oled_enable.data.panel_inst = (uint8_t)panel_inst;
cmd.smart_power_oled_enable.data.peak_nits = peak_nits;
cmd.smart_power_oled_enable.data.otg_inst = otg_inst;
- cmd.smart_power_oled_enable.data.digfe_inst = link->link_enc->preferred_engine;
- cmd.smart_power_oled_enable.data.digbe_inst = link->link_enc->transmitter;
+ cmd.smart_power_oled_enable.data.digfe_inst = (uint8_t)link->link_enc->preferred_engine;
+ cmd.smart_power_oled_enable.data.digbe_inst = (uint8_t)link->link_enc->transmitter;
cmd.smart_power_oled_enable.data.debugcontrol = debug_control;
cmd.smart_power_oled_enable.data.triggerline = triggerline;
cmd.smart_power_oled_getmaxcll.header.payload_bytes = sizeof(cmd.smart_power_oled_getmaxcll.data);
cmd.smart_power_oled_getmaxcll.header.ret_status = 1;
- cmd.smart_power_oled_getmaxcll.data.input.panel_inst = panel_inst;
+ cmd.smart_power_oled_getmaxcll.data.input.panel_inst = (uint8_t)panel_inst;
// send cmd and wait for reply
status = dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
cmd.set_config_access.header.type = DMUB_CMD__DPIA;
cmd.set_config_access.header.sub_type = DMUB_CMD__DPIA_SET_CONFIG_ACCESS;
- cmd.set_config_access.set_config_control.instance = dc->links[link_index]->ddc_hw_inst;
+ cmd.set_config_access.set_config_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;
cmd.set_config_access.set_config_control.cmd_pkt.msg_type = payload->msg_type;
cmd.set_config_access.set_config_control.cmd_pkt.msg_data = payload->msg_data;
cmd.set_mst_alloc_slots.header.type = DMUB_CMD__DPIA;
cmd.set_mst_alloc_slots.header.sub_type = DMUB_CMD__DPIA_MST_ALLOC_SLOTS;
- cmd.set_mst_alloc_slots.mst_slots_control.instance = dc->links[link_index]->ddc_hw_inst;
+ cmd.set_mst_alloc_slots.mst_slots_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;
cmd.set_mst_alloc_slots.mst_slots_control.mst_alloc_slots = mst_alloc_slots;
if (!dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
cmd.set_tps_notification.header.type = DMUB_CMD__DPIA;
cmd.set_tps_notification.header.sub_type = DMUB_CMD__DPIA_SET_TPS_NOTIFICATION;
- cmd.set_tps_notification.tps_notification.instance = dc->links[link_index]->ddc_hw_inst;
+ cmd.set_tps_notification.tps_notification.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;
cmd.set_tps_notification.tps_notification.tps = tps;
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
switch (pipe_ctx->plane_res.scl_data.format) {
case PIXEL_FORMAT_ARGB8888:
/* set border color to red */
- color->color_r_cr = color_value;
+ color->color_r_cr = (uint16_t)color_value;
if (pipe_ctx->plane_state->layer_index > 0) {
/* set border color to pink */
- color->color_b_cb = color_value;
- color->color_g_y = color_value * 0.5;
+ color->color_b_cb = (uint16_t)color_value;
+ color->color_g_y = (uint16_t)(color_value / 2);
}
break;
case PIXEL_FORMAT_ARGB2101010:
/* set border color to blue */
- color->color_b_cb = color_value;
+ color->color_b_cb = (uint16_t)color_value;
if (pipe_ctx->plane_state->layer_index > 0) {
/* set border color to cyan */
- color->color_g_y = color_value;
+ color->color_g_y = (uint16_t)color_value;
}
break;
case PIXEL_FORMAT_420BPP8:
/* set border color to green */
- color->color_g_y = color_value;
+ color->color_g_y = (uint16_t)color_value;
break;
case PIXEL_FORMAT_420BPP10:
/* set border color to yellow */
- color->color_g_y = color_value;
- color->color_r_cr = color_value;
+ color->color_g_y = (uint16_t)color_value;
+ color->color_r_cr = (uint16_t)color_value;
break;
case PIXEL_FORMAT_FP16:
/* set border color to white */
- color->color_r_cr = color_value;
- color->color_b_cb = color_value;
- color->color_g_y = color_value;
+ color->color_r_cr = (uint16_t)color_value;
+ color->color_b_cb = (uint16_t)color_value;
+ color->color_g_y = (uint16_t)color_value;
if (pipe_ctx->plane_state->layer_index > 0) {
/* set border color to orange */
- color->color_g_y = 0.22 * color_value;
+ color->color_g_y = (uint16_t)((color_value * 22) / 100);
color->color_b_cb = 0;
}
break;
case PIXEL_FORMAT_ARGB2101010:
if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
/* HDR10, ARGB2101010 - set border color to red */
- color->color_r_cr = color_value;
+ color->color_r_cr = (uint16_t)color_value;
} else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
/* FreeSync 2 ARGB2101010 - set border color to pink */
- color->color_r_cr = color_value;
- color->color_b_cb = color_value;
+ color->color_r_cr = (uint16_t)color_value;
+ color->color_b_cb = (uint16_t)color_value;
} else
is_sdr = true;
break;
case PIXEL_FORMAT_FP16:
if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
/* HDR10, FP16 - set border color to blue */
- color->color_b_cb = color_value;
+ color->color_b_cb = (uint16_t)color_value;
} else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
/* FreeSync 2 HDR - set border color to green */
- color->color_g_y = color_value;
+ color->color_g_y = (uint16_t)color_value;
} else
is_sdr = true;
break;
if (is_sdr) {
/* SDR - set border color to Gray */
- color->color_r_cr = color_value/2;
- color->color_b_cb = color_value/2;
- color->color_g_y = color_value/2;
+ color->color_r_cr = (uint16_t)(color_value / 2);
+ color->color_b_cb = (uint16_t)(color_value / 2);
+ color->color_g_y = (uint16_t)(color_value / 2);
}
}
*color = sm_ver_colors[dc->config.smart_mux_version];
} else {
/* dGPU driving the eDP - red */
- color->color_r_cr = color_value;
+ color->color_r_cr = (uint16_t)color_value;
color->color_g_y = 0;
color->color_b_cb = 0;
}
if (edp_link) {
switch (edp_link->backlight_control_type) {
case BACKLIGHT_CONTROL_PWM:
- color->color_r_cr = color_value;
+ color->color_r_cr = (uint16_t)color_value;
color->color_g_y = 0;
color->color_b_cb = 0;
break;
case BACKLIGHT_CONTROL_AMD_AUX:
color->color_r_cr = 0;
- color->color_g_y = color_value;
+ color->color_g_y = (uint16_t)color_value;
color->color_b_cb = 0;
break;
case BACKLIGHT_CONTROL_VESA_AUX:
color->color_r_cr = 0;
color->color_g_y = 0;
- color->color_b_cb = color_value;
+ color->color_b_cb = (uint16_t)color_value;
break;
}
} else {
if (pipe_ctx) {
switch (pipe_ctx->p_state_type) {
case P_STATE_SUB_VP:
- color->color_r_cr = color_value;
+ color->color_r_cr = (uint16_t)color_value;
color->color_g_y = 0;
color->color_b_cb = 0;
break;
case P_STATE_DRR_SUB_VP:
color->color_r_cr = 0;
- color->color_g_y = color_value;
+ color->color_g_y = (uint16_t)color_value;
color->color_b_cb = 0;
break;
case P_STATE_V_BLANK_SUB_VP:
color->color_r_cr = 0;
color->color_g_y = 0;
- color->color_b_cb = color_value;
+ color->color_b_cb = (uint16_t)color_value;
break;
default:
break;
if (pipe_ctx) {
switch (pipe_ctx->p_state_type) {
case P_STATE_V_BLANK:
- color->color_r_cr = color_value;
- color->color_g_y = color_value;
+ color->color_r_cr = (uint16_t)color_value;
+ color->color_g_y = (uint16_t)color_value;
color->color_b_cb = 0;
break;
case P_STATE_FPO:
color->color_r_cr = 0;
- color->color_g_y = color_value;
- color->color_b_cb = color_value;
+ color->color_g_y = (uint16_t)color_value;
+ color->color_b_cb = (uint16_t)color_value;
break;
case P_STATE_V_ACTIVE:
- color->color_r_cr = color_value;
+ color->color_r_cr = (uint16_t)color_value;
color->color_g_y = 0;
- color->color_b_cb = color_value;
+ color->color_b_cb = (uint16_t)color_value;
break;
case P_STATE_SUB_VP:
- color->color_r_cr = color_value;
+ color->color_r_cr = (uint16_t)color_value;
color->color_g_y = 0;
color->color_b_cb = 0;
break;
case P_STATE_DRR_SUB_VP:
color->color_r_cr = 0;
- color->color_g_y = color_value;
+ color->color_g_y = (uint16_t)color_value;
color->color_b_cb = 0;
break;
case P_STATE_V_BLANK_SUB_VP:
color->color_r_cr = 0;
color->color_g_y = 0;
- color->color_b_cb = color_value;
+ color->color_b_cb = (uint16_t)color_value;
break;
default:
break;
uint32_t color_value = MAX_TG_COLOR_VALUE;
if (pipe_ctx->stream && pipe_ctx->stream->cursor_position.enable) {
- color->color_r_cr = color_value;
+ color->color_r_cr = (uint16_t)color_value;
color->color_g_y = 0;
color->color_b_cb = 0;
} else {
color->color_r_cr = 0;
color->color_g_y = 0;
- color->color_b_cb = color_value;
+ color->color_b_cb = (uint16_t)color_value;
}
}
/* driver only handles visual confirm when FAMS2 is disabled */
if (!dc_state_is_fams2_in_use(dc, context)) {
/* when FAMS2 is disabled, all pipes are grey */
- color->color_g_y = color_value / 2;
- color->color_b_cb = color_value / 2;
- color->color_r_cr = color_value / 2;
+ color->color_g_y = (uint16_t)(color_value / 2);
+ color->color_b_cb = (uint16_t)(color_value / 2);
+ color->color_r_cr = (uint16_t)(color_value / 2);
}
}
switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {
case DC_SW_LINEAR:
/* LINEAR Surface - set border color to red */
- color->color_r_cr = color_value;
+ color->color_r_cr = (uint16_t)color_value;
break;
default:
break;
if (max_refresh_rate - min_refresh_rate)
scaling_factor = MAX_TG_COLOR_VALUE * (refresh_rate - min_refresh_rate) / (max_refresh_rate - min_refresh_rate);
- pipe_ctx->visual_confirm_color.color_r_cr = color_value;
- pipe_ctx->visual_confirm_color.color_g_y = scaling_factor;
- pipe_ctx->visual_confirm_color.color_b_cb = color_value;
+ pipe_ctx->visual_confirm_color.color_r_cr = (uint16_t)color_value;
+ pipe_ctx->visual_confirm_color.color_g_y = (uint16_t)scaling_factor;
+ pipe_ctx->visual_confirm_color.color_b_cb = (uint16_t)color_value;
}
}
#endif
case DCE_VERSION_8_0:
res_pool = dce80_create_resource_pool(
- init_data->num_virtual_links, dc);
+ (uint8_t)init_data->num_virtual_links, dc);
break;
case DCE_VERSION_8_1:
res_pool = dce81_create_resource_pool(
- init_data->num_virtual_links, dc);
+ (uint8_t)init_data->num_virtual_links, dc);
break;
case DCE_VERSION_8_3:
res_pool = dce83_create_resource_pool(
- init_data->num_virtual_links, dc);
+ (uint8_t)init_data->num_virtual_links, dc);
break;
case DCE_VERSION_10_0:
res_pool = dce100_create_resource_pool(
- init_data->num_virtual_links, dc);
+ (uint8_t)init_data->num_virtual_links, dc);
break;
case DCE_VERSION_11_0:
res_pool = dce110_create_resource_pool(
- init_data->num_virtual_links, dc,
+ (uint8_t)init_data->num_virtual_links, dc,
init_data->asic_id);
break;
case DCE_VERSION_11_2:
case DCE_VERSION_11_22:
res_pool = dce112_create_resource_pool(
- init_data->num_virtual_links, dc);
+ (uint8_t)init_data->num_virtual_links, dc);
break;
case DCE_VERSION_12_0:
case DCE_VERSION_12_1:
res_pool = dce120_create_resource_pool(
- init_data->num_virtual_links, dc);
+ (uint8_t)init_data->num_virtual_links, dc);
break;
#if defined(CONFIG_DRM_AMD_DC_FP)
pool->hpo_dp_link_enc_count = 0;
if (create_funcs->create_hpo_dp_link_encoder) {
for (i = 0; i < caps->num_hpo_dp_link_encoder; i++) {
- pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder(i, ctx);
+ pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder((uint8_t)i, ctx);
if (pool->hpo_dp_link_enc[i] == NULL)
DC_ERR("DC: failed to create HPO DP link encoder!\n");
pool->hpo_dp_link_enc_count++;
{
uint32_t base60_refresh_rates[] = {10, 20, 5};
uint8_t i;
- uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates);
+ uint8_t rr_count = (uint8_t)ARRAY_SIZE(base60_refresh_rates);
uint64_t frame_time_diff;
if (stream1->ctx->dc->config.vblank_alignment_dto_params &&
int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
- secondary_pipe->pipe_idx = preferred_pipe_idx;
+ secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx;
}
}
for (i = pool->pipe_count - 1; i >= 0; i--) {
if (res_ctx->pipe_ctx[i].stream == NULL) {
secondary_pipe = &res_ctx->pipe_ctx[i];
- secondary_pipe->pipe_idx = i;
+ secondary_pipe->pipe_idx = (uint8_t)i;
break;
}
}
split_pipe->plane_res.ipp = pool->ipps[i];
split_pipe->plane_res.dpp = pool->dpps[i];
split_pipe->stream_res.opp = pool->opps[i];
- split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
- split_pipe->pipe_idx = i;
+ split_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[i]->inst;
+ split_pipe->pipe_idx = (uint8_t)i;
split_pipe->stream = stream;
return i;
pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
if (pool->dpps[id_src[i]]) {
- pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst;
+ pipe_ctx->plane_res.mpcc_inst = (uint8_t)pool->dpps[id_src[i]]->inst;
if (pool->mpc->funcs->read_mpcc_state) {
struct mpcc_state s = {0};
pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
}
}
- pipe_ctx->pipe_idx = id_src[i];
+ pipe_ctx->pipe_idx = (uint8_t)id_src[i];
if (id_src[i] >= pool->timing_generator_count) {
id_src[i] = pool->timing_generator_count - 1;
if (pipe_idx != FREE_PIPE_INDEX_NOT_FOUND) {
pipe_ctx = &new_ctx->res_ctx.pipe_ctx[pipe_idx];
memset(pipe_ctx, 0, sizeof(*pipe_ctx));
- pipe_ctx->pipe_idx = pipe_idx;
+ pipe_ctx->pipe_idx = (uint8_t)pipe_idx;
pipe_ctx->stream_res.tg = pool->timing_generators[pipe_idx];
pipe_ctx->plane_res.mi = pool->mis[pipe_idx];
pipe_ctx->plane_res.hubp = pool->hubps[pipe_idx];
pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx];
pipe_ctx->stream_res.opp = pool->opps[pipe_idx];
if (pool->dpps[pipe_idx])
- pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
+ pipe_ctx->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst;
if (pipe_idx >= pool->timing_generator_count && pool->timing_generator_count != 0) {
int tg_inst = pool->timing_generator_count - 1;
for (i = 0; i <= gamut_packet->sb[1]; i++)
chk_sum += ptr[i];
- gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
+ gamut_packet->sb[2] = (uint8_t)(0x100 - chk_sum);
}
}
/* Y0_Y1_Y2 : The pixel encoding */
/* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
- hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
+ hdmi_info.bits.Y0_Y1_Y2 = (uint8_t)pixel_encoding;
/* A0 = 1 Active Format Information valid */
hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
}
}
/* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
- hdmi_info.bits.VIC0_VIC7 = vic;
+ hdmi_info.bits.VIC0_VIC7 = (uint8_t)vic;
if (vic >= 128)
hdmi_info.bits.header.version = 3;
/* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
hdmi_info.bits.FR0_FR3 = fr_ind & 0xF;
hdmi_info.bits.FR4 = (fr_ind >> 4) & 0x1;
- hdmi_info.bits.RID0_RID5 = rid;
+ hdmi_info.bits.RID0_RID5 = (uint8_t)rid;
}
/* pixel repetition
* barBottom: Line Number of Start of Bottom Bar.
* barLeft: Pixel Number of End of Left Bar.
* barRight: Pixel Number of Start of Right Bar. */
- hdmi_info.bits.bar_top = stream->timing.v_border_top;
+ hdmi_info.bits.bar_top = (uint16_t)stream->timing.v_border_top;
hdmi_info.bits.bar_bottom = (stream->timing.v_total
- stream->timing.v_border_bottom + 1);
- hdmi_info.bits.bar_left = stream->timing.h_border_left;
+ hdmi_info.bits.bar_left = (uint16_t)stream->timing.h_border_left;
hdmi_info.bits.bar_right = (stream->timing.h_total
- stream->timing.h_border_right + 1);
*check_sum += hdmi_info.packet_raw_data.sb[byte_index];
/* one byte complement */
- *check_sum = (uint8_t) (0x100 - *check_sum);
+ *check_sum = (uint8_t)(0x100 - *check_sum);
/* Store in hw_path_mode */
info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
sec_pipe->next_odm_pipe = sec_next;
sec_pipe->prev_odm_pipe = sec_prev;
- sec_pipe->pipe_idx = pipe_idx;
+ sec_pipe->pipe_idx = (uint8_t)pipe_idx;
sec_pipe->plane_res.mi = pool->mis[pipe_idx];
sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
- sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
+ sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst;
sec_pipe->stream_res.dsc = NULL;
if (odm) {
if (!sec_pipe->top_pipe)
struct dc *dc,
struct dc_stream_state *stream)
{
- int i;
+ uint8_t i;
struct resource_context *res_ctx;
struct pipe_ctx *pipe_to_program = NULL;
bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);
struct dc *dc,
struct dc_stream_state *stream)
{
- int i;
+ uint8_t i;
struct resource_context *res_ctx;
struct pipe_ctx *pipe_to_program = NULL;
bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);
int refresh_hz)
{
long long slope = 0;
+ long long y_intercept = 0;
+ long long brightness_millinits = 0;
+
if (stream->lumin_data.refresh_rate_hz[index2] != stream->lumin_data.refresh_rate_hz[index1]) {
slope = (stream->lumin_data.luminance_millinits[index2] - stream->lumin_data.luminance_millinits[index1]) /
(stream->lumin_data.refresh_rate_hz[index2] - stream->lumin_data.refresh_rate_hz[index1]);
}
- int y_intercept = stream->lumin_data.luminance_millinits[index2] - slope * stream->lumin_data.refresh_rate_hz[index2];
+ y_intercept = stream->lumin_data.luminance_millinits[index2] - slope * stream->lumin_data.refresh_rate_hz[index2];
+ brightness_millinits = y_intercept + (long long)refresh_hz * slope;
- return (y_intercept + refresh_hz * slope);
+ return (int)brightness_millinits;
}
/*
int brightness_millinits)
{
long long slope = 1;
+ long long y_intercept = 0;
+ long long refresh_hz = 0;
+
if (stream->lumin_data.refresh_rate_hz[index2] != stream->lumin_data.refresh_rate_hz[index1]) {
slope = (stream->lumin_data.luminance_millinits[index2] - stream->lumin_data.luminance_millinits[index1]) /
(stream->lumin_data.refresh_rate_hz[index2] - stream->lumin_data.refresh_rate_hz[index1]);
}
- int y_intercept = stream->lumin_data.luminance_millinits[index2] - slope * stream->lumin_data.refresh_rate_hz[index2];
+ y_intercept = stream->lumin_data.luminance_millinits[index2] - slope * stream->lumin_data.refresh_rate_hz[index2];
+ refresh_hz = div64_s64((brightness_millinits - y_intercept), slope);
- return ((int)div64_s64((brightness_millinits - y_intercept), slope));
+ return (int)refresh_hz;
}
/*
struct pipe_ctx *pipe_ctx = &dc_state->res_ctx.pipe_ctx[i];
if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp)
- pipe_mask |= 1 << pipe_ctx->plane_res.hubp->inst;
+ pipe_mask |= (uint8_t)(1 << pipe_ctx->plane_res.hubp->inst);
}
return pipe_mask;
return false;
}
- return boot_status.bits.optimized_init_done;
+ return (bool)boot_status.bits.optimized_init_done;
}
bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
return false;
return dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,
- stream_mask, NULL, DM_DMUB_WAIT_TYPE_WAIT);
+ (uint16_t)stream_mask, NULL, DM_DMUB_WAIT_TYPE_WAIT);
}
bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)
return false;
}
- return boot_status.bits.restore_required;
+ return (bool)boot_status.bits.restore_required;
}
bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)
static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream)
{
uint8_t pipes = 0;
- int i = 0;
+ uint8_t i = 0;
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
int j;
int pipe_idx = 0;
- fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst;
+ fams_pipe_data->pipe_index[pipe_idx++] = (uint8_t)head_pipe->plane_res.hubp->inst;
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j];
if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) {
- fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst;
+ fams_pipe_data->pipe_index[pipe_idx++] = (uint8_t)split_pipe->plane_res.hubp->inst;
}
}
- fams_pipe_data->pipe_count = pipe_idx;
+ fams_pipe_data->pipe_count = (uint8_t)pipe_idx;
}
bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context)
if (dc == NULL)
return false;
- visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS;
+ visual_confirm_enabled = (uint8_t)(dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS);
// Format command.
cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
*/
stream_status = dc_state_get_stream_status(context, pipe->stream);
if (stream_status && !stream_status->fpo_in_use) {
- cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us;
+ cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us =
+ (uint16_t)dc->debug.fpo_vactive_margin_us;
break;
}
}
stream_status = dc_state_get_stream_status(context, pipe->stream);
if (stream_status && stream_status->fpo_in_use) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
- uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000;
+ uint8_t min_refresh_in_hz;
+
+ min_refresh_in_hz = (uint8_t)((pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000);
config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz;
config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz;
- config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps;
+ config_data->pipe_data[k].max_ramp_step = (uint8_t)ramp_up_num_steps;
config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream);
dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]);
k++;
cmd.visual_confirm_color.header.sub_type = 0;
cmd.visual_confirm_color.header.ret_status = 1;
cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data);
- cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst;
+ cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = (uint16_t)panel_inst;
// If command was processed, copy feature caps to dmub srv
if (dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
struct dc_crtc_timing *phantom_timing;
struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing;
- uint16_t drr_frame_us = 0;
- uint16_t min_drr_supported_us = 0;
- uint16_t max_drr_supported_us = 0;
- uint16_t max_drr_vblank_us = 0;
- uint16_t max_drr_mallregion_us = 0;
- uint16_t mall_region_us = 0;
- uint16_t prefetch_us = 0;
- uint16_t subvp_active_us = 0;
- uint16_t drr_active_us = 0;
- uint16_t min_vtotal_supported = 0;
- uint16_t max_vtotal_supported = 0;
+ uint64_t drr_frame_us = 0;
+ uint64_t min_drr_supported_us = 0;
+ uint64_t max_drr_supported_us = 0;
+ uint64_t max_drr_vblank_us = 0;
+ uint64_t max_drr_mallregion_us = 0;
+ uint64_t mall_region_us = 0;
+ uint64_t prefetch_us = 0;
+ uint64_t subvp_active_us = 0;
+ uint64_t drr_active_us = 0;
+ uint64_t min_vtotal_supported = 0;
+ uint64_t max_vtotal_supported = 0;
if (!phantom_stream)
return;
*/
max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us;
- pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;
- pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;
- pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us;
+ pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = (uint16_t)min_vtotal_supported;
+ pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = (uint16_t)max_vtotal_supported;
+ pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin =
+ (uint16_t)dc->caps.subvp_drr_vblank_start_margin_us;
}
/**
pipe_data->mode = VBLANK;
pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz;
- pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total -
- vblank_pipe->stream->timing.v_front_porch;
- pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total;
- pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total;
+ pipe_data->pipe_config.vblank_data.vblank_start = (uint16_t)(vblank_pipe->stream->timing.v_total -
+ vblank_pipe->stream->timing.v_front_porch);
+ pipe_data->pipe_config.vblank_data.vtotal = (uint16_t)vblank_pipe->stream->timing.v_total;
+ pipe_data->pipe_config.vblank_data.htotal = (uint16_t)vblank_pipe->stream->timing.h_total;
pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx;
- pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start;
+ pipe_data->pipe_config.vblank_data.vstartup_start = (uint16_t)vblank_pipe->pipe_dlg_param.vstartup_start;
pipe_data->pipe_config.vblank_data.vblank_end =
vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable;
phantom_timing0 = &phantom_stream0->timing;
phantom_timing1 = &phantom_stream1->timing;
- subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) *
+ subvp0_prefetch_us = (uint32_t)div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) *
(uint64_t)phantom_timing0->h_total * 1000000),
(((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
- subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) *
+ subvp1_prefetch_us = (uint32_t)div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) *
(uint64_t)phantom_timing1->h_total * 1000000),
(((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
if (subvp0_prefetch_us > subvp1_prefetch_us) {
pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1];
prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us;
- pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
- div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
+pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
+ (uint16_t)div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)),
((uint64_t)phantom_timing1->h_total * 1000000));
pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0];
prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us;
pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
- div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
+ (uint16_t)div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)),
((uint64_t)phantom_timing0->h_total * 1000000));
}
pipe_data->mode = SUBVP;
pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz;
- pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total;
- pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total;
+ pipe_data->pipe_config.subvp_data.htotal = (uint16_t)subvp_pipe->stream->timing.h_total;
+ pipe_data->pipe_config.subvp_data.vtotal = (uint16_t)subvp_pipe->stream->timing.v_total;
pipe_data->pipe_config.subvp_data.main_vblank_start =
- main_timing->v_total - main_timing->v_front_porch;
+ (uint16_t)(main_timing->v_total - main_timing->v_front_porch);
pipe_data->pipe_config.subvp_data.main_vblank_end =
- main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable;
- pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable;
- pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst;
+ (uint16_t)(main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable);
+ pipe_data->pipe_config.subvp_data.mall_region_lines = (uint16_t)phantom_timing->v_addressable;
+ pipe_data->pipe_config.subvp_data.main_pipe_index = (uint8_t)subvp_pipe->stream_res.tg->inst;
pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param &&
(subvp_pipe->stream->allow_freesync || subvp_pipe->stream->vrr_active_variable || subvp_pipe->stream->vrr_active_fixed);
reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height,
&out_num_plane, &out_den_plane);
reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den);
- pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num;
- pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den;
+ pipe_data->pipe_config.subvp_data.scale_factor_numerator = (uint8_t)out_num;
+ pipe_data->pipe_config.subvp_data.scale_factor_denominator = (uint8_t)out_den;
// Prefetch lines is equal to VACTIVE + BP + VSYNC
pipe_data->pipe_config.subvp_data.prefetch_lines =
// Round up
pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
- div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
+ (uint16_t)div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
pipe_data->pipe_config.subvp_data.processing_delay_lines =
- div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
+ (uint16_t)div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
if (subvp_pipe->bottom_pipe) {
- pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx;
+ pipe_data->pipe_config.subvp_data.main_split_pipe_index = (uint8_t)subvp_pipe->bottom_pipe->pipe_idx;
} else if (subvp_pipe->next_odm_pipe) {
- pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx;
+ pipe_data->pipe_config.subvp_data.main_split_pipe_index = (uint8_t)subvp_pipe->next_odm_pipe->pipe_idx;
} else {
pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0xF;
}
if (resource_is_pipe_type(phantom_pipe, OTG_MASTER) &&
phantom_pipe->stream == dc_state_get_paired_subvp_stream(context, subvp_pipe->stream)) {
- pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst;
+ pipe_data->pipe_config.subvp_data.phantom_pipe_index = (uint8_t)phantom_pipe->stream_res.tg->inst;
if (phantom_pipe->bottom_pipe) {
- pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst;
+ pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = (uint8_t)phantom_pipe->bottom_pipe->plane_res.hubp->inst;
} else if (phantom_pipe->next_odm_pipe) {
- pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst;
+ pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = (uint8_t)phantom_pipe->next_odm_pipe->plane_res.hubp->inst;
} else {
pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0xF;
}
if (subvp_count == 2) {
update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes);
}
- cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
- cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us;
+ cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = (uint8_t)dc->caps.subvp_pstate_allow_width_us;
+ cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = (uint8_t)dc->caps.subvp_vertical_int_margin_us;
// Store the original watermark value for this SubVP config so we can lower it when the
// MCLK switch starts
wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns *
(dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000;
- cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF;
+ cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = (uint16_t)(wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF);
}
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
payload->cursor_rect.width = hubp->cur_rect.w;
payload->cursor_rect.height = hubp->cur_rect.h;
- payload->enable = hubp->pos.cur_ctl.bits.cur_enable;
+ payload->enable = (uint8_t)hubp->pos.cur_ctl.bits.cur_enable;
payload->pipe_idx = p_idx;
- payload->panel_inst = panel_inst;
- payload->otg_inst = pipe_ctx->stream_res.tg->inst;
+ payload->panel_inst = (uint8_t)panel_inst;
+ payload->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
}
static void dc_build_cursor_position_update_payload0(
if (dc_dmub_srv->dmub->shared_state &&
dc_dmub_srv->dmub->meta_info.feature_bits.bits.shared_state_link_detection) {
ips_fw = &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw;
- return ips_fw->signals.bits.detection_required;
+ return (bool)ips_fw->signals.bits.detection_required;
}
/* Detection may require reading scratch 0 - exit out of idle prior to the read. */
cmd.fams2_drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
cmd.fams2_drr_update.header.sub_type = DMUB_CMD__FAMS2_DRR_UPDATE;
- cmd.fams2_drr_update.dmub_optc_state_req.tg_inst = tg_inst;
+ cmd.fams2_drr_update.dmub_optc_state_req.tg_inst = (uint8_t)tg_inst;
cmd.fams2_drr_update.dmub_optc_state_req.v_total_max = vtotal_max;
cmd.fams2_drr_update.dmub_optc_state_req.v_total_min = vtotal_min;
cmd.fams2_drr_update.dmub_optc_state_req.v_total_mid = vtotal_mid;
cmds[num_cmds].fams2_flip.header.multi_cmd_pending = 1;
/* set topology info */
- cmds[num_cmds].fams2_flip.flip_info.pipe_mask = dc_plane_get_pipe_mask(state, plane_state);
- if (stream_status)
- cmds[num_cmds].fams2_flip.flip_info.otg_inst = stream_status->primary_otg_inst;
-
+ cmds[num_cmds].fams2_flip.flip_info.pipe_mask = (uint8_t)dc_plane_get_pipe_mask(state, plane_state);
+ if (stream_status) {
+ cmds[num_cmds].fams2_flip.flip_info.otg_inst = (uint8_t)stream_status->primary_otg_inst;
+ }
cmds[num_cmds].fams2_flip.flip_info.config.bits.is_immediate = plane_state->flip_immediate;
/* build address info for command */
req->type = type;
loc->is_aux = false;
- loc->ddc_line = ddc_line;
+ loc->ddc_line = (uint8_t)ddc_line;
loc->over_aux = over_aux;
loc->address = op->address;
loc->offset = op->offset;
- loc->length = op->size;
+ loc->length = (uint8_t)op->size;
memcpy(req->buffer, op->data, op->size);
return true;
timeout_us += timeout_per_aux_transaction_us * (io->request.u.aux.length / 16);
}
- if (!dm_helpers_execute_fused_io(link->ctx, link, commands, count, timeout_us))
+ if (!dm_helpers_execute_fused_io(link->ctx, link, commands, count, (uint32_t)timeout_us))
return false;
return commands[0].fused_io.request.status == FUSED_REQUEST_STATUS_SUCCESS;
field_value = va_arg(ap, uint32_t);
set_reg_field_value_masks(field_value_mask,
- field_value, mask, shift);
+ field_value, mask, (uint8_t)shift);
i++;
}
}
reg_val = dm_read_reg(ctx, addr);
- field_value = get_reg_field_value_ex(reg_val, mask, shift);
+ field_value = get_reg_field_value_ex(reg_val, mask, (uint8_t)shift);
if (field_value == condition_value) {
if (i * delay_between_poll_us > 1000)
mask = va_arg(ap, uint32_t);
field_value = va_arg(ap, uint32_t *);
- *field_value = get_reg_field_value_ex(value, mask, shift);
+ *field_value = get_reg_field_value_ex(value, mask, (uint8_t)shift);
i++;
}
mask = va_arg(ap, uint32_t);
field_value = va_arg(ap, uint32_t);
- reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);
+ reg_val = set_reg_field_value_ex(reg_val, field_value, mask, (uint8_t)shift);
i++;
}
mask = va_arg(ap, uint32_t);
field_value = va_arg(ap, uint32_t);
- reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);
+ reg_val = set_reg_field_value_ex(reg_val, field_value, mask, (uint8_t)shift);
i++;
}
mask = va_arg(ap, uint32_t);
field_value = va_arg(ap, uint32_t *);
- *field_value = get_reg_field_value_ex(value, mask, shift);
+ *field_value = get_reg_field_value_ex(value, mask, (uint8_t)shift);
i++;
}
// phase / modulo = dtbclk / dtbclk ref
modulo = params->ref_dtbclk_khz * 1000;
- phase = div_u64((((unsigned long long)modulo * req_dtbclk_khz) + params->ref_dtbclk_khz - 1),
+ phase = (uint32_t)div_u64((((unsigned long long)modulo * req_dtbclk_khz) + params->ref_dtbclk_khz - 1),
params->ref_dtbclk_khz);
REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
// phase / modulo = dtbclk / dtbclk ref
modulo = params->ref_dtbclk_khz * 1000;
- phase = div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1),
+ phase = (uint32_t)div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1),
params->ref_dtbclk_khz);
* int = target_pix_rate / reference_clock
* phase = target_pix_rate - int * reference_clock,
* modulo = reference_clock */
- dto_integer = div_u64(params->pixclk_hz, dto_modulo_hz);
+
+ /* dto_modulo_hz = refclk (~100 MHz), well within uint32_t range */
+ dto_integer = div_u64(params->pixclk_hz, (uint32_t)dto_modulo_hz);
dto_phase_hz = params->pixclk_hz - dto_integer * dto_modulo_hz;
- if (dto_phase_hz <= 0 && dto_integer <= 0) {
- /* negative pixel rate should never happen */
+ if (dto_phase_hz == 0 && dto_integer == 0) {
+ /* zero pixel rate should never happen */
BREAK_TO_DEBUGGER();
return;
}
dccg401_set_dtbclk_p_src(dccg, params->clk_src, params->otg_inst);
- REG_WRITE(DP_DTO_PHASE[params->otg_inst], dto_phase_hz);
- REG_WRITE(DP_DTO_MODULO[params->otg_inst], dto_modulo_hz);
+ REG_WRITE(DP_DTO_PHASE[params->otg_inst], (uint32_t)dto_phase_hz);
+ REG_WRITE(DP_DTO_MODULO[params->otg_inst], (uint32_t)dto_modulo_hz);
switch (params->otg_inst) {
case 0:
REG_UPDATE(OTG_PIXEL_RATE_DIV,
- DPDTO0_INT, dto_integer);
+ DPDTO0_INT, (uint32_t)dto_integer);
break;
case 1:
REG_UPDATE(OTG_PIXEL_RATE_DIV,
- DPDTO1_INT, dto_integer);
+ DPDTO1_INT, (uint32_t)dto_integer);
break;
case 2:
REG_UPDATE(OTG_PIXEL_RATE_DIV,
- DPDTO2_INT, dto_integer);
+ DPDTO2_INT, (uint32_t)dto_integer);
break;
case 3:
REG_UPDATE(OTG_PIXEL_RATE_DIV,
- DPDTO3_INT, dto_integer);
+ DPDTO3_INT, (uint32_t)dto_integer);
break;
default:
BREAK_TO_DEBUGGER();
uint32_t aux_sw_data_val;
REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val);
- buffer[i] = aux_sw_data_val;
+ buffer[i] = (uint8_t)aux_sw_data_val;
++i;
}
(value & AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK))
return AUX_RET_ERROR_INVALID_REPLY;
- *returned_bytes = get_reg_field_value(value,
+ *returned_bytes = (uint8_t)get_reg_field_value(value,
AUX_SW_STATUS,
AUX_SW_REPLY_BYTE_COUNT);
feedback_divider *= (uint64_t)
(calc_pll_cs->fract_fb_divider_precision_factor);
- *feedback_divider_param =
- div_u64_rem(
- feedback_divider,
- calc_pll_cs->fract_fb_divider_factor,
- fract_feedback_divider_param);
+ *feedback_divider_param = (uint32_t)div_u64_rem(
+ feedback_divider, calc_pll_cs->fract_fb_divider_factor,
+ fract_feedback_divider_param);
if (*feedback_divider_param != 0)
return true;
pll_settings->calculated_pix_clk_100hz =
actual_calculated_clock_100hz;
pll_settings->vco_freq =
- div_u64((u64)actual_calculated_clock_100hz * post_divider, 10);
+ (uint32_t)div_u64((u64)actual_calculated_clock_100hz * post_divider, 10);
return true;
}
return false;
bp_adjust_pixel_clock_params.
encoder_object_id = pix_clk_params->encoder_object_id;
bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
- bp_adjust_pixel_clock_params.
- ss_enable = pix_clk_params->flags.ENABLE_SS;
+ bp_adjust_pixel_clock_params.ss_enable = pix_clk_params->flags.ENABLE_SS != 0;
bp_result = clk_src->bios->funcs->adjust_pixel_clock(
clk_src->bios, &bp_adjust_pixel_clock_params);
if (bp_result == BP_RESULT_OK) {
dce112_program_pixel_clk_resync(clk_src,
pix_clk_params->signal_type,
pix_clk_params->color_depth,
- pix_clk_params->flags.SUPPORT_YCBCR420);
+ pix_clk_params->flags.SUPPORT_YCBCR420 != 0);
return true;
}
dce112_program_pixel_clk_resync(clk_src,
pix_clk_params->signal_type,
pix_clk_params->color_depth,
- pix_clk_params->flags.SUPPORT_YCBCR420);
+ pix_clk_params->flags.SUPPORT_YCBCR420 != 0);
}
return true;
dce112_program_pixel_clk_resync(clk_src,
pix_clk_params->signal_type,
pix_clk_params->color_depth,
- pix_clk_params->flags.SUPPORT_YCBCR420);
+ pix_clk_params->flags.SUPPORT_YCBCR420 != 0);
}
return true;
*/
modulo_hz = REG_READ(MODULO[inst]);
if (modulo_hz)
- *pixel_clk_khz = div_u64((uint64_t)clock_hz*
- dp_dto_ref_khz*10,
- modulo_hz);
+ *pixel_clk_khz = (unsigned int)div_u64((uint64_t)clock_hz *
+ dp_dto_ref_khz * 10, modulo_hz);
else
*pixel_clk_khz = 0;
} else {
uint32_t i2c_data;
REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data);
- *buffer++ = i2c_data;
+ *buffer++ = (uint8_t)i2c_data;
--length;
}
if (pwm_period_bitcnt == 0)
bit_count = 16;
else
- bit_count = pwm_period_bitcnt;
+ bit_count = (uint8_t)pwm_period_bitcnt;
/* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */
masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1);
* components shift by bitCount then mask 16 bits and add rounding bit
* from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0
*/
- backlight_16bit = active_duty_cycle >> bit_count;
+ backlight_16bit = (uint32_t)(active_duty_cycle >> bit_count);
backlight_16bit &= 0xFFFF;
backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1;
ASSERT(depth <= COLOR_DEPTH_121212); /* Invalid clamp bit depth */
- spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED;
+ spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED != 0;
/* Default to 12 bit truncation without rounding */
trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_12BIT;
trunc_mode = DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE;
spatial_dither_enable,
DCP_SPATIAL_DITHER_MODE_A_AA_A,
DCP_SPATIAL_DITHER_DEPTH_30BPP,
- bit_depth_params->flags.FRAME_RANDOM,
- bit_depth_params->flags.RGB_RANDOM,
- bit_depth_params->flags.HIGHPASS_RANDOM);
+ bit_depth_params->flags.FRAME_RANDOM != 0,
+ bit_depth_params->flags.RGB_RANDOM != 0,
+ bit_depth_params->flags.HIGHPASS_RANDOM != 0);
}
#if defined(CONFIG_DRM_AMD_DC_SI)
cmd.abm_init_config.header.type = DMUB_CMD__ABM;
cmd.abm_init_config.header.sub_type = DMUB_CMD__ABM_INIT_CONFIG;
cmd.abm_init_config.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr;
- cmd.abm_init_config.abm_init_config_data.bytes = bytes;
+ cmd.abm_init_config.abm_init_config_data.bytes = (uint16_t)bytes;
cmd.abm_init_config.abm_init_config_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1;
cmd.abm_init_config.abm_init_config_data.panel_mask = panel_mask;
cmd.abm_save_restore.header.sub_type = DMUB_CMD__ABM_SAVE_RESTORE;
cmd.abm_save_restore.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr;
- cmd.abm_save_restore.abm_init_config_data.bytes = bytes;
+ cmd.abm_save_restore.abm_init_config_data.bytes = (uint16_t)bytes;
cmd.abm_save_restore.abm_init_config_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1;
cmd.abm_save_restore.abm_init_config_data.panel_mask = panel_mask;
memset(&cmd, 0, sizeof(cmd));
cmd.abm_set_pipe.header.type = DMUB_CMD__ABM;
cmd.abm_set_pipe.header.sub_type = DMUB_CMD__ABM_SET_PIPE;
- cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst;
- cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = pwrseq_inst;
- cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = option;
- cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = panel_inst;
+ cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = (uint8_t)otg_inst;
+ cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = (uint8_t)pwrseq_inst;
+ cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = (uint8_t)option;
+ cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = (uint8_t)panel_inst;
cmd.abm_set_pipe.abm_set_pipe_data.ramping_boundary = ramping_boundary;
cmd.abm_set_pipe.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pipe_data);
memset(&cmd, 0, sizeof(cmd));
cmd.abm_set_event.header.type = DMUB_CMD__ABM;
cmd.abm_set_event.header.sub_type = DMUB_CMD__ABM_SET_EVENT;
- cmd.abm_set_event.abm_set_event_data.vb_scaling_enable = scaling_enable;
+ cmd.abm_set_event.abm_set_event_data.vb_scaling_enable = (uint8_t)scaling_enable;
cmd.abm_set_event.abm_set_event_data.vb_scaling_strength_mapping = scaling_strength_map;
cmd.abm_set_event.abm_set_event_data.panel_mask = (1<<panel_inst);
cmd.abm_set_event.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_event_data);
copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
if (pipe_ctx->plane_res.dpp)
- copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;
+ copy_settings_data->dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst;
else
copy_settings_data->dpp_inst = 0;
if (pipe_ctx->stream_res.opp)
- copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst;
+ copy_settings_data->opp_inst = (uint8_t)pipe_ctx->stream_res.opp->inst;
else
copy_settings_data->opp_inst = 0;
if (pipe_ctx->stream_res.tg)
- copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst;
+ copy_settings_data->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
else
copy_settings_data->otg_inst = 0;
// Misc
copy_settings_data->use_phy_fsm = link->ctx->dc->debug.psr_power_use_phy_fsm;
- copy_settings_data->psr_level = psr_context->psr_level.u32all;
+ copy_settings_data->psr_level = (uint16_t)psr_context->psr_level.u32all;
copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations;
copy_settings_data->multi_disp_optimizations_en = psr_context->allow_multi_disp_optimizations;
- copy_settings_data->frame_delay = psr_context->frame_delay;
+ copy_settings_data->frame_delay = (uint8_t)psr_context->frame_delay;
copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq;
- copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline;
+ copy_settings_data->init_sdp_deadline = (uint16_t)psr_context->sdpTransmitLineNumDeadline;
copy_settings_data->debug.u32All = 0;
copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;
copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1;
copy_settings_data->digfe_inst = replay_context->digfe_inst;
if (pipe_ctx->plane_res.dpp)
- copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;
+ copy_settings_data->dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst;
else
copy_settings_data->dpp_inst = 0;
+
if (pipe_ctx->stream_res.tg)
- copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst;
+ copy_settings_data->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
else
copy_settings_data->otg_inst = 0;
copy_settings_data->dpphy_inst = link->link_enc->transmitter;
// Misc
- copy_settings_data->line_time_in_ns = replay_context->line_time_in_ns;
- copy_settings_data->panel_inst = panel_inst;
- copy_settings_data->debug.u32All = link->replay_settings.config.debug_flags;
+ copy_settings_data->line_time_in_ns = (uint16_t)replay_context->line_time_in_ns;
+ copy_settings_data->panel_inst = (uint16_t)panel_inst;
+ copy_settings_data->debug.u32All = (uint16_t)link->replay_settings.config.debug_flags;
copy_settings_data->pixel_deviation_per_line = link->dpcd_caps.pr_info.pixel_deviation_per_line;
- copy_settings_data->max_deviation_line = link->dpcd_caps.pr_info.max_deviation_line;
+ copy_settings_data->max_deviation_line = (uint16_t)link->dpcd_caps.pr_info.max_deviation_line;
copy_settings_data->smu_optimizations_en = link->replay_settings.replay_smu_opt_enable;
copy_settings_data->replay_timing_sync_supported = link->replay_settings.config.replay_timing_sync_supported;
copy_settings_data->replay_support_fast_resync_in_ultra_sleep_mode = link->replay_settings.config.replay_support_fast_resync_in_ultra_sleep_mode;
copy_settings_data->flags.bitfields.alpm_mode = (enum dmub_alpm_mode)link->replay_settings.config.alpm_mode;
if (link->replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) {
- copy_settings_data->auxless_alpm_data.lfps_setup_ns = dc->dc->debug.auxless_alpm_lfps_setup_ns;
- copy_settings_data->auxless_alpm_data.lfps_period_ns = dc->dc->debug.auxless_alpm_lfps_period_ns;
- copy_settings_data->auxless_alpm_data.lfps_silence_ns = dc->dc->debug.auxless_alpm_lfps_silence_ns;
+ copy_settings_data->auxless_alpm_data.lfps_setup_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_setup_ns;
+ copy_settings_data->auxless_alpm_data.lfps_period_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_period_ns;
+ copy_settings_data->auxless_alpm_data.lfps_silence_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_silence_ns;
copy_settings_data->auxless_alpm_data.lfps_t1_t2_override_us =
- dc->dc->debug.auxless_alpm_lfps_t1t2_us;
+ (uint16_t)dc->dc->debug.auxless_alpm_lfps_t1t2_us;
copy_settings_data->auxless_alpm_data.lfps_t1_t2_offset_us =
- dc->dc->debug.auxless_alpm_lfps_t1t2_offset_us;
+ (uint16_t)dc->dc->debug.auxless_alpm_lfps_t1t2_offset_us;
copy_settings_data->auxless_alpm_data.lttpr_count = link->dc->link_srv->dp_get_lttpr_count(link);
}
set_reg_field_value(
value,
- pix_dur,
+ (uint32_t)pix_dur,
DPG_PIPE_ARBITRATION_CONTROL1,
PIXEL_DURATION);
csc_c11, ®val0,
csc_c12, ®val1);
- regval[2 * i] = regval0;
- regval[(2 * i) + 1] = regval1;
+ regval[2 * i] = (uint16_t)regval0;
+ regval[(2 * i) + 1] = (uint16_t)regval1;
i++;
}
struct dcn30_mmhubbub *mcif_wb30 = TO_DCN30_MMHUBBUB(mcif_wb);
/* buffer address for packing mode or Luma in planar mode */
- REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0]));
+ REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, (uint32_t)MCIF_ADDR(params->luma_address[0]));
REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[0]));
/* buffer address for Chroma in planar mode (unused in packing mode) */
- REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0]));
+ REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, (uint32_t)MCIF_ADDR(params->chroma_address[0]));
REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[0]));
/* buffer address for packing mode or Luma in planar mode */
- REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1]));
+ REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, (uint32_t)MCIF_ADDR(params->luma_address[1]));
REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[1]));
/* buffer address for Chroma in planar mode (unused in packing mode) */
- REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1]));
+ REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, (uint32_t)MCIF_ADDR(params->chroma_address[1]));
REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[1]));
/* buffer address for packing mode or Luma in planar mode */
- REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, MCIF_ADDR(params->luma_address[2]));
+ REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, (uint32_t)MCIF_ADDR(params->luma_address[2]));
REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[2]));
/* buffer address for Chroma in planar mode (unused in packing mode) */
- REG_UPDATE(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, MCIF_ADDR(params->chroma_address[2]));
+ REG_UPDATE(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, (uint32_t)MCIF_ADDR(params->chroma_address[2]));
REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[2]));
/* buffer address for packing mode or Luma in planar mode */
- REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, MCIF_ADDR(params->luma_address[3]));
+ REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, (uint32_t)MCIF_ADDR(params->luma_address[3]));
REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[3]));
/* buffer address for Chroma in planar mode (unused in packing mode) */
- REG_UPDATE(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, MCIF_ADDR(params->chroma_address[3]));
+ REG_UPDATE(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, (uint32_t)MCIF_ADDR(params->chroma_address[3]));
REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[3]));
/* setup luma & chroma size
#undef FN
#define FN(reg_name, field_name) \
- enc1->se_shift->field_name, enc1->se_mask->field_name
+ (uint8_t)enc1->se_shift->field_name, enc1->se_mask->field_name
#define VBI_LINE_0 0
#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
#undef FN
#define FN(reg_name, field_name) \
- enc1->se_shift->field_name, enc1->se_mask->field_name
+ (uint8_t)enc1->se_shift->field_name, enc1->se_mask->field_name
#define VBI_LINE_0 0
#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
{
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
- REG_UPDATE(DIG_FE_AUDIO_CNTL, APG_CLOCK_ENABLE, !!enable);
+ REG_UPDATE(DIG_FE_AUDIO_CNTL, APG_CLOCK_ENABLE, enable);
}
*secondary_pipe = *primary_pipe;
- secondary_pipe->pipe_idx = pipe_idx;
+ secondary_pipe->pipe_idx = (uint8_t)pipe_idx;
secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
- secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
+ secondary_pipe->plane_res.mpcc_inst =
+ (uint8_t)pool->dpps[secondary_pipe->pipe_idx]->inst;
if (primary_pipe->bottom_pipe) {
ASSERT(primary_pipe->bottom_pipe != secondary_pipe);
secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
timing->h_addressable + timing->h_border_left + timing->h_border_right;
pipes[pipe_cnt].pipe.dest.vactive =
timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
- pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
+ pipes[pipe_cnt].pipe.dest.interlaced = (unsigned char)timing->flags.INTERLACE;
pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
- pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
+ pipes[pipe_cnt].pipe.dest.otg_inst =
+ (unsigned char)res_ctx->pipe_ctx[i].stream_res.tg->inst;
pipes[pipe_cnt].dout.dp_lanes = 4;
pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na;
pipes[pipe_cnt].dout.is_virtual = 0;
bb->clock_limits[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
// FCLK:UCLK ratio is 1.08
- min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
+ min_fclk_required_by_uclk = (int)div_u64(((unsigned long long)uclk_states[i]) * 1080,
1000000);
bb->clock_limits[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
double pstate_latency_us = base->ctx->dc->dml.soc.dram_clock_change_latency_us;
double sr_exit_time_us = base->ctx->dc->dml.soc.sr_exit_time_us;
double sr_enter_plus_exit_time_us = base->ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
- uint16_t min_uclk_mhz = base->bw_params->clk_table.entries[0].memclk_mhz;
+ uint16_t min_uclk_mhz = (uint16_t)base->bw_params->clk_table.entries[0].memclk_mhz;
dc_assert_fp_enabled();
double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
/* For min clocks use as reported by PM FW and report those as min */
- uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
- uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
+ uint16_t min_uclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
+ uint16_t min_dcfclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
uint16_t setb_min_uclk_mhz = min_uclk_mhz;
- uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
+ uint16_t dcfclk_mhz_for_the_second_state =
+ (uint16_t)clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
dc_assert_fp_enabled();
/* For Set B ranges use min clocks state 2 when available, and report those to PM FW */
- if (dcfclk_mhz_for_the_second_state)
- clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state;
- else
- clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
+ if (dcfclk_mhz_for_the_second_state) {
+ clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk =
+ (uint16_t)dcfclk_mhz_for_the_second_state;
+ } else
+ clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk =
+ (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz)
- setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;
+ setb_min_uclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;
/* Set A - Normal - default values */
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
struct pipe_ctx *subvp_pipe = NULL;
bool found = false;
bool schedulable = false;
- uint32_t i = 0;
+ uint8_t i = 0;
uint8_t vblank_index = 0;
uint16_t prefetch_us = 0;
uint16_t mall_region_us = 0;
struct dc_state *context)
{
bool result = false;
- uint32_t i;
+ uint8_t i;
uint8_t subvp_count = 0;
uint32_t min_refresh = subvp_high_refresh_list.min_refresh, max_refresh = 0;
uint64_t refresh_rate = 0;
if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
pipe = &context->res_ctx.pipe_ctx[old_index];
- pipe->pipe_idx = old_index;
+ pipe->pipe_idx = (uint8_t)old_index;
}
if (!pipe)
&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
if (context->res_ctx.pipe_ctx[i].stream == NULL) {
pipe = &context->res_ctx.pipe_ctx[i];
- pipe->pipe_idx = i;
+ pipe->pipe_idx = (uint8_t)i;
break;
}
}
for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
if (context->res_ctx.pipe_ctx[i].stream == NULL) {
pipe = &context->res_ctx.pipe_ctx[i];
- pipe->pipe_idx = i;
+ pipe->pipe_idx = (uint8_t)i;
break;
}
}
*sec_pipe = *pri_pipe;
- sec_pipe->pipe_idx = pipe_idx;
+ sec_pipe->pipe_idx = (uint8_t)pipe_idx;
sec_pipe->plane_res.mi = pool->mis[pipe_idx];
sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
- sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
+ sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst;
sec_pipe->stream_res.dsc = NULL;
if (odm) {
if (pri_pipe->next_odm_pipe) {
refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
(uint64_t)pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);
- refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
- refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
+ refresh_rate = (uint32_t)div_u64(refresh_rate, pipe->stream->timing.v_total);
+ refresh_rate = (uint32_t)div_u64(refresh_rate, pipe->stream->timing.h_total);
if (refresh_rate >= min_refresh && refresh_rate <= max_refresh &&
dcn32_check_native_scaling_for_res(pipe, width, height)) {
dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple);
dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h;
dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v;
- dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor;
- dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width;
- dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height;
+ dsc_reg_vals->pps.dsc_version_minor = (u8)dsc_cfg->dc_dsc_cfg.version_minor;
+ dsc_reg_vals->pps.pic_width = (u16)dsc_cfg->pic_width;
+ dsc_reg_vals->pps.pic_height = (u16)dsc_cfg->pic_height;
dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth);
dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable;
- dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth;
+ dsc_reg_vals->pps.line_buf_depth = (u8)dsc_cfg->dc_dsc_cfg.linebuf_depth;
dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1;
dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0;
dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1;
if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
- dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32;
+ dsc_reg_vals->pps.bits_per_pixel = (u16)dsc_reg_vals->bpp_x32;
else
- dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1;
+ dsc_reg_vals->pps.bits_per_pixel = (u16)(dsc_reg_vals->bpp_x32 >> 1);
dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0;
dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422);
{
int i;
- dsc_cfg->rc_quant_incr_limit0 = rc->rc_quant_incr_limit0;
- dsc_cfg->rc_quant_incr_limit1 = rc->rc_quant_incr_limit1;
- dsc_cfg->initial_offset = rc->initial_fullness_offset;
- dsc_cfg->initial_xmit_delay = rc->initial_xmit_delay;
- dsc_cfg->first_line_bpg_offset = rc->first_line_bpg_offset;
- dsc_cfg->second_line_bpg_offset = rc->second_line_bpg_offset;
- dsc_cfg->flatness_min_qp = rc->flatness_min_qp;
- dsc_cfg->flatness_max_qp = rc->flatness_max_qp;
+ dsc_cfg->rc_quant_incr_limit0 = (u8)rc->rc_quant_incr_limit0;
+ dsc_cfg->rc_quant_incr_limit1 = (u8)rc->rc_quant_incr_limit1;
+ dsc_cfg->initial_offset = (u16)rc->initial_fullness_offset;
+ dsc_cfg->initial_xmit_delay = (u16)rc->initial_xmit_delay;
+ dsc_cfg->first_line_bpg_offset = (u8)rc->first_line_bpg_offset;
+ dsc_cfg->second_line_bpg_offset = (u8)rc->second_line_bpg_offset;
+ dsc_cfg->flatness_min_qp = (u8)rc->flatness_min_qp;
+ dsc_cfg->flatness_max_qp = (u8)rc->flatness_max_qp;
for (i = 0; i < QP_SET_SIZE; ++i) {
- dsc_cfg->rc_range_params[i].range_min_qp = rc->qp_min[i];
- dsc_cfg->rc_range_params[i].range_max_qp = rc->qp_max[i];
+ dsc_cfg->rc_range_params[i].range_min_qp = (u8)rc->qp_min[i];
+ dsc_cfg->rc_range_params[i].range_max_qp = (u8)rc->qp_max[i];
/* Truncate 8-bit signed value to 6-bit signed value */
dsc_cfg->rc_range_params[i].range_bpg_offset = 0x3f & rc->ofs[i];
}
- dsc_cfg->rc_model_size = rc->rc_model_size;
- dsc_cfg->rc_edge_factor = rc->rc_edge_factor;
- dsc_cfg->rc_tgt_offset_high = rc->rc_tgt_offset_hi;
- dsc_cfg->rc_tgt_offset_low = rc->rc_tgt_offset_lo;
+ dsc_cfg->rc_model_size = (u16)rc->rc_model_size;
+ dsc_cfg->rc_edge_factor = (u8)rc->rc_edge_factor;
+ dsc_cfg->rc_tgt_offset_high = (u8)rc->rc_tgt_offset_hi;
+ dsc_cfg->rc_tgt_offset_low = (u8)rc->rc_tgt_offset_lo;
for (i = 0; i < QP_SET_SIZE - 1; ++i)
- dsc_cfg->rc_buf_thresh[i] = rc->rc_buf_thresh[i];
+ dsc_cfg->rc_buf_thresh[i] = (u16)rc->rc_buf_thresh[i];
}
int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps,
#undef FN
#define FN(reg_name, field_name) \
- ddc->shifts->field_name, ddc->masks->field_name
+ gpio_reg_shift(ddc->shifts->field_name), ddc->masks->field_name
#define CTX \
ddc->base.base.ctx
#undef FN
#define FN(reg_name, field_name) \
- generic->shifts->field_name, generic->masks->field_name
+ gpio_reg_shift(generic->shifts->field_name), generic->masks->field_name
#define CTX \
generic->base.base.ctx
#undef FN
#define FN(reg_name, field_name) \
- gpio->regs->field_name ## _shift, gpio->regs->field_name ## _mask
+ gpio_reg_shift(gpio->regs->field_name ## _shift), gpio->regs->field_name ## _mask
#define CTX \
gpio->base.ctx
void dal_hw_gpio_close(
struct hw_gpio_pin *ptr);
+/*
+ * Shared helper used by all GPIO register helpers that pass a field shift
+ * (stored as uint32_t) into register functions that expect uint8_t.
+ */
+static inline uint8_t gpio_reg_shift(uint32_t shift)
+{
+ return (uint8_t)shift;
+}
+
#endif
#undef FN
#define FN(reg_name, field_name) \
- hpd->shifts->field_name, hpd->masks->field_name
+ gpio_reg_shift(hpd->shifts->field_name), hpd->masks->field_name
#define CTX \
hpd->base.base.ctx
SDPIF_FB_BASE, 0x0FFFF);
REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
- SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+ SDPIF_AGP_BASE, (uint32_t)(dh_data->zfb_phys_addr_base >> 22));
REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
- SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+ SDPIF_AGP_BOT, (uint32_t)(dh_data->zfb_mc_base_addr >> 22));
REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
- SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
- dh_data->zfb_size_in_byte - 1) >> 22);
+ SDPIF_AGP_TOP, (uint32_t)((dh_data->zfb_mc_base_addr +
+ dh_data->zfb_size_in_byte - 1) >> 22));
break;
case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
- SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+ SDPIF_AGP_BASE, (uint32_t)(dh_data->zfb_phys_addr_base >> 22));
REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
- SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+ SDPIF_AGP_BOT, (uint32_t)(dh_data->zfb_mc_base_addr >> 22));
REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
- SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
- dh_data->zfb_size_in_byte - 1) >> 22);
+ SDPIF_AGP_TOP, (uint32_t)((dh_data->zfb_mc_base_addr +
+ dh_data->zfb_size_in_byte - 1) >> 22));
break;
case FRAME_BUFFER_MODE_LOCAL_ONLY:
/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
struct dcn_vmid_page_table_config phys_config;
REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
- FB_BASE, pa_config->system_aperture.fb_base >> 24);
+ FB_BASE, ADDR_HI24(pa_config->system_aperture.fb_base));
REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
- FB_TOP, pa_config->system_aperture.fb_top >> 24);
+ FB_TOP, ADDR_HI24(pa_config->system_aperture.fb_top));
REG_SET(DCN_VM_FB_OFFSET, 0,
- FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
+ FB_OFFSET, ADDR_HI24(pa_config->system_aperture.fb_offset));
REG_SET(DCN_VM_AGP_BOT, 0,
- AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
+ AGP_BOT, ADDR_HI24(pa_config->system_aperture.agp_bot));
REG_SET(DCN_VM_AGP_TOP, 0,
- AGP_TOP, pa_config->system_aperture.agp_top >> 24);
+ AGP_TOP, ADDR_HI24(pa_config->system_aperture.agp_top));
REG_SET(DCN_VM_AGP_BASE, 0,
- AGP_BASE, pa_config->system_aperture.agp_base >> 24);
+ AGP_BASE, ADDR_HI24(pa_config->system_aperture.agp_base));
REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, (pa_config->page_table_default_page_addr >> 44) & 0xF);
/*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
REG_UPDATE(DCN_VM_AGP_BASE,
- AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
+ AGP_BASE, ADDR_HI24(dh_data->zfb_phys_addr_base));
/*This field defines the bottom range of the AGP aperture and represents the 24*/
/*MSBs, bits [47:24] of the 48 address bits*/
REG_UPDATE(DCN_VM_AGP_BOT,
- AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
+ AGP_BOT, ADDR_HI24(dh_data->zfb_mc_base_addr));
/*This field defines the top range of the AGP aperture and represents the 24*/
/*MSBs, bits [47:24] of the 48 address bits*/
REG_UPDATE(DCN_VM_AGP_TOP,
- AGP_TOP, (dh_data->zfb_mc_base_addr +
- dh_data->zfb_size_in_byte - 1) >> 24);
+ AGP_TOP, ADDR_HI24(dh_data->zfb_mc_base_addr +
+ dh_data->zfb_size_in_byte - 1));
break;
case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
/*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
REG_UPDATE(DCN_VM_AGP_BASE,
- AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
+ AGP_BASE, ADDR_HI24(dh_data->zfb_phys_addr_base));
/*This field defines the bottom range of the AGP aperture and represents the 24*/
/*MSBs, bits [47:24] of the 48 address bits*/
REG_UPDATE(DCN_VM_AGP_BOT,
- AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
+ AGP_BOT, ADDR_HI24(dh_data->zfb_mc_base_addr));
/*This field defines the top range of the AGP aperture and represents the 24*/
/*MSBs, bits [47:24] of the 48 address bits*/
REG_UPDATE(DCN_VM_AGP_TOP,
- AGP_TOP, (dh_data->zfb_mc_base_addr +
- dh_data->zfb_size_in_byte - 1) >> 24);
+ AGP_TOP, ADDR_HI24(dh_data->zfb_mc_base_addr +
+ dh_data->zfb_size_in_byte - 1));
break;
case FRAME_BUFFER_MODE_LOCAL_ONLY:
/*Should not touch FB LOCATION (should be done by VBIOS)*/
void hubbub2_read_state(struct hubbub *hubbub,
struct dcn_hubbub_state *hubbub_state);
+/* Extract bits [47:24] of a physical address for hardware register fields */
+#define ADDR_HI24(a) ((uint32_t)((uint64_t)(a) >> 24))
+
#endif
struct dcn_vmid_page_table_config phys_config;
REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
- FB_BASE, pa_config->system_aperture.fb_base >> 24);
+ FB_BASE, ADDR_HI24(pa_config->system_aperture.fb_base));
REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
- FB_TOP, pa_config->system_aperture.fb_top >> 24);
+ FB_TOP, ADDR_HI24(pa_config->system_aperture.fb_top));
REG_SET(DCN_VM_FB_OFFSET, 0,
- FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
+ FB_OFFSET, ADDR_HI24(pa_config->system_aperture.fb_offset));
REG_SET(DCN_VM_AGP_BOT, 0,
- AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
+ AGP_BOT, ADDR_HI24(pa_config->system_aperture.agp_bot));
REG_SET(DCN_VM_AGP_TOP, 0,
- AGP_TOP, pa_config->system_aperture.agp_top >> 24);
+ AGP_TOP, ADDR_HI24(pa_config->system_aperture.agp_top));
REG_SET(DCN_VM_AGP_BASE, 0,
- AGP_BASE, pa_config->system_aperture.agp_base >> 24);
+ AGP_BASE, ADDR_HI24(pa_config->system_aperture.agp_base));
if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
struct dcn_vmid_page_table_config phys_config;
REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
- FB_BASE, pa_config->system_aperture.fb_base >> 24);
+ FB_BASE, ADDR_HI24(pa_config->system_aperture.fb_base));
REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
- FB_TOP, pa_config->system_aperture.fb_top >> 24);
+ FB_TOP, ADDR_HI24(pa_config->system_aperture.fb_top));
REG_SET(DCN_VM_FB_OFFSET, 0,
- FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
+ FB_OFFSET, ADDR_HI24(pa_config->system_aperture.fb_offset));
REG_SET(DCN_VM_AGP_BOT, 0,
- AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
+ AGP_BOT, ADDR_HI24(pa_config->system_aperture.agp_bot));
REG_SET(DCN_VM_AGP_TOP, 0,
- AGP_TOP, pa_config->system_aperture.agp_top >> 24);
+ AGP_TOP, ADDR_HI24(pa_config->system_aperture.agp_top));
REG_SET(DCN_VM_AGP_BASE, 0,
- AGP_BASE, pa_config->system_aperture.agp_base >> 24);
+ AGP_BASE, ADDR_HI24(pa_config->system_aperture.agp_base));
if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
struct dcn_vmid_page_table_config phys_config;
REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
- FB_BASE, pa_config->system_aperture.fb_base >> 24);
+ FB_BASE, ADDR_HI24(pa_config->system_aperture.fb_base));
REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
- FB_TOP, pa_config->system_aperture.fb_top >> 24);
+ FB_TOP, ADDR_HI24(pa_config->system_aperture.fb_top));
REG_SET(DCN_VM_FB_OFFSET, 0,
- FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
+ FB_OFFSET, ADDR_HI24(pa_config->system_aperture.fb_offset));
REG_SET(DCN_VM_AGP_BOT, 0,
- AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
+ AGP_BOT, ADDR_HI24(pa_config->system_aperture.agp_bot));
REG_SET(DCN_VM_AGP_TOP, 0,
- AGP_TOP, pa_config->system_aperture.agp_top >> 24);
+ AGP_TOP, ADDR_HI24(pa_config->system_aperture.agp_top));
REG_SET(DCN_VM_AGP_BASE, 0,
- AGP_BASE, pa_config->system_aperture.agp_base >> 24);
+ AGP_BASE, ADDR_HI24(pa_config->system_aperture.agp_base));
if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
- MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
+ MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.low_part);
REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
- MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
+ MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.low_part);
REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
ENABLE_L1_TLB, 1,
mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
- MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
+ MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.low_part);
REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
- MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
+ MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.low_part);
REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
ENABLE_L1_TLB, 1,
mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
- MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
+ MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.low_part);
REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
- MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
+ MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.low_part);
REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
ENABLE_L1_TLB, 1,
DC_LOG_HW_RESUME_S3(
"%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n",
__func__, remaining_min_edp_poweroff_time_ms);
- msleep(remaining_min_edp_poweroff_time_ms);
+ msleep((unsigned int)remaining_min_edp_poweroff_time_ms);
DC_LOG_HW_RESUME_S3(
"%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n",
__func__, remaining_min_edp_poweroff_time_ms);
cntl.coherent = false;
cntl.lanes_number = LANE_COUNT_FOUR;
cntl.hpd_sel = link->link_enc->hpd_source;
- pwrseq_instance = link->panel_cntl->pwrseq_inst;
+ pwrseq_instance = (uint8_t)link->panel_cntl->pwrseq_inst;
if (ctx->dc->ctx->dmub_srv &&
ctx->dc->debug.dmub_command_table) {
t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12
if (time_since_edp_poweroff_ms < t12_duration)
- msleep(t12_duration - time_since_edp_poweroff_ms);
+ msleep((unsigned int)(t12_duration - time_since_edp_poweroff_ms));
}
}
/*todo: cloned in stream enc, fix*/
*/
/* dc_service_sleep_in_milliseconds(50); */
/*edp 1.2*/
- if (link->panel_cntl)
- pwrseq_instance = link->panel_cntl->pwrseq_inst;
+ if (link->panel_cntl) {
+ pwrseq_instance = (uint8_t)link->panel_cntl->pwrseq_inst;
+ }
if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {
if (!link->dc->config.edp_no_power_sequencing)
audio_output->crtc_info.pixel_repetition = 1;
audio_output->crtc_info.interlaced =
- stream->timing.flags.INTERLACE;
+ (stream->timing.flags.INTERLACE != 0);
audio_output->crtc_info.refresh_rate =
(stream->timing.pix_clk_100hz*100)/
static void disable_vga_and_power_gate_all_controllers(
struct dc *dc)
{
- int i;
+ uint8_t i;
struct timing_generator *tg;
struct dc_context *ctx = dc->ctx;
struct dc_stream_state **edp_streams,
int *edp_stream_num)
{
- int i;
+ uint8_t i;
*edp_stream_num = 0;
for (i = 0; i < context->stream_count; i++) {
const struct dc_stream_state *stream)
{
uint32_t total_dest_line_time_ns;
+ int64_t pstate_blackout_duration_ns64;
uint32_t pstate_blackout_duration_ns;
- pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
+ pstate_blackout_duration_ns64 = (1000 * blackout_duration.value) >> 24;
+ pstate_blackout_duration_ns = (uint32_t)pstate_blackout_duration_ns64;
total_dest_line_time_ns = 1000000UL *
(stream->timing.h_total * 10) /
}
hws->funcs.enable_display_power_gating(
- dc, i, dc->ctx->dc_bios,
+ dc, (uint8_t)i, dc->ctx->dc_bios,
PIPE_GATING_CONTROL_DISABLE);
}
xfm->funcs->transform_reset(xfm);
hws->funcs.enable_display_power_gating(
- dc, i, bp,
+ dc, (uint8_t)i, bp,
PIPE_GATING_CONTROL_INIT);
hws->funcs.enable_display_power_gating(
- dc, i, bp,
+ dc, (uint8_t)i, bp,
PIPE_GATING_CONTROL_DISABLE);
hws->funcs.enable_display_pipe_clock_gating(
dc->ctx,
return;
hws->funcs.enable_display_power_gating(
- dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
+ dc, (uint8_t)fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
dc->res_pool->transforms[fe_idx]);
FB_BASE, 0x0FFFF);
REG_UPDATE(DCHUB_AGP_BASE,
- AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+ AGP_BASE, (uint32_t)(dh_data->zfb_phys_addr_base >> 22));
REG_UPDATE(DCHUB_AGP_BOT,
- AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+ AGP_BOT, (uint32_t)(dh_data->zfb_mc_base_addr >> 22));
REG_UPDATE(DCHUB_AGP_TOP,
- AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
+ AGP_TOP, (uint32_t)((dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22));
break;
case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
REG_UPDATE(DCHUB_AGP_BASE,
- AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+ AGP_BASE, (uint32_t)(dh_data->zfb_phys_addr_base >> 22));
REG_UPDATE(DCHUB_AGP_BOT,
- AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+ AGP_BOT, (uint32_t)(dh_data->zfb_mc_base_addr >> 22));
REG_UPDATE(DCHUB_AGP_TOP,
- AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
+ AGP_TOP, (uint32_t)((dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22));
break;
case FRAME_BUFFER_MODE_LOCAL_ONLY:
/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
{
- int i;
+ uint8_t i;
struct dce_hwseq *hws = dc->hwseq;
struct hubbub *hubbub = dc->res_pool->hubbub;
bool can_apply_seamless_boot = false;
pipe_ctx->plane_res.hubp = hubp;
pipe_ctx->plane_res.dpp = dpp;
- pipe_ctx->plane_res.mpcc_inst = dpp->inst;
+ pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;
hubp->mpcc_id = dpp->inst;
hubp->opp_id = OPP_ID_INVALID;
hubp->power_gated = false;
struct dmub_hw_lock_inst_flags inst_flags = { 0 };
hw_locks.bits.lock_cursor = 1;
- inst_flags.opp_inst = pipe->stream_res.opp->inst;
+ inst_flags.opp_inst = (uint8_t)pipe->stream_res.opp->inst;
dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
lock,
}
clock_divider *= numpipes;
- return clock_divider;
+ return (uint8_t)clock_divider;
}
static int dcn10_align_pixel_clocks(struct dc *dc, int group_size,
dc->res_pool->dp_clock_source->funcs->override_dp_pix_clk(
dc->res_pool->dp_clock_source,
grouped_pipes[i]->stream_res.tg->inst,
- phase[i], modulo[i]);
+ (unsigned int)phase[i], (unsigned int)modulo[i]);
dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
dc->res_pool->dp_clock_source,
grouped_pipes[i]->stream_res.tg->inst, &pclk);
}
}
flags->RIGHT_EYE_POLARITY =\
- stream->timing.flags.RIGHT_EYE_3D_POLARITY;
+ (stream->timing.flags.RIGHT_EYE_3D_POLARITY != 0);
if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
flags->FRAME_PACKED = 1;
}
group_idx = find_free_gsl_group(dc);
ASSERT(group_idx != 0);
- pipe_ctx->stream_res.gsl_group = group_idx;
+ pipe_ctx->stream_res.gsl_group = (uint8_t)group_idx;
/* set gsl group reg field and mark resource used */
switch (group_idx) {
unsigned int event_triggers = 0;
int opp_cnt = 1;
int opp_inst[MAX_PIPES] = {0};
- bool interlace = stream->timing.flags.INTERLACE;
+ bool interlace = (stream->timing.flags.INTERLACE != 0);
int i;
struct mpc_dwb_flow_control flow_control;
struct mpc *mpc = dc->res_pool->mpc;
struct dmub_hw_lock_inst_flags inst_flags = { 0 };
hw_locks.bits.lock_pipe = 1;
- inst_flags.otg_inst = pipe->stream_res.tg->inst;
+ inst_flags.otg_inst = (uint8_t)pipe->stream_res.tg->inst;
if (pipe->plane_state != NULL)
hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips;
addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
// Call Helper to track VMID use
- vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
+ vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid,
+ (uint8_t)pipe_ctx->plane_res.hubp->inst);
pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
pipe_ctx->plane_res.hubp,
void dcn20_fpga_init_hw(struct dc *dc)
{
- int i, j;
+ uint8_t i, j;
struct dce_hwseq *hws = dc->hwseq;
struct resource_pool *res_pool = dc->res_pool;
struct dc_state *context = dc->current_state;
pipe_ctx->plane_res.hubp = hubp;
pipe_ctx->plane_res.dpp = dpp;
- pipe_ctx->plane_res.mpcc_inst = dpp->inst;
+ pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;
hubp->mpcc_id = dpp->inst;
hubp->opp_id = OPP_ID_INVALID;
hubp->power_gated = false;
memset(&cmd, 0, sizeof(cmd));
cmd.abm_set_pipe.header.type = DMUB_CMD__ABM;
cmd.abm_set_pipe.header.sub_type = DMUB_CMD__ABM_SET_PIPE;
- cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst;
- cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = pwrseq_inst;
- cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = option;
- cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = panel_inst;
+ cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = (uint8_t)otg_inst;
+ cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = (uint8_t)pwrseq_inst;
+ cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = (uint8_t)option;
+ cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = (uint8_t)panel_inst;
cmd.abm_set_pipe.abm_set_pipe_data.ramping_boundary = ramping_boundary;
cmd.abm_set_pipe.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pipe_data);
cursor_cache_enable ? &cursor_attr : NULL)) {
unsigned int v_total = stream->adjust.v_total_max ?
stream->adjust.v_total_max : stream->timing.v_total;
- unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz *
+ unsigned int refresh_hz = (unsigned int)div_u64((unsigned long long)stream->timing.pix_clk_100hz *
100LL, (v_total * stream->timing.h_total));
/*
unsigned int denom = refresh_hz * 6528;
unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
- tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
+ tmr_delay = (uint32_t)(div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
(100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
- denom) - 64LL;
+ denom) - 64LL);
/* In some cases the stutter period is really big (tiny modes) in these
* cases MALL cant be enabled, So skip these cases to avoid a ASSERT()
}
denom *= 2;
- tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
+ tmr_delay = (uint32_t)(div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
(100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
- denom) - 64LL;
+ denom) - 64LL);
}
/* Copy HW cursor */
cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
cmd.mall.cursor_copy_dst.quad_part =
(plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047;
- cmd.mall.cursor_width = cursor_attr.width;
- cmd.mall.cursor_height = cursor_attr.height;
- cmd.mall.cursor_pitch = cursor_attr.pitch;
+ cmd.mall.cursor_width = (uint16_t)cursor_attr.width;
+ cmd.mall.cursor_height = (uint16_t)cursor_attr.height;
+ cmd.mall.cursor_pitch = (uint16_t)cursor_attr.pitch;
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
if (pipe_ctx->stream_res.dsc) {
struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
- update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
+ update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0);
/* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&
if (dcn314_is_pipe_dig_fifo_on(pipe))
continue;
pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
- reset_sync_context_for_pipe(dc, context, i);
+ reset_sync_context_for_pipe(dc, context, (uint8_t)i);
otg_disabled[i] = true;
}
}
if (pipe_ctx->stream_res.dsc) {
struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
- dcn32_update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
+ dcn32_update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0);
/* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&
if ((pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))
&& dc_state_get_pipe_subvp_type(dc_state, pipe) != SUBVP_PHANTOM) {
pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
- reset_sync_context_for_pipe(dc, context, i);
+ reset_sync_context_for_pipe(dc, context, (uint8_t)i);
otg_disabled[i] = true;
}
}
if (pipe_ctx->stream_res.dsc) {
struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
- update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
+ update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0);
/* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&
void dcn35_init_pipes(struct dc *dc, struct dc_state *context)
{
- int i;
+ uint8_t i;
struct dce_hwseq *hws = dc->hwseq;
struct hubbub *hubbub = dc->res_pool->hubbub;
struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
pipe_ctx->plane_res.hubp = hubp;
pipe_ctx->plane_res.dpp = dpp;
- pipe_ctx->plane_res.mpcc_inst = dpp->inst;
+ pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;
hubp->mpcc_id = dpp->inst;
hubp->opp_id = OPP_ID_INVALID;
hubp->power_gated = false;
static uint32_t dcn401_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
{
int i;
- uint8_t num_ways = 0;
+ uint32_t num_ways = 0;
uint32_t mall_ss_size_bytes = 0;
mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes;
bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable)
{
union dmub_rb_cmd cmd;
- uint8_t ways, i;
+ uint32_t ways;
+ uint8_t i;
int j;
bool mall_ss_unsupported = false;
struct dc_plane_state *plane = NULL;
}
if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {
cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
- cmd.cab.cab_alloc_ways = ways;
+ cmd.cab.cab_alloc_ways = (uint8_t)ways;
DC_LOG_MALL("cab allocation: %d ways. CAB action: DCN_SS_FIT_IN_CAB\n", ways);
} else {
cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB;
void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable)
{
bool fams2_info_required;
+ bool fams2_enabled;
+ bool fams2_legacy_no_fams2;
if (!dc->ctx || !dc->ctx->dmub_srv || !dc->debug.fams2_config.bits.enable)
return;
- fams2_info_required = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;
- fams2_info_required |= context->bw_ctx.bw.dcn.fams2_global_config.features.bits.legacy_method_no_fams2;
+ fams2_enabled = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable != 0u;
+ fams2_legacy_no_fams2 = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.legacy_method_no_fams2 != 0u;
+ fams2_info_required = fams2_enabled || fams2_legacy_no_fams2;
dc_dmub_srv_fams2_update_config(dc, context, enable && fams2_info_required);
}
if (otg_master->stream_res.dsc)
dcn32_update_dsc_on_stream(otg_master,
- otg_master->stream->timing.flags.DSC);
+ otg_master->stream->timing.flags.DSC != 0u);
if (old_otg_master && old_otg_master->stream_res.dsc) {
for (i = 0; i < old_opp_head_count; i++) {
old_pipe = old_opp_heads[i];
group_idx = find_free_gsl_group(dc);
ASSERT(group_idx != 0);
- pipe_ctx->stream_res.gsl_group = group_idx;
+ pipe_ctx->stream_res.gsl_group = (uint8_t)group_idx;
/* set gsl group reg field and mark resource used */
switch (group_idx) {
static inline int32_t bw_fixed_to_int(struct bw_fixed value)
{
- return BW_FIXED_GET_INTEGER_PART(value.value);
+ return (int32_t)BW_FIXED_GET_INTEGER_PART(value.value);
}
struct bw_fixed bw_frc_to_fixed(int64_t num, int64_t denum);
unsigned int channel_count;
unsigned int channel = 0;
unsigned int modes = 0;
- unsigned int sampling_rate_in_hz = 0;
// get audio test mode and test pattern parameters
core_link_read_dpcd(
}
}
- // translate sampling rate
- switch (dpcd_test_mode.bits.sampling_rate) {
- case AUDIO_SAMPLING_RATE_32KHZ:
- sampling_rate_in_hz = 32000;
- break;
- case AUDIO_SAMPLING_RATE_44_1KHZ:
- sampling_rate_in_hz = 44100;
- break;
- case AUDIO_SAMPLING_RATE_48KHZ:
- sampling_rate_in_hz = 48000;
- break;
- case AUDIO_SAMPLING_RATE_88_2KHZ:
- sampling_rate_in_hz = 88200;
- break;
- case AUDIO_SAMPLING_RATE_96KHZ:
- sampling_rate_in_hz = 96000;
- break;
- case AUDIO_SAMPLING_RATE_176_4KHZ:
- sampling_rate_in_hz = 176400;
- break;
- case AUDIO_SAMPLING_RATE_192KHZ:
- sampling_rate_in_hz = 192000;
- break;
- default:
- sampling_rate_in_hz = 0;
- break;
- }
-
link->audio_test_data.flags.test_requested = 1;
link->audio_test_data.flags.disable_video = disable_video;
- link->audio_test_data.sampling_rate = sampling_rate_in_hz;
- link->audio_test_data.channel_count = channel_count;
+ link->audio_test_data.sampling_rate = (uint8_t)dpcd_test_mode.bits.sampling_rate;
+ link->audio_test_data.channel_count = (uint8_t)channel_count;
link->audio_test_data.pattern_type = test_pattern;
if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
struct dmub_hw_lock_inst_flags inst_flags = { 0 };
hw_locks.bits.lock_dig = 1;
- inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
+ inst_flags.dig_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
true,
struct dmub_hw_lock_inst_flags inst_flags = { 0 };
hw_locks.bits.lock_dig = 1;
- inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
+ inst_flags.dig_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
false,
time_slot_in_ms = dc_fixpt_from_fraction(32 * 4, link_bw_in_kbps);
mtp_cnt_per_h_blank = dc_fixpt_div(h_blank_in_ms,
dc_fixpt_mul_int(time_slot_in_ms, 64));
- hblank_min_symbol_width = dc_fixpt_floor(
+ hblank_min_symbol_width = (uint16_t)dc_fixpt_floor(
dc_fixpt_mul(mtp_cnt_per_h_blank, throttled_vcp_size));
}
&stream->timing,
stream->output_color_space,
stream->use_vsc_sdp_for_colorimetry,
- stream->timing.flags.DSC,
+ (stream->timing.flags.DSC != 0),
false);
link->dc->link_srv->dp_trace_source_sequence(link,
DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR);
struct i2c_payload payloads[2] = {
{
.write = true,
- .address = address,
+ .address = (uint8_t)address,
.length = 1,
.data = &offs_data },
{
.write = false,
- .address = address,
+ .address = (uint8_t)address,
.length = len,
.data = buffer } };
/* link encoder index */
config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
if (dp_is_128b_132b_signal(pipe_ctx))
- config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;
+ config.link_enc_idx = (uint8_t)pipe_ctx->link_res.hpo_dp_link_enc->inst;
/* dio output index is dpia index for DPIA endpoint & dcio index by default */
if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
if (allocate) {
avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link);
- req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
+ req_slot_count = (uint8_t)dc_fixpt_ceil(avg_time_slots_per_mtp);
/// Validation should filter out modes that exceed link BW
ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT);
if (req_slot_count > MAX_MTP_SLOT_COUNT)
write_scdc_data(
stream->link->ddc,
stream->phy_pix_clk,
- stream->timing.flags.LTE_340MCSC_SCRAMBLE);
+ (stream->timing.flags.LTE_340MCSC_SCRAMBLE != 0));
memset(&stream->link->cur_link_settings, 0,
sizeof(struct dc_link_settings));
sizeof(struct dc_link_settings));
link->link_id =
- bios->funcs->get_connector_id(bios, init_params->connector_index);
+ bios->funcs->get_connector_id(bios, (uint8_t)init_params->connector_index);
link->ep_type = DISPLAY_ENDPOINT_PHY;
if (bios->funcs->get_disp_connector_caps_info) {
bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
- link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
+ link->is_internal_display = (disp_connect_caps_info.INTERNAL_DISPLAY != 0);
DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
}
}
/* Set dpia port index : 0 to number of dpia ports */
- link->ddc_hw_inst = init_params->connector_index;
+ link->ddc_hw_inst = (uint8_t)init_params->connector_index;
// Assign Dpia preferred eng_id
if (link->dc->res_pool->funcs->get_preferred_eng_id_dpia)
for (pos = 0; pos < len; pos += payload_size) {
struct i2c_payload payload = {
.write = write,
- .address = address,
+ .address = (uint8_t)address,
.length = DDC_MIN(payload_size, len - pos),
.data = data + pos };
dal_vector_append(&payloads->payloads, &payload);
i2c_payloads_add(
&payloads, address, read_size, read_buf, false);
- command.number_of_payloads =
- i2c_payloads_get_count(&payloads);
+ command.number_of_payloads = (uint8_t)i2c_payloads_get_count(&payloads);
success = dm_helpers_submit_i2c(
ddc->ctx,
CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
// Identify closest LTTPR to determine if workarounds required for known embedded LTTPR
- closest_lttpr_offset = dp_get_closest_lttpr_offset(lttpr_count);
+ closest_lttpr_offset = dp_get_closest_lttpr_offset((uint8_t)lttpr_count);
core_link_read_dpcd(link, (DP_LTTPR_IEEE_OUI + closest_lttpr_offset),
link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui));
return bw_estimated_bw * (Kbps_TO_Gbps / link->dpia_bw_alloc_config.bw_granularity);
}
-static int get_non_reduced_max_link_rate(struct dc_link *link)
+static uint8_t get_non_reduced_max_link_rate(struct dc_link *link)
{
uint8_t nrd_max_link_rate = 0;
return nrd_max_link_rate;
}
-static int get_non_reduced_max_lane_count(struct dc_link *link)
+static uint8_t get_non_reduced_max_lane_count(struct dc_link *link)
{
uint8_t nrd_max_lane_count = 0;
if (dc->current_state->res_ctx.pipe_ctx[i].stream &&
dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;
- unsigned int vsync_rate_hz = div64_u64(div64_u64(
- (stream->timing.pix_clk_100hz * (u64)100),
- stream->timing.v_total),
- stream->timing.h_total);
-
+ unsigned int vsync_rate_hz = (unsigned int)div64_u64(div64_u64(
+ (stream->timing.pix_clk_100hz * (u64)100),
+ stream->timing.v_total),
+ stream->timing.h_total);
params.triggers.cursor_update = true;
params.triggers.overlay_update = true;
params.triggers.surface_update = true;
cmd.pr_enable.header.type = DMUB_CMD__PR;
cmd.pr_enable.header.sub_type = DMUB_CMD__PR_ENABLE;
cmd.pr_enable.header.payload_bytes = sizeof(struct dmub_cmd_pr_enable_data);
- cmd.pr_enable.data.panel_inst = panel_inst;
+ cmd.pr_enable.data.panel_inst = (uint8_t)panel_inst;
cmd.pr_enable.data.enable = enable ? 1 : 0;
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
cmd.pr_copy_settings.header.type = DMUB_CMD__PR;
cmd.pr_copy_settings.header.sub_type = DMUB_CMD__PR_COPY_SETTINGS;
cmd.pr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_pr_copy_settings_data);
- cmd.pr_copy_settings.data.panel_inst = panel_inst;
+ cmd.pr_copy_settings.data.panel_inst = (uint8_t)panel_inst;
// HW inst
cmd.pr_copy_settings.data.aux_inst = replay_context->aux_inst;
cmd.pr_copy_settings.data.digbe_inst = replay_context->digbe_inst;
cmd.pr_copy_settings.data.digfe_inst = replay_context->digfe_inst;
if (pipe_ctx->plane_res.dpp)
- cmd.pr_copy_settings.data.dpp_inst = pipe_ctx->plane_res.dpp->inst;
+ cmd.pr_copy_settings.data.dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst;
else
cmd.pr_copy_settings.data.dpp_inst = 0;
if (pipe_ctx->stream_res.tg)
- cmd.pr_copy_settings.data.otg_inst = pipe_ctx->stream_res.tg->inst;
+ cmd.pr_copy_settings.data.otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
else
cmd.pr_copy_settings.data.otg_inst = 0;
cmd.pr_update_state.header.type = DMUB_CMD__PR;
cmd.pr_update_state.header.sub_type = DMUB_CMD__PR_UPDATE_STATE;
cmd.pr_update_state.header.payload_bytes = sizeof(struct dmub_cmd_pr_update_state_data);
- cmd.pr_update_state.data.panel_inst = panel_inst;
+ cmd.pr_update_state.data.panel_inst = (uint8_t)panel_inst;
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
return true;
cmd.pr_general_cmd.header.type = DMUB_CMD__PR;
cmd.pr_general_cmd.header.sub_type = DMUB_CMD__PR_GENERAL_CMD;
cmd.pr_general_cmd.header.payload_bytes = sizeof(struct dmub_cmd_pr_general_cmd_data);
- cmd.pr_general_cmd.data.panel_inst = panel_inst;
+ cmd.pr_general_cmd.data.panel_inst = (uint8_t)panel_inst;
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
return true;
do {
// Send gpint command and wait for ack
- if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__GET_REPLAY_STATE, panel_inst,
+ if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__GET_REPLAY_STATE, (uint16_t)panel_inst,
&replay_state, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) {
// Return invalid state when GPINT times out
replay_state = PR_STATE_INVALID;
*/
lt_settings->link_settings.link_spread = link->dp_ss_off ?
LINK_SPREAD_DISABLED : LINK_SPREAD_05_DOWNSPREAD_30KHZ;
- lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
+ lt_settings->eq_pattern_time = (uint16_t)get_eq_training_aux_rd_interval(link, link_setting);
lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_res, link_setting);
lt_settings->enhanced_framing = 1;
lt_settings->disallow_per_lane_settings = true;
lt_settings->always_match_dpcd_with_hw_lane_settings = true;
lt_settings->lttpr_mode = dp_decide_8b_10b_lttpr_mode(link);
- lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting, lt_settings->lttpr_mode);
+ lt_settings->cr_pattern_time = (uint16_t)get_cr_training_aux_rd_interval(link, link_setting, lt_settings->lttpr_mode);
dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
/* Some embedded LTTPRs rely on receiving TPS2 before LT to interop reliably with sensitive VGA dongles
* 6. Begin link training as usual
* */
- uint32_t closest_lttpr_address_offset = dp_get_closest_lttpr_offset(lttpr_count);
+ uint32_t closest_lttpr_address_offset = dp_get_closest_lttpr_offset((uint8_t)lttpr_count);
union dpcd_training_pattern dpcd_pattern = {0};
dpcd_set_lane_settings(link, lt_settings, offset);
/* 3. wait for receiver to lock-on*/
- wait_time_microsec = dp_get_eq_aux_rd_interval(link, lt_settings, offset, retries_ch_eq);
+ wait_time_microsec = dp_get_eq_aux_rd_interval(link, lt_settings, offset, (uint8_t)retries_ch_eq);
dp_wait_for_training_aux_rd_interval(
link,
/* 6. check CHEQ done*/
if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
- dp_check_interlane_aligned(dpcd_lane_status_updated, link, retries_ch_eq))
+ dp_check_interlane_aligned(dpcd_lane_status_updated, link, (uint8_t)retries_ch_eq))
return LINK_TRAINING_SUCCESS;
/* 7. update VS/PE/PC2 in lt_settings*/
link->psr_settings.psr_power_opt = *power_opts;
if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
- psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
+ psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, (uint8_t)panel_inst);
}
if (psr != NULL && link->psr_settings.psr_feature_enabled &&
force_static && psr->funcs->psr_force_static)
- psr->funcs->psr_force_static(psr, panel_inst);
+ psr->funcs->psr_force_static(psr, (uint8_t)panel_inst);
/* Enable or Disable PSR */
if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
if (!link->psr_settings.psr_allow_active)
dc_z10_restore(dc);
- if (psr != NULL && link->psr_settings.psr_feature_enabled) {
- psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
- } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
+ if (psr != NULL && link->psr_settings.psr_feature_enabled)
+ psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, (uint8_t)panel_inst);
+ else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
link->psr_settings.psr_feature_enabled)
dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);
else
return false;
if (psr != NULL && link->psr_settings.psr_feature_enabled)
- psr->funcs->psr_get_state(psr, state, panel_inst);
+ psr->funcs->psr_get_state(psr, state, (uint8_t)panel_inst);
else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
dmcu->funcs->get_psr_state(dmcu, state);
psr_context->smuPhyId = transmitter_to_phy_id(link);
psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
- psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
+ psr_context->vsync_rate_hz = (unsigned int)div64_u64(div64_u64((stream->
timing.pix_clk_100hz * (u64)100),
stream->timing.v_total),
stream->timing.h_total);
if (psr) {
link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
- link, psr_context, panel_inst);
+ link, psr_context, (uint8_t)panel_inst);
link->psr_settings.psr_power_opt = 0;
link->psr_settings.psr_allow_active = 0;
} else {
// PSR residency measurements only supported on DMCUB
if (psr != NULL && link->psr_settings.psr_feature_enabled)
- psr->funcs->psr_get_residency(psr, residency, panel_inst, mode);
+ psr->funcs->psr_get_residency(psr, residency, (uint8_t)panel_inst, mode);
else
*residency = 0;
}
if (power_opts && link->replay_settings.replay_power_opt_active != *power_opts) {
if (replay != NULL && link->replay_settings.replay_feature_enabled &&
replay->funcs->replay_set_power_opt) {
- replay->funcs->replay_set_power_opt(replay, *power_opts, panel_inst);
+ replay->funcs->replay_set_power_opt(replay, *power_opts, (uint8_t)panel_inst);
link->replay_settings.replay_power_opt_active = *power_opts;
}
}
// TODO: Handle mux change case if force_static is set
// If force_static is set, just change the replay_allow_active state directly
if (replay != NULL && link->replay_settings.replay_feature_enabled)
- replay->funcs->replay_enable(replay, *allow_active, wait, panel_inst);
+ replay->funcs->replay_enable(replay, *allow_active, wait, (uint8_t)panel_inst);
link->replay_settings.replay_allow_active = *allow_active;
}
return false;
if (replay != NULL && link->replay_settings.replay_feature_enabled)
- replay->funcs->replay_get_state(replay, &pr_state, panel_inst);
+ replay->funcs->replay_get_state(replay, &pr_state, (uint8_t)panel_inst);
*state = pr_state;
return true;
replay_context.os_request_force_ffu = link->replay_settings.config.os_request_force_ffu;
link->replay_settings.replay_feature_enabled =
- replay->funcs->replay_copy_settings(replay, link, &replay_context, panel_inst);
+ replay->funcs->replay_copy_settings(replay, link, &replay_context, (uint8_t)panel_inst);
if (link->replay_settings.replay_feature_enabled) {
replay_config.bits.FREESYNC_PANEL_REPLAY_MODE = 1;
return false;
if (dp_pr_get_panel_inst(dc, link, &panel_inst))
- cmd_data->panel_inst = panel_inst;
+ cmd_data->panel_inst = (uint8_t)panel_inst;
else {
DC_LOG_DC("%s(): get edp panel inst fail ", __func__);
return false;
if (coasting_vtotal && (link->replay_settings.coasting_vtotal != coasting_vtotal ||
link->replay_settings.frame_skip_number != frame_skip_number)) {
- replay->funcs->replay_set_coasting_vtotal(replay, coasting_vtotal, panel_inst, frame_skip_number);
+ replay->funcs->replay_set_coasting_vtotal(replay, coasting_vtotal, (uint8_t)panel_inst, frame_skip_number);
link->replay_settings.coasting_vtotal = coasting_vtotal;
link->replay_settings.frame_skip_number = frame_skip_number;
}
return false;
if (replay != NULL && link->replay_settings.replay_feature_enabled)
- replay->funcs->replay_residency(replay, panel_inst, residency, is_start, mode);
+ replay->funcs->replay_residency(replay, (uint8_t)panel_inst, residency, is_start, mode);
else
*residency = 0;
if (link->replay_settings.replay_feature_enabled &&
replay->funcs->replay_set_power_opt_and_coasting_vtotal) {
replay->funcs->replay_set_power_opt_and_coasting_vtotal(replay,
- *power_opts, panel_inst, coasting_vtotal, frame_skip_number);
+ *power_opts, (uint8_t)panel_inst, coasting_vtotal, frame_skip_number);
link->replay_settings.replay_power_opt_active = *power_opts;
link->replay_settings.coasting_vtotal = coasting_vtotal;
link->replay_settings.frame_skip_number = frame_skip_number;
memset(&cmd, 0, sizeof(cmd));
- link_enc_index = link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;
+ link_enc_index = (uint8_t)(link->link_enc->transmitter - TRANSMITTER_UNIPHY_A);
if (link_res->hpo_dp_link_enc) {
- link_enc_index = link_res->hpo_dp_link_enc->inst;
+ link_enc_index = (uint8_t)link_res->hpo_dp_link_enc->inst;
use_hpo_dp_link_enc = true;
}
#define FN(reg_name, field_name) \
mcif_wb20->mcif_wb_shift->field_name, mcif_wb20->mcif_wb_mask->field_name
-#define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8
-#define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40
+#define MCIF_ADDR(addr) ((uint32_t)((((unsigned long long)(addr) & 0xffffffffffULL) + 0xFEULL) >> 8))
+#define MCIF_ADDR_HIGH(addr) ((uint32_t)(((unsigned long long)(addr)) >> 40))
/* wbif programming guide:
* 1. set up wbif parameter:
#define FN(reg_name, field_name) \
mcif_wb30->mcif_wb_shift->field_name, mcif_wb30->mcif_wb_mask->field_name
-#define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8
-#define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40
+#define MCIF_ADDR(addr) ((uint32_t)((((unsigned long long)(addr) & 0xffffffffffULL) + 0xFEULL) >> 8))
+#define MCIF_ADDR_HIGH(addr) ((uint32_t)(((unsigned long long)(addr)) >> 40))
/* wbif programming guide:
* 1. set up wbif parameter:
L = div_u64(L, master_h_total);
L = div_u64(L, slave_pixel_clock_100Hz);
XY = div_u64(L, p);
- Y = master_v_active - XY - 1;
- X = div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider);
+ Y = (uint32_t)(master_v_active - XY - 1);
+ X = (uint32_t)div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider);
/*
* set master OTG to unlock when V/H
/*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/
pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];
pipe_ctx->stream_res.opp = pool->opps[underlay_idx];
- pipe_ctx->pipe_idx = underlay_idx;
+ pipe_ctx->pipe_idx = (uint8_t)underlay_idx;
pipe_ctx->stream = stream;
hws->funcs.enable_display_power_gating(
dc,
- pipe_ctx->stream_res.tg->inst,
+ (uint8_t)pipe_ctx->stream_res.tg->inst,
dcb, PIPE_GATING_CONTROL_DISABLE);
/*
idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
- idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
+ idle_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[idle_pipe->pipe_idx]->inst;
return idle_pipe;
}
if (!pool)
return NULL;
- if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn10_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return &pool->base;
kfree(pool);
*next_odm_pipe = *prev_odm_pipe;
- next_odm_pipe->pipe_idx = pipe_idx;
+ next_odm_pipe->pipe_idx = (uint8_t)pipe_idx;
next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
- next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
+ next_odm_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[next_odm_pipe->pipe_idx]->inst;
next_odm_pipe->stream_res.dsc = NULL;
if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
*secondary_pipe = *primary_pipe;
secondary_pipe->bottom_pipe = sec_bot_pipe;
- secondary_pipe->pipe_idx = pipe_idx;
+ secondary_pipe->pipe_idx = (uint8_t)pipe_idx;
secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
- secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
+ secondary_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[secondary_pipe->pipe_idx]->inst;
secondary_pipe->stream_res.dsc = NULL;
if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
ASSERT(!secondary_pipe->bottom_pipe);
preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
- secondary_pipe->pipe_idx = preferred_pipe_idx;
+ secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx;
}
}
if (secondary_pipe == NULL &&
preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
- secondary_pipe->pipe_idx = preferred_pipe_idx;
+ secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx;
}
}
if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
- secondary_pipe->pipe_idx = preferred_pipe_idx;
+ secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx;
break;
}
}
if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
- secondary_pipe->pipe_idx = preferred_pipe_idx;
+ secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx;
break;
}
}
sec_dpp_pipe->plane_res.hubp = pool->hubps[sec_dpp_pipe->pipe_idx];
sec_dpp_pipe->plane_res.ipp = pool->ipps[sec_dpp_pipe->pipe_idx];
sec_dpp_pipe->plane_res.dpp = pool->dpps[sec_dpp_pipe->pipe_idx];
- sec_dpp_pipe->plane_res.mpcc_inst = pool->dpps[sec_dpp_pipe->pipe_idx]->inst;
+ sec_dpp_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[sec_dpp_pipe->pipe_idx]->inst;
return sec_dpp_pipe;
}
ranges.num_reader_wm_sets = 0;
if (loaded_bb->num_states == 1) {
- ranges.reader_wm_sets[0].wm_inst = i;
+ ranges.reader_wm_sets[0].wm_inst = (uint8_t)i;
ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
ranges.num_reader_wm_sets = 1;
} else if (loaded_bb->num_states > 1) {
for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
- ranges.reader_wm_sets[i].wm_inst = i;
+ ranges.reader_wm_sets[i].wm_inst = (uint8_t)i;
ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
DC_FP_START();
if (!pool)
return NULL;
- if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn20_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
if (!pool)
return NULL;
- if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn21_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
*sec_pipe = *pri_pipe;
- sec_pipe->pipe_idx = pipe_idx;
+ sec_pipe->pipe_idx = (uint8_t)pipe_idx;
sec_pipe->plane_res.mi = pool->mis[pipe_idx];
sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
- sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
+ sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst;
sec_pipe->stream_res.dsc = NULL;
if (odm) {
if (pri_pipe->next_odm_pipe) {
if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
pipe = &context->res_ctx.pipe_ctx[old_index];
- pipe->pipe_idx = old_index;
+ pipe->pipe_idx = (uint8_t)old_index;
}
if (!pipe)
&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
if (context->res_ctx.pipe_ctx[i].stream == NULL) {
pipe = &context->res_ctx.pipe_ctx[i];
- pipe->pipe_idx = i;
+ pipe->pipe_idx = (uint8_t)i;
break;
}
}
for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
if (context->res_ctx.pipe_ctx[i].stream == NULL) {
pipe = &context->res_ctx.pipe_ctx[i];
- pipe->pipe_idx = i;
+ pipe->pipe_idx = (uint8_t)i;
break;
}
}
dc->caps.color.dpp.ocsc = 0;
dc->caps.color.mpc.gamut_remap = 1;
- dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3
+ dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;
dc->caps.color.mpc.ogam_ram = 1;
dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
if (!pool)
return NULL;
- if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn30_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
{
struct pp_smu_wm_range_sets ranges = {0};
- int i;
+ unsigned int i;
ranges.num_reader_wm_sets = 0;
ranges.num_reader_wm_sets = 1;
} else if (loaded_bb->num_states > 1) {
for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
- ranges.reader_wm_sets[i].wm_inst = i;
+ ranges.reader_wm_sets[i].wm_inst = (uint8_t)i;
ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
DC_FP_START();
dc->caps.color.dpp.ocsc = 0;
dc->caps.color.mpc.gamut_remap = 1;
- dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+ dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;
dc->caps.color.mpc.ogam_ram = 1;
dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
if (!pool)
return NULL;
- if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn301_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
dc->caps.color.dpp.ocsc = 0;
dc->caps.color.mpc.gamut_remap = 1;
- dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
+ dc->caps.color.mpc.num_3dluts = (uint16_t)pool->res_cap->num_mpc_3dlut;
dc->caps.color.mpc.ogam_ram = 1;
dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
if (!pool)
return NULL;
- if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn302_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return pool;
BREAK_TO_DEBUGGER();
dc->caps.color.dpp.ocsc = 0;
dc->caps.color.mpc.gamut_remap = 1;
- dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
+ dc->caps.color.mpc.num_3dluts = (uint16_t)pool->res_cap->num_mpc_3dlut;
dc->caps.color.mpc.ogam_ram = 1;
dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
if (!pool)
return NULL;
- if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn303_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return pool;
BREAK_TO_DEBUGGER();
dc->caps.color.dpp.ocsc = 0;
dc->caps.color.mpc.gamut_remap = 1;
- dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+ dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
dc->caps.color.mpc.ogam_ram = 1;
dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
if (!pool)
return NULL;
- if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn31_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
dc->caps.color.dpp.ocsc = 0;
dc->caps.color.mpc.gamut_remap = 1;
- dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+ dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
dc->caps.color.mpc.ogam_ram = 1;
dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
if (!pool)
return NULL;
- if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn314_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
dc->caps.color.dpp.ocsc = 0;
dc->caps.color.mpc.gamut_remap = 1;
- dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+ dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;
dc->caps.color.mpc.ogam_ram = 1;
dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
if (!pool)
return NULL;
- if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn315_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
dc->caps.color.dpp.ocsc = 0;
dc->caps.color.mpc.gamut_remap = 1;
- dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+ dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
dc->caps.color.mpc.ogam_ram = 1;
dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
if (!pool)
return NULL;
- if (dcn316_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn316_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
dc->caps.color.dpp.ocsc = 0;
dc->caps.color.mpc.gamut_remap = 1;
- dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
+ dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
dc->caps.color.mpc.ogam_ram = 1;
dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
if (!pool)
return NULL;
- if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn32_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) &&
!(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) {
secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
- secondary_pipe->pipe_idx = preferred_pipe_idx;
+ secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx;
}
}
if ((res_ctx->pipe_ctx[i].stream == NULL) &&
!(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) {
secondary_pipe = &res_ctx->pipe_ctx[i];
- secondary_pipe->pipe_idx = i;
+ secondary_pipe->pipe_idx = (uint8_t)i;
break;
}
}
pipe = &old_ctx->pipe_ctx[head_index];
if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) {
idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx];
- idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx;
+ idle_pipe->pipe_idx = (uint8_t)pipe->bottom_pipe->pipe_idx;
} else {
idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe);
if (!idle_pipe)
idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
- idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
+ idle_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[idle_pipe->pipe_idx]->inst;
return idle_pipe;
}
pool, opp_head_pipe);
if (free_pipe_idx >= 0) {
free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
- free_pipe->pipe_idx = free_pipe_idx;
+ free_pipe->pipe_idx = (uint8_t)free_pipe_idx;
free_pipe->stream = opp_head_pipe->stream;
free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg;
free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp;
free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx];
free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx];
free_pipe->plane_res.mpcc_inst =
- pool->dpps[free_pipe->pipe_idx]->inst;
+ (uint8_t)pool->dpps[free_pipe->pipe_idx]->inst;
} else {
ASSERT(opp_head_pipe);
free_pipe = NULL;
if (free_pipe_idx >= 0) {
free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
- free_pipe->pipe_idx = free_pipe_idx;
+ free_pipe->pipe_idx = (uint8_t)free_pipe_idx;
free_pipe->stream = otg_master->stream;
free_pipe->stream_res.tg = otg_master->stream_res.tg;
free_pipe->stream_res.dsc = NULL;
free_pipe->plane_res.ipp = pool->ipps[free_pipe_idx];
free_pipe->plane_res.xfm = pool->transforms[free_pipe_idx];
free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx];
- free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst;
+ free_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[free_pipe_idx]->inst;
free_pipe->dsc_padding_params = otg_master->dsc_padding_params;
if (free_pipe->stream->timing.flags.DSC == 1) {
dcn20_acquire_dsc(free_pipe->stream->ctx->dc,
dc->caps.color.dpp.ocsc = 0;
dc->caps.color.mpc.gamut_remap = 1;
- dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
+ dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
dc->caps.color.mpc.ogam_ram = 1;
dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
if (!pool)
return NULL;
- if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn321_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
dc->caps.color.dpp.ocsc = 0;
dc->caps.color.mpc.gamut_remap = 1;
- dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+ dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
dc->caps.color.mpc.ogam_ram = 1;
dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
if (!pool)
return NULL;
- if (dcn35_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn35_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
dc->caps.color.dpp.ocsc = 0;
dc->caps.color.mpc.gamut_remap = 1;
- dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+ dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
dc->caps.color.mpc.ogam_ram = 1;
dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
if (!pool)
return NULL;
- if (dcn351_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn351_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
dc->caps.color.dpp.ocsc = 0;
dc->caps.color.mpc.gamut_remap = 1;
- dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+ dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
dc->caps.color.mpc.ogam_ram = 1;
dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
if (!pool)
return NULL;
- if (dcn36_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn36_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
dc->caps.color.dpp.ocsc = 0;
dc->caps.color.mpc.gamut_remap = 1;
- dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
+ dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
dc->caps.color.mpc.ogam_ram = 1;
dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
if (!pool)
return NULL;
- if (dcn401_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn401_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
dc->caps.color.mpc.gamut_remap = 1;
//configurable to be before or after BLND in MPCC
- dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut;
+ dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;
dc->caps.color.mpc.num_rmcm_3dluts = 2;
dc->caps.color.mpc.ogam_ram = 1;
dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
if (!pool)
return NULL;
- if (dcn42_resource_construct(init_data->num_virtual_links, dc, pool))
+ if (dcn42_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
/* dcfclk */
if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) {
- dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels;
+ dml_clk_table->dcfclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dcfclk_levels;
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
if (i < dml_clk_table->dcfclk.num_clk_values) {
if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dcfclk_mhz &&
dml_clk_table->dcfclk.num_clk_values = i + 1;
} else {
dml_clk_table->dcfclk.clk_values_khz[i] = 0;
- dml_clk_table->dcfclk.num_clk_values = i;
+ dml_clk_table->dcfclk.num_clk_values = (uint8_t)i;
}
} else {
dml_clk_table->dcfclk.clk_values_khz[i] = dc_clk_table->entries[i].dcfclk_mhz * 1000;
/* fclk */
if (dc_clk_table->num_entries_per_clk.num_fclk_levels) {
- dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_fclk_levels;
+ dml_clk_table->fclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_fclk_levels;
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
if (i < dml_clk_table->fclk.num_clk_values) {
if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.fclk_mhz &&
dml_clk_table->fclk.num_clk_values = i + 1;
} else {
dml_clk_table->fclk.clk_values_khz[i] = 0;
- dml_clk_table->fclk.num_clk_values = i;
+ dml_clk_table->fclk.num_clk_values = (uint8_t)i;
}
} else {
dml_clk_table->fclk.clk_values_khz[i] = dc_clk_table->entries[i].fclk_mhz * 1000;
/* uclk */
if (dc_clk_table->num_entries_per_clk.num_memclk_levels) {
- dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels;
+ dml_clk_table->uclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_memclk_levels;
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
if (i < dml_clk_table->uclk.num_clk_values) {
if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.memclk_mhz &&
dml_clk_table->uclk.num_clk_values = i + 1;
} else {
dml_clk_table->uclk.clk_values_khz[i] = 0;
- dml_clk_table->uclk.num_clk_values = i;
+ dml_clk_table->uclk.num_clk_values = (uint8_t)i;
}
} else {
dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000;
/* dispclk */
if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) {
- dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels;
+ dml_clk_table->dispclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dispclk_levels;
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
if (i < dml_clk_table->dispclk.num_clk_values) {
if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dispclk_mhz &&
dml_clk_table->dispclk.num_clk_values = i + 1;
} else {
dml_clk_table->dispclk.clk_values_khz[i] = 0;
- dml_clk_table->dispclk.num_clk_values = i;
+ dml_clk_table->dispclk.num_clk_values = (uint8_t)i;
}
} else {
dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000;
/* dppclk */
if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) {
- dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels;
+ dml_clk_table->dppclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dppclk_levels;
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
if (i < dml_clk_table->dppclk.num_clk_values) {
if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dppclk_mhz &&
dml_clk_table->dppclk.num_clk_values = i + 1;
} else {
dml_clk_table->dppclk.clk_values_khz[i] = 0;
- dml_clk_table->dppclk.num_clk_values = i;
+ dml_clk_table->dppclk.num_clk_values = (uint8_t)i;
}
} else {
dml_clk_table->dppclk.clk_values_khz[i] = dc_clk_table->entries[i].dppclk_mhz * 1000;
/* dtbclk */
if (dc_clk_table->num_entries_per_clk.num_dtbclk_levels) {
- dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels;
+ dml_clk_table->dtbclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dtbclk_levels;
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
if (i < dml_clk_table->dtbclk.num_clk_values) {
if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dtbclk_mhz &&
dml_clk_table->dtbclk.num_clk_values = i + 1;
} else {
dml_clk_table->dtbclk.clk_values_khz[i] = 0;
- dml_clk_table->dtbclk.num_clk_values = i;
+ dml_clk_table->dtbclk.num_clk_values = (uint8_t)i;
}
} else {
dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000;
/* socclk */
if (dc_clk_table->num_entries_per_clk.num_socclk_levels) {
- dml_clk_table->socclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_socclk_levels;
+ dml_clk_table->socclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_socclk_levels;
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
if (i < dml_clk_table->socclk.num_clk_values) {
if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.socclk_mhz &&
dml_clk_table->socclk.num_clk_values = i + 1;
} else {
dml_clk_table->socclk.clk_values_khz[i] = 0;
- dml_clk_table->socclk.num_clk_values = i;
+ dml_clk_table->socclk.num_clk_values = (uint8_t)i;
}
} else {
dml_clk_table->socclk.clk_values_khz[i] = dc_clk_table->entries[i].socclk_mhz * 1000;
* for use with dml we need to fill in using an active value aiming for >= 2x DCFCLK
*/
if (dc_clk_table->num_entries_per_clk.num_fclk_levels && dc_clk_table->num_entries_per_clk.num_dcfclk_levels) {
- dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels;
- dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels;
+ dml_clk_table->fclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dcfclk_levels;
+ dml_clk_table->dcfclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dcfclk_levels;
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
if (i < dc_clk_table->num_entries_per_clk.num_dcfclk_levels) {
int j, max_fclk = 0;
/* uclk */
if (dc_clk_table->num_entries_per_clk.num_memclk_levels) {
- dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels;
+ dml_clk_table->uclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_memclk_levels;
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
if (i < dml_clk_table->uclk.num_clk_values) {
dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000;
/* dispclk */
if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) {
- dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels;
+ dml_clk_table->dispclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dispclk_levels;
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
if (i < dml_clk_table->dispclk.num_clk_values) {
dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000;
/* dppclk */
if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) {
- dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels;
+ dml_clk_table->dppclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dppclk_levels;
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
if (i < dml_clk_table->dppclk.num_clk_values) {
dml_clk_table->dppclk.clk_values_khz[i] = dc_clk_table->entries[i].dppclk_mhz * 1000;
/* dtbclk */
if (dc_clk_table->num_entries_per_clk.num_dtbclk_levels) {
- dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels;
+ dml_clk_table->dtbclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dtbclk_levels;
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
if (i < dml_clk_table->dtbclk.num_clk_values) {
dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000;
/* socclk */
if (dc_clk_table->num_entries_per_clk.num_socclk_levels) {
- dml_clk_table->socclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_socclk_levels;
+ dml_clk_table->socclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_socclk_levels;
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
if (i < dml_clk_table->socclk.num_clk_values) {
dml_clk_table->socclk.clk_values_khz[i] = dc_clk_table->entries[i].socclk_mhz * 1000;
projects / thirdparty / kernel / linux.git / commitdiff
