drm/amdgpu: add PTL enable/query gfx control support for GC 9.4.4

Introduce hardware detection, runtime state tracking and a
kgd->ptl_ctrl() callback to enable/disable/query PTL via the
PSP performance-monitor interface (commands 0xA0000000/1).
The driver now exposes PTL capability to KFD and keeps the
software state in sync with the hardware.

Signed-off-by: Perry Yuan <perry.yuan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index d0b8fb9317201535f213e7fd9e8b1d6ce38fa517..467a3dbe1bfad702cab3244764686b3cbcb7e348 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -2374,11 +2374,43 @@ static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block)
        return r;
 }
 
+static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool enable)
+{
+       struct amdgpu_ptl *ptl = &adev->psp.ptl;
+       uint32_t ptl_state = enable ? 1 : 0;
+       uint32_t fmt1, fmt2;
+       int r;
+
+       if (!adev->psp.funcs)
+               return -EOPNOTSUPP;
+
+       if (!ptl->hw_supported) {
+               fmt1 = GFX_FTYPE_I8;
+               fmt2 = GFX_FTYPE_BF16;
+       } else {
+               fmt1 = ptl->fmt1;
+               fmt2 = ptl->fmt2;
+       }
+
+       /* initialize PTL with default formats: GFX_FTYPE_I8 & GFX_FTYPE_BF16 */
+       r = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state,
+                                                       &fmt1, &fmt2);
+       if (r)
+               return r;
+
+       ptl->hw_supported = true;
+
+       return 0;
+}
+
 static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block)
 {
        struct amdgpu_device *adev = ip_block->adev;
        int i, num_xcc;
 
+       if (adev->psp.ptl.hw_supported)
+               gfx_v9_4_3_perf_monitor_ptl_init(adev, false);
+
        amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
        amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
        amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
@@ -2553,6 +2585,8 @@ static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block)
            adev->gfx.ras->enable_watchdog_timer)
                adev->gfx.ras->enable_watchdog_timer(adev);
 
+       gfx_v9_4_3_perf_monitor_ptl_init(adev, true);
+
        return 0;
 }