const struct resource_pool *pool = dc->res_pool;
struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;
- int i, input_idx, k;
+ unsigned int i;
+ int input_idx, k;
int vesa_sync_start, asic_blank_end, asic_blank_start;
bool bw_limit_pass;
float bw_limit;
context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
if (context->bw_ctx.bw.dcn.clk.dispclk_khz <
- dc->debug.min_disp_clk_khz) {
+ (int)dc->debug.min_disp_clk_khz) {
context->bw_ctx.bw.dcn.clk.dispclk_khz =
- dc->debug.min_disp_clk_khz;
+ (int)dc->debug.min_disp_clk_khz;
}
context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz /
PERFORMANCE_TRACE_END();
BW_VAL_TRACE_FINISH();
- if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->config.is_vmin_only_asic))
+ if (bw_limit_pass && v->voltage_level <= (int)get_highest_allowed_voltage_level(dc->config.is_vmin_only_asic))
return true;
else
return false;
struct resource_context *res_ctx,
display_e2e_pipe_params_st *pipes)
{
- int pipe_cnt, i;
+ unsigned int i;
+ int pipe_cnt;
dc_assert_fp_enabled();
static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
{
- int i;
+ unsigned int i;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
if (!context->res_ctx.pipe_ctx[i].stream)
continue;
/* The newVStartUp is 1 line before vsync point */
newVstartup = asic_blank_end + 1;
- *vstartup_start = ((newVstartup > *vstartup_start) ? newVstartup : *vstartup_start);
+ *vstartup_start = (((int)newVstartup > *vstartup_start) ? (int)newVstartup : *vstartup_start);
}
void dcn20_calculate_dlg_params(struct dc *dc,
int pipe_cnt,
int vlevel)
{
- int i, pipe_idx, active_hubp_count = 0;
+ int pipe_idx, active_hubp_count = 0;
+ unsigned int i;
dc_assert_fp_enabled();
context->bw_ctx.bw.dcn.clk.socclk_khz = (int)(context->bw_ctx.dml.vba.SOCCLK * 1000.0);
context->bw_ctx.bw.dcn.clk.dramclk_khz = (int)(context->bw_ctx.dml.vba.DRAMSpeed * 1000.0 / 16.0);
- if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz)
+ if ((int)dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz)
context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz;
context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000.0);
context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
- if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
- context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
+ if ((unsigned int)context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
+ context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)dc->debug.min_disp_clk_khz;
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
if (!context->res_ctx.pipe_ctx[i].stream)
enum dc_validate_mode validate_mode)
{
(void)validate_mode;
- int pipe_cnt, i;
+ int pipe_cnt;
+ unsigned int i;
bool synchronized_vblank = true;
struct resource_context *res_ctx = &context->res_ctx;
int vlevel,
enum dc_validate_mode validate_mode)
{
- int pipe_cnt, i, pipe_idx;
+ int pipe_cnt, pipe_idx;
+ unsigned int i;
dc_assert_fp_enabled();
{
int num_calculated_states = 0;
int min_dcfclk = 0;
- int i;
+ unsigned int i;
dc_assert_fp_enabled();
void dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st *bb,
struct pp_smu_nv_clock_table max_clocks)
{
- int i;
+ unsigned int i;
dc_assert_fp_enabled();
enum dc_validate_mode validate_mode)
{
uint32_t pipe_cnt;
- int i;
+ unsigned int i;
dc_assert_fp_enabled();
int vlevel_req,
enum dc_validate_mode validate_mode)
{
- int pipe_cnt, i, pipe_idx;
+ int pipe_cnt, pipe_idx;
+ unsigned int i;
int vlevel, vlevel_max;
struct wm_range_table_entry *table_entry;
struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
struct resource_context *res_ctx,
display_e2e_pipe_params_st *pipes)
{
- int pipe_cnt, i, j;
+ int pipe_cnt;
+ unsigned int i, j;
double max_calc_writeback_dispclk;
double writeback_dispclk;
struct writeback_st dout_wb = {0};
{
struct vba_vars_st *locals = &mode_lib->vba;
- int i;
- unsigned int j, k, m;
+ int idx;
+ unsigned int i, j, k, m;
/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
}
/*Mode Support, Voltage State and SOC Configuration*/
- for (i = mode_lib->vba.soc.num_states; i >= 0; i--) {
+ for (idx = mode_lib->vba.soc.num_states; idx >= 0; idx--) {
for (j = 0; j < 2; j++) {
enum dm_validation_status status = DML_VALIDATION_OK;
status = DML_FAIL_SCALE_RATIO_TAP;
} else if (mode_lib->vba.SourceFormatPixelAndScanSupport != true) {
status = DML_FAIL_SOURCE_PIXEL_FORMAT;
- } else if (locals->ViewportSizeSupport[i][0] != true) {
+ } else if (locals->ViewportSizeSupport[idx][0] != true) {
status = DML_FAIL_VIEWPORT_SIZE;
- } else if (locals->DIOSupport[i] != true) {
+ } else if (locals->DIOSupport[idx] != true) {
status = DML_FAIL_DIO_SUPPORT;
- } else if (locals->NotEnoughDSCUnits[i] != false) {
+ } else if (locals->NotEnoughDSCUnits[idx] != false) {
status = DML_FAIL_NOT_ENOUGH_DSC;
- } else if (locals->DSCCLKRequiredMoreThanSupported[i] != false) {
+ } else if (locals->DSCCLKRequiredMoreThanSupported[idx] != false) {
status = DML_FAIL_DSC_CLK_REQUIRED;
- } else if (locals->UrgentLatencySupport[i][j] != true) {
+ } else if (locals->UrgentLatencySupport[idx][j] != true) {
status = DML_FAIL_URGENT_LATENCY;
- } else if (locals->ROBSupport[i][0] != true) {
+ } else if (locals->ROBSupport[idx][0] != true) {
status = DML_FAIL_REORDERING_BUFFER;
- } else if (locals->DISPCLK_DPPCLK_Support[i][j] != true) {
+ } else if (locals->DISPCLK_DPPCLK_Support[idx][j] != true) {
status = DML_FAIL_DISPCLK_DPPCLK;
- } else if (locals->TotalAvailablePipesSupport[i][j] != true) {
+ } else if (locals->TotalAvailablePipesSupport[idx][j] != true) {
status = DML_FAIL_TOTAL_AVAILABLE_PIPES;
} else if (mode_lib->vba.NumberOfOTGSupport != true) {
status = DML_FAIL_NUM_OTG;
status = DML_FAIL_CURSOR_SUPPORT;
} else if (mode_lib->vba.PitchSupport != true) {
status = DML_FAIL_PITCH_SUPPORT;
- } else if (locals->PrefetchSupported[i][j] != true) {
+ } else if (locals->PrefetchSupported[idx][j] != true) {
status = DML_FAIL_PREFETCH_SUPPORT;
- } else if (locals->TotalVerticalActiveBandwidthSupport[i][0] != true) {
+ } else if (locals->TotalVerticalActiveBandwidthSupport[idx][0] != true) {
status = DML_FAIL_TOTAL_V_ACTIVE_BW;
- } else if (locals->VRatioInPrefetchSupported[i][j] != true) {
+ } else if (locals->VRatioInPrefetchSupported[idx][j] != true) {
status = DML_FAIL_V_RATIO_PREFETCH;
- } else if (locals->PTEBufferSizeNotExceeded[i][j] != true) {
+ } else if (locals->PTEBufferSizeNotExceeded[idx][j] != true) {
status = DML_FAIL_PTE_BUFFER_SIZE;
} else if (mode_lib->vba.NonsupportedDSCInputBPC != false) {
status = DML_FAIL_DSC_INPUT_BPC;
}
if (status == DML_VALIDATION_OK) {
- locals->ModeSupport[i][j] = true;
+ locals->ModeSupport[idx][j] = true;
} else {
- locals->ModeSupport[i][j] = false;
+ locals->ModeSupport[idx][j] = false;
}
- locals->ValidationStatus[i] = status;
+ locals->ValidationStatus[idx] = status;
}
}
{
{
struct vba_vars_st *locals = &mode_lib->vba;
- int i;
- unsigned int j, k, m;
+ int idx;
+ unsigned int i, j, k, m;
/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
}
/*Mode Support, Voltage State and SOC Configuration*/
- for (i = mode_lib->vba.soc.num_states; i >= 0; i--) {
+ for (idx = mode_lib->vba.soc.num_states; idx >= 0; idx--) {
for (j = 0; j < 2; j++) {
enum dm_validation_status status = DML_VALIDATION_OK;
status = DML_FAIL_SCALE_RATIO_TAP;
} else if (mode_lib->vba.SourceFormatPixelAndScanSupport != true) {
status = DML_FAIL_SOURCE_PIXEL_FORMAT;
- } else if (locals->ViewportSizeSupport[i][0] != true) {
+ } else if (locals->ViewportSizeSupport[idx][0] != true) {
status = DML_FAIL_VIEWPORT_SIZE;
- } else if (locals->DIOSupport[i] != true) {
+ } else if (locals->DIOSupport[idx] != true) {
status = DML_FAIL_DIO_SUPPORT;
- } else if (locals->NotEnoughDSCUnits[i] != false) {
+ } else if (locals->NotEnoughDSCUnits[idx] != false) {
status = DML_FAIL_NOT_ENOUGH_DSC;
- } else if (locals->DSCCLKRequiredMoreThanSupported[i] != false) {
+ } else if (locals->DSCCLKRequiredMoreThanSupported[idx] != false) {
status = DML_FAIL_DSC_CLK_REQUIRED;
- } else if (locals->UrgentLatencySupport[i][j] != true) {
+ } else if (locals->UrgentLatencySupport[idx][j] != true) {
status = DML_FAIL_URGENT_LATENCY;
- } else if (locals->ROBSupport[i][0] != true) {
+ } else if (locals->ROBSupport[idx][0] != true) {
status = DML_FAIL_REORDERING_BUFFER;
- } else if (locals->DISPCLK_DPPCLK_Support[i][j] != true) {
+ } else if (locals->DISPCLK_DPPCLK_Support[idx][j] != true) {
status = DML_FAIL_DISPCLK_DPPCLK;
- } else if (locals->TotalAvailablePipesSupport[i][j] != true) {
+ } else if (locals->TotalAvailablePipesSupport[idx][j] != true) {
status = DML_FAIL_TOTAL_AVAILABLE_PIPES;
} else if (mode_lib->vba.NumberOfOTGSupport != true) {
status = DML_FAIL_NUM_OTG;
status = DML_FAIL_CURSOR_SUPPORT;
} else if (mode_lib->vba.PitchSupport != true) {
status = DML_FAIL_PITCH_SUPPORT;
- } else if (locals->PrefetchSupported[i][j] != true) {
+ } else if (locals->PrefetchSupported[idx][j] != true) {
status = DML_FAIL_PREFETCH_SUPPORT;
- } else if (locals->TotalVerticalActiveBandwidthSupport[i][0] != true) {
+ } else if (locals->TotalVerticalActiveBandwidthSupport[idx][0] != true) {
status = DML_FAIL_TOTAL_V_ACTIVE_BW;
- } else if (locals->VRatioInPrefetchSupported[i][j] != true) {
+ } else if (locals->VRatioInPrefetchSupported[idx][j] != true) {
status = DML_FAIL_V_RATIO_PREFETCH;
- } else if (locals->PTEBufferSizeNotExceeded[i][j] != true) {
+ } else if (locals->PTEBufferSizeNotExceeded[idx][j] != true) {
status = DML_FAIL_PTE_BUFFER_SIZE;
} else if (mode_lib->vba.NonsupportedDSCInputBPC != false) {
status = DML_FAIL_DSC_INPUT_BPC;
}
if (status == DML_VALIDATION_OK) {
- locals->ModeSupport[i][j] = true;
+ locals->ModeSupport[idx][j] = true;
} else {
- locals->ModeSupport[i][j] = false;
+ locals->ModeSupport[idx][j] = false;
}
- locals->ValidationStatus[i] = status;
+ locals->ValidationStatus[idx] = status;
}
}
{
{
struct vba_vars_st *locals = &mode_lib->vba;
- int i;
- unsigned int j, k, m;
+ int idx;
+ unsigned int i, j, k, m;
/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
}
/*Mode Support, Voltage State and SOC Configuration*/
- for (i = mode_lib->vba.soc.num_states; i >= 0; i--) {
+ for (idx = mode_lib->vba.soc.num_states; idx >= 0; idx--) {
for (j = 0; j < 2; j++) {
enum dm_validation_status status = DML_VALIDATION_OK;
status = DML_FAIL_SCALE_RATIO_TAP;
} else if (!mode_lib->vba.SourceFormatPixelAndScanSupport) {
status = DML_FAIL_SOURCE_PIXEL_FORMAT;
- } else if (!locals->ViewportSizeSupport[i][0]) {
+ } else if (!locals->ViewportSizeSupport[idx][0]) {
status = DML_FAIL_VIEWPORT_SIZE;
- } else if (!locals->DIOSupport[i]) {
+ } else if (!locals->DIOSupport[idx]) {
status = DML_FAIL_DIO_SUPPORT;
- } else if (locals->NotEnoughDSCUnits[i]) {
+ } else if (locals->NotEnoughDSCUnits[idx]) {
status = DML_FAIL_NOT_ENOUGH_DSC;
- } else if (locals->DSCCLKRequiredMoreThanSupported[i]) {
+ } else if (locals->DSCCLKRequiredMoreThanSupported[idx]) {
status = DML_FAIL_DSC_CLK_REQUIRED;
- } else if (!locals->ROBSupport[i][0]) {
+ } else if (!locals->ROBSupport[idx][0]) {
status = DML_FAIL_REORDERING_BUFFER;
- } else if (!locals->DISPCLK_DPPCLK_Support[i][j]) {
+ } else if (!locals->DISPCLK_DPPCLK_Support[idx][j]) {
status = DML_FAIL_DISPCLK_DPPCLK;
- } else if (!locals->TotalAvailablePipesSupport[i][j]) {
+ } else if (!locals->TotalAvailablePipesSupport[idx][j]) {
status = DML_FAIL_TOTAL_AVAILABLE_PIPES;
} else if (!mode_lib->vba.NumberOfOTGSupport) {
status = DML_FAIL_NUM_OTG;
status = DML_FAIL_CURSOR_SUPPORT;
} else if (!mode_lib->vba.PitchSupport) {
status = DML_FAIL_PITCH_SUPPORT;
- } else if (!locals->TotalVerticalActiveBandwidthSupport[i][0]) {
+ } else if (!locals->TotalVerticalActiveBandwidthSupport[idx][0]) {
status = DML_FAIL_TOTAL_V_ACTIVE_BW;
- } else if (!locals->PTEBufferSizeNotExceeded[i][j]) {
+ } else if (!locals->PTEBufferSizeNotExceeded[idx][j]) {
status = DML_FAIL_PTE_BUFFER_SIZE;
} else if (mode_lib->vba.NonsupportedDSCInputBPC) {
status = DML_FAIL_DSC_INPUT_BPC;
} else if ((mode_lib->vba.HostVMEnable
- && !locals->ImmediateFlipSupportedForState[i][j])) {
+ && !locals->ImmediateFlipSupportedForState[idx][j])) {
status = DML_FAIL_HOST_VM_IMMEDIATE_FLIP;
- } else if (!locals->PrefetchSupported[i][j]) {
+ } else if (!locals->PrefetchSupported[idx][j]) {
status = DML_FAIL_PREFETCH_SUPPORT;
- } else if (!locals->VRatioInPrefetchSupported[i][j]) {
+ } else if (!locals->VRatioInPrefetchSupported[idx][j]) {
status = DML_FAIL_V_RATIO_PREFETCH;
}
if (status == DML_VALIDATION_OK) {
- locals->ModeSupport[i][j] = true;
+ locals->ModeSupport[idx][j] = true;
} else {
- locals->ModeSupport[i][j] = false;
+ locals->ModeSupport[idx][j] = false;
}
- locals->ValidationStatus[i] = status;
+ locals->ValidationStatus[idx] = status;
}
}
{
void dcn30_fpu_populate_dml_writeback_from_context(
struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
{
- int pipe_cnt, i, j;
+ int pipe_cnt;
+ unsigned int i, j;
double max_calc_writeback_dispclk;
double writeback_dispclk;
struct writeback_st dout_wb = {0};
{
int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
int i, pipe_idx;
+ unsigned int pipe_i, state_i;
double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb];
bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported;
unsigned int dummy_latency_index = 0;
/* Make set D = set A until set D is enabled */
context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
- for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
- if (!context->res_ctx.pipe_ctx[i].stream)
+ for (pipe_i = 0, pipe_idx = 0; pipe_i < dc->res_pool->pipe_count; pipe_i++) {
+ if (!context->res_ctx.pipe_ctx[pipe_i].stream)
continue;
pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
context->bw_ctx.dml.vba.DRAMSpeed <= 1700 &&
context->bw_ctx.dml.vba.DRAMSpeed >= 1500) {
- for (i = 0; i < dc->dml.soc.num_states; i++) {
- if (dc->dml.soc.clock_limits[i].dram_speed_mts > 1700) {
- context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[i].dram_speed_mts;
+ for (state_i = 0; state_i < dc->dml.soc.num_states; state_i++) {
+ if (dc->dml.soc.clock_limits[state_i].dram_speed_mts > 1700) {
+ context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[state_i].dram_speed_mts;
break;
}
}
double CursorRequestDeliveryTimePrefetch[]);
static void CalculateMetaAndPTETimes(
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
double TimePerVMRequestFlip[]);
static void CalculateStutterEfficiency(
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
long ROBBufferSizeInKByte,
double TotalDataReadBandwidth,
double DCFCLK,
static void CalculateSwathAndDETConfiguration(
bool ForceSingleDPP,
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
unsigned int DETBufferSizeInKByte,
double MaximumSwathWidthLuma[],
double MaximumSwathWidthChroma[],
bool *ViewportSizeSupport);
static void CalculateSwathWidth(
bool ForceSingleDPP,
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
enum source_format_class SourcePixelFormat[],
enum scan_direction_class SourceScan[],
unsigned int ViewportWidth[],
int MetaChunkSize,
bool GPUVMEnable,
bool HostVMEnable,
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
int NumberOfDPP[],
int dpte_group_bytes[],
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
max_vp_horz_width = (long)dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit);
max_vp_vert_height = (long)dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit);
eff_surf_width_l =
- (SurfaceWidthLuma > max_vp_horz_width ? max_vp_horz_width : SurfaceWidthLuma);
+ (SurfaceWidthLuma > (unsigned long)max_vp_horz_width ?
+ (unsigned long)max_vp_horz_width : SurfaceWidthLuma);
eff_surf_width_c = eff_surf_width_l / (1 + yuv420);
eff_surf_height_l = (
- SurfaceHeightLuma > max_vp_vert_height ?
- max_vp_vert_height : SurfaceHeightLuma);
+ SurfaceHeightLuma > (unsigned long)max_vp_vert_height ?
+ (unsigned long)max_vp_vert_height : SurfaceHeightLuma);
eff_surf_height_c = eff_surf_height_l / (1 + yuv420);
full_swath_bytes_horz_wc_l = eff_surf_width_l * RequestHeight256ByteLuma * BytePerPixelY;
{
struct vba_vars_st *v = &mode_lib->vba;
int MinPrefetchMode, MaxPrefetchMode;
- int i, start_state;
- unsigned int j, k, m;
+ int idx, start_state;
+ unsigned int i, j, k, m;
bool EnoughWritebackUnits = true;
bool WritebackModeSupport = true;
bool ViewportExceedsSurface = false;
}
/*Mode Support, Voltage State and SOC Configuration*/
- for (i = v->soc.num_states - 1; i >= start_state; i--) {
+ for (idx = v->soc.num_states - 1; idx >= start_state; idx--) {
for (j = 0; j < 2; j++) {
- if (v->ScaleRatioAndTapsSupport == 1 && v->SourceFormatPixelAndScanSupport == 1 && v->ViewportSizeSupport[i][j] == 1
- && v->DIOSupport[i] == 1 && v->ODMCombine4To1SupportCheckOK[i] == 1
- && v->NotEnoughDSCUnits[i] == 0
- && v->DTBCLKRequiredMoreThanSupported[i] == 0
- && v->ROBSupport[i][j] == 1 && v->DISPCLK_DPPCLK_Support[i][j] == 1 && v->TotalAvailablePipesSupport[i][j] == 1
+ if (v->ScaleRatioAndTapsSupport == 1 && v->SourceFormatPixelAndScanSupport == 1
+ && v->ViewportSizeSupport[idx][j] == 1
+ && v->DIOSupport[idx] == 1 && v->ODMCombine4To1SupportCheckOK[idx] == 1
+ && v->NotEnoughDSCUnits[idx] == 0
+ && v->DTBCLKRequiredMoreThanSupported[idx] == 0
+ && v->ROBSupport[idx][j] == 1 && v->DISPCLK_DPPCLK_Support[idx][j] == 1
+ && v->TotalAvailablePipesSupport[idx][j] == 1
&& EnoughWritebackUnits == 1 && WritebackModeSupport == 1
- && v->WritebackLatencySupport == 1 && v->WritebackScaleRatioAndTapsSupport == 1 && v->CursorSupport == 1 && v->PitchSupport == 1
- && ViewportExceedsSurface == 0 && v->PrefetchSupported[i][j] == 1 && v->DynamicMetadataSupported[i][j] == 1
- && v->TotalVerticalActiveBandwidthSupport[i][j] == 1 && v->VRatioInPrefetchSupported[i][j] == 1
- && v->PTEBufferSizeNotExceeded[i][j] == 1 && v->NonsupportedDSCInputBPC == 0
+ && v->WritebackLatencySupport == 1 && v->WritebackScaleRatioAndTapsSupport == 1
+ && v->CursorSupport == 1 && v->PitchSupport == 1
+ && ViewportExceedsSurface == 0 && v->PrefetchSupported[idx][j] == 1
+ && v->DynamicMetadataSupported[idx][j] == 1
+ && v->TotalVerticalActiveBandwidthSupport[idx][j] == 1
+ && v->VRatioInPrefetchSupported[idx][j] == 1
+ && v->PTEBufferSizeNotExceeded[idx][j] == 1 && v->NonsupportedDSCInputBPC == 0
&& ((v->HostVMEnable == 0 && v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)
- || v->ImmediateFlipSupportedForState[i][j] == true)) {
- v->ModeSupport[i][j] = true;
+ || v->ImmediateFlipSupportedForState[idx][j] == true)) {
+ v->ModeSupport[idx][j] = true;
} else {
- v->ModeSupport[i][j] = false;
+ v->ModeSupport[idx][j] = false;
}
}
}
{
unsigned int MaximumMPCCombine = 0;
- for (i = v->soc.num_states; i >= start_state; i--) {
- if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {
- v->VoltageLevel = i;
- v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;
- if (v->ModeSupport[i][1] == true) {
+ for (idx = v->soc.num_states; idx >= start_state; idx--) {
+ if (idx == (int)v->soc.num_states || v->ModeSupport[idx][0] == true
+ || v->ModeSupport[idx][1] == true) {
+ v->VoltageLevel = idx;
+ v->ModeIsSupported = v->ModeSupport[idx][0] == true || v->ModeSupport[idx][1] == true;
+ if (v->ModeSupport[idx][1] == true) {
MaximumMPCCombine = 1;
} else {
MaximumMPCCombine = 0;
}
static void CalculateMetaAndPTETimes(
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
}
static void CalculateStutterEfficiency(
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
long ROBBufferSizeInKByte,
double TotalDataReadBandwidth,
double DCFCLK,
static void CalculateSwathAndDETConfiguration(
bool ForceSingleDPP,
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
unsigned int DETBufferSizeInKByte,
double MaximumSwathWidthLuma[],
double MaximumSwathWidthChroma[],
long RoundedUpSwathSizeBytesC = 0;
double SwathWidthSingleDPP[DC__NUM_DPP__MAX] = { 0 };
double SwathWidthSingleDPPChroma[DC__NUM_DPP__MAX] = { 0 };
- int k;
+ unsigned int k;
CalculateSwathWidth(
ForceSingleDPP,
}
if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC
- <= DETBufferSizeInKByte * 1024 / 2) {
+ <= (long)DETBufferSizeInKByte * 1024 / 2) {
SwathHeightY[k] = MaximumSwathHeightY[k];
SwathHeightC[k] = MaximumSwathHeightC[k];
RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY;
RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC;
} else if (RoundedUpMaxSwathSizeBytesY >= 1.5 * RoundedUpMaxSwathSizeBytesC
&& RoundedUpMinSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC
- <= DETBufferSizeInKByte * 1024 / 2) {
+ <= (long)DETBufferSizeInKByte * 1024 / 2) {
SwathHeightY[k] = MinimumSwathHeightY;
SwathHeightC[k] = MaximumSwathHeightC[k];
RoundedUpSwathSizeBytesY = RoundedUpMinSwathSizeBytesY;
RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC;
} else if (RoundedUpMaxSwathSizeBytesY < 1.5 * RoundedUpMaxSwathSizeBytesC
&& RoundedUpMaxSwathSizeBytesY + RoundedUpMinSwathSizeBytesC
- <= DETBufferSizeInKByte * 1024 / 2) {
+ <= (long)DETBufferSizeInKByte * 1024 / 2) {
SwathHeightY[k] = MaximumSwathHeightY[k];
SwathHeightC[k] = MinimumSwathHeightC;
RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY;
}
if (RoundedUpMinSwathSizeBytesY + RoundedUpMinSwathSizeBytesC
- > DETBufferSizeInKByte * 1024 / 2
+ > (long)DETBufferSizeInKByte * 1024 / 2
|| SwathWidth[k] > MaximumSwathWidthLuma[k]
|| (SwathHeightC[k] > 0
&& SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) {
static void CalculateSwathWidth(
bool ForceSingleDPP,
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
enum source_format_class SourcePixelFormat[],
enum scan_direction_class SourceScan[],
unsigned int ViewportWidth[],
int MetaChunkSize,
bool GPUVMEnable,
bool HostVMEnable,
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
int NumberOfDPP[],
int dpte_group_bytes[],
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool);
struct clk_limit_table *clk_table = &bw_params->clk_table;
unsigned int i, closest_clk_lvl;
- int j = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0;
+ int j = 0;
+ unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
dc_assert_fp_enabled();
int pipe_cnt,
int vlevel_req)
{
- int i, pipe_idx;
+ unsigned int i, pipe_idx;
int vlevel, vlevel_max;
struct wm_range_table_entry *table_entry;
struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
if (bw_params->clk_table.entries[0].memclk_mhz) {
- int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
+ unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
if (bw_params->clk_table.entries[0].memclk_mhz) {
- int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
+ unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
int pipe_cnt,
int vlevel)
{
- int i, pipe_idx, total_det = 0, active_hubp_count = 0;
+ int total_det = 0, active_hubp_count = 0;
+ unsigned int i, pipe_idx;
double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
uint32_t cstate_enter_plus_exit_z8_ns;
+ uint32_t minimum_z8_residency_time_ns =
+ (uint32_t)dc->debug.minimum_z8_residency_time * 1000U;
dc_assert_fp_enabled();
(uint32_t)(get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000);
if (get_stutter_period(&context->bw_ctx.dml, pipes, pipe_cnt) < dc->debug.minimum_z8_residency_time &&
- cstate_enter_plus_exit_z8_ns < dc->debug.minimum_z8_residency_time * 1000)
- cstate_enter_plus_exit_z8_ns = dc->debug.minimum_z8_residency_time * 1000;
+ cstate_enter_plus_exit_z8_ns < minimum_z8_residency_time_ns)
+ cstate_enter_plus_exit_z8_ns = minimum_z8_residency_time_ns;
/* Set A:
* All clocks min required
struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;
struct clk_limit_table *clk_table = &bw_params->clk_table;
unsigned int i, closest_clk_lvl;
- int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
+ unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
int j;
dc_assert_fp_enabled();
void dcn315_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
{
struct clk_limit_table *clk_table = &bw_params->clk_table;
- int i, max_dispclk_mhz = 0, max_dppclk_mhz = 0;
+ unsigned int i, max_dispclk_mhz = 0, max_dppclk_mhz = 0;
dc_assert_fp_enabled();
struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;
struct clk_limit_table *clk_table = &bw_params->clk_table;
unsigned int i, closest_clk_lvl;
- int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
+ unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
int j;
dc_assert_fp_enabled();
double detile_buf_vp_horz_limit;
double detile_buf_vp_vert_limit;
- int MAS_vp_horz_limit;
- int MAS_vp_vert_limit;
- int max_vp_horz_width;
- int max_vp_vert_height;
+ unsigned int MAS_vp_horz_limit;
+ unsigned int MAS_vp_vert_limit;
+ unsigned int max_vp_horz_width;
+ unsigned int max_vp_vert_height;
int eff_surf_width_l;
int eff_surf_width_c;
int eff_surf_height_l;
static void PatchDETBufferSizeInKByte(unsigned int NumberOfActivePlanes, int NoOfDPPThisState[], unsigned int config_return_buffer_size_in_kbytes, unsigned int DETBufferSizeInKByte[])
{
- int i, total_pipes = 0;
+ int total_pipes = 0;
+ unsigned int i;
for (i = 0; i < NumberOfActivePlanes; i++)
total_pipes += NoOfDPPThisState[i];
DETBufferSizeInKByte[0] = ((config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB) / 64 / total_pipes) * 64;
{
struct vba_vars_st *v = &mode_lib->vba;
- int i, j;
- unsigned int k, m;
+ int idx;
+ unsigned int i, j, k, m;
int ReorderingBytes;
int MinPrefetchMode = 0, MaxPrefetchMode = 2;
bool NoChroma = true;
}
/*Mode Support, Voltage State and SOC Configuration*/
- for (i = v->soc.num_states - 1; i >= 0; i--) {
+ for (idx = (int)v->soc.num_states - 1; idx >= 0; idx--) {
for (j = 0; j < 2; j++) {
- if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true && v->ViewportSizeSupport[i][j] == true
- && v->LinkCapacitySupport[i] == true && !P2IWith420 && !DSCOnlyIfNecessaryWithBPP
- && !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[i] == true && v->NotEnoughDSCUnits[i] == false
- && v->DTBCLKRequiredMoreThanSupported[i] == false
- && v->ROBSupport[i][j] == true && v->DISPCLK_DPPCLK_Support[i][j] == true
- && v->TotalAvailablePipesSupport[i][j] == true && EnoughWritebackUnits == true
+ if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true
+ && v->ViewportSizeSupport[idx][j] == true
+ && v->LinkCapacitySupport[idx] == true && !P2IWith420
+ && !DSCOnlyIfNecessaryWithBPP
+ && !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[idx] == true
+ && v->NotEnoughDSCUnits[idx] == false
+ && v->DTBCLKRequiredMoreThanSupported[idx] == false
+ && v->ROBSupport[idx][j] == true && v->DISPCLK_DPPCLK_Support[idx][j] == true
+ && v->TotalAvailablePipesSupport[idx][j] == true && EnoughWritebackUnits == true
&& v->WritebackLatencySupport == true && v->WritebackScaleRatioAndTapsSupport == true
- && v->CursorSupport == true && v->PitchSupport == true && ViewportExceedsSurface == false
- && v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true
- && v->TotalVerticalActiveBandwidthSupport[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true
- && v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false
+ && v->CursorSupport == true && v->PitchSupport == true
+ && ViewportExceedsSurface == false
+ && v->PrefetchSupported[idx][j] == true
+ && v->DynamicMetadataSupported[idx][j] == true
+ && v->TotalVerticalActiveBandwidthSupport[idx][j] == true
+ && v->VRatioInPrefetchSupported[idx][j] == true
+ && v->PTEBufferSizeNotExceeded[idx][j] == true
+ && v->NonsupportedDSCInputBPC == false
&& ((v->HostVMEnable == false
&& v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)
- || v->ImmediateFlipSupportedForState[i][j] == true)
+ || v->ImmediateFlipSupportedForState[idx][j] == true)
&& FMTBufferExceeded == false) {
- v->ModeSupport[i][j] = true;
+ v->ModeSupport[idx][j] = true;
} else {
- v->ModeSupport[i][j] = false;
+ v->ModeSupport[idx][j] = false;
#ifdef __DML_VBA_DEBUG__
if (v->ScaleRatioAndTapsSupport == false)
dml_print("DML SUPPORT: ScaleRatioAndTapsSupport failed");
if (v->SourceFormatPixelAndScanSupport == false)
dml_print("DML SUPPORT: SourceFormatPixelAndScanSupport failed");
- if (v->ViewportSizeSupport[i][j] == false)
+ if (v->ViewportSizeSupport[idx][j] == false)
dml_print("DML SUPPORT: ViewportSizeSupport failed");
- if (v->LinkCapacitySupport[i] == false)
+ if (v->LinkCapacitySupport[idx] == false)
dml_print("DML SUPPORT: LinkCapacitySupport failed");
- if (v->ODMCombine4To1SupportCheckOK[i] == false)
+ if (v->ODMCombine4To1SupportCheckOK[idx] == false)
dml_print("DML SUPPORT: DSC422NativeNotSupported failed");
- if (v->NotEnoughDSCUnits[i] == true)
+ if (v->NotEnoughDSCUnits[idx] == true)
dml_print("DML SUPPORT: NotEnoughDSCUnits");
- if (v->DTBCLKRequiredMoreThanSupported[i] == true)
+ if (v->DTBCLKRequiredMoreThanSupported[idx] == true)
dml_print("DML SUPPORT: DTBCLKRequiredMoreThanSupported");
- if (v->ROBSupport[i][j] == false)
+ if (v->ROBSupport[idx][j] == false)
dml_print("DML SUPPORT: ROBSupport failed");
- if (v->DISPCLK_DPPCLK_Support[i][j] == false)
+ if (v->DISPCLK_DPPCLK_Support[idx][j] == false)
dml_print("DML SUPPORT: DISPCLK_DPPCLK_Support failed");
- if (v->TotalAvailablePipesSupport[i][j] == false)
+ if (v->TotalAvailablePipesSupport[idx][j] == false)
dml_print("DML SUPPORT: DSC422NativeNotSupported failed");
if (EnoughWritebackUnits == false)
dml_print("DML SUPPORT: DSC422NativeNotSupported failed");
dml_print("DML SUPPORT: PitchSupport failed");
if (ViewportExceedsSurface == true)
dml_print("DML SUPPORT: ViewportExceedsSurface failed");
- if (v->PrefetchSupported[i][j] == false)
+ if (v->PrefetchSupported[idx][j] == false)
dml_print("DML SUPPORT: PrefetchSupported failed");
- if (v->DynamicMetadataSupported[i][j] == false)
+ if (v->DynamicMetadataSupported[idx][j] == false)
dml_print("DML SUPPORT: DSC422NativeNotSupported failed");
- if (v->TotalVerticalActiveBandwidthSupport[i][j] == false)
+ if (v->TotalVerticalActiveBandwidthSupport[idx][j] == false)
dml_print("DML SUPPORT: TotalVerticalActiveBandwidthSupport failed");
- if (v->VRatioInPrefetchSupported[i][j] == false)
+ if (v->VRatioInPrefetchSupported[idx][j] == false)
dml_print("DML SUPPORT: VRatioInPrefetchSupported failed");
- if (v->PTEBufferSizeNotExceeded[i][j] == false)
+ if (v->PTEBufferSizeNotExceeded[idx][j] == false)
dml_print("DML SUPPORT: PTEBufferSizeNotExceeded failed");
if (v->NonsupportedDSCInputBPC == true)
dml_print("DML SUPPORT: NonsupportedDSCInputBPC failed");
if (!((v->HostVMEnable == false
&& v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)
- || v->ImmediateFlipSupportedForState[i][j] == true))
+ || v->ImmediateFlipSupportedForState[idx][j] == true))
dml_print("DML SUPPORT: ImmediateFlipRequirement failed");
if (FMTBufferExceeded == true)
dml_print("DML SUPPORT: FMTBufferExceeded failed");
{
unsigned int MaximumMPCCombine = 0;
- for (i = v->soc.num_states; i >= 0; i--) {
- if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {
- v->VoltageLevel = i;
- v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;
- if (v->ModeSupport[i][0] == true) {
+ for (idx = (int)v->soc.num_states; idx >= 0; idx--) {
+ if (idx == (int)v->soc.num_states || v->ModeSupport[idx][0] == true
+ || v->ModeSupport[idx][1] == true) {
+ v->VoltageLevel = idx;
+ v->ModeIsSupported = v->ModeSupport[idx][0] == true || v->ModeSupport[idx][1] == true;
+ if (v->ModeSupport[idx][0] == true) {
MaximumMPCCombine = 0;
} else {
MaximumMPCCombine = 1;
}
}
v->ImmediateFlipSupport = v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine];
- for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
+ for (k = 0; k < v->NumberOfActivePlanes; k++) {
v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
}
double SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank;
double WritebackDRAMClockChangeLatencyHiding;
double TotalPixelBW = 0.0;
- int k, j;
+ unsigned int k, j;
v->UrgentWatermark = UrgentLatency + ExtraLatency;
double DisplayPipeLineDeliveryTimeLuma;
double DisplayPipeLineDeliveryTimeChroma;
double ReadBandwidth = 0.0;
- int k;
+ unsigned int k;
for (k = 0; k < NumberOfActivePlanes; ++k) {
double CursorRequestDeliveryTimePrefetch[])
{
double req_per_swath_ub;
- int k;
+ unsigned int k;
for (k = 0; k < NumberOfActivePlanes; ++k) {
if (VRatio[k] <= 1) {
(void)dpte_row_width_chroma_ub;
int num_group_per_lower_vm_stage;
int num_req_per_lower_vm_stage;
- int k;
+ unsigned int k;
for (k = 0; k < NumberOfActivePlanes; ++k) {
if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
int MaximumSwathHeightC[DC__NUM_DPP__MAX];
int MinimumSwathHeightY;
int MinimumSwathHeightC;
- int RoundedUpMaxSwathSizeBytesY;
- int RoundedUpMaxSwathSizeBytesC;
- int RoundedUpMinSwathSizeBytesY;
- int RoundedUpMinSwathSizeBytesC;
- int RoundedUpSwathSizeBytesY;
- int RoundedUpSwathSizeBytesC;
+ unsigned int RoundedUpMaxSwathSizeBytesY;
+ unsigned int RoundedUpMaxSwathSizeBytesC;
+ unsigned int RoundedUpMinSwathSizeBytesY;
+ unsigned int RoundedUpMinSwathSizeBytesC;
+ unsigned int RoundedUpSwathSizeBytesY;
+ unsigned int RoundedUpSwathSizeBytesC;
double SwathWidthSingleDPP[DC__NUM_DPP__MAX];
double SwathWidthSingleDPPChroma[DC__NUM_DPP__MAX];
int k;
int ReorderingBytes)
{
struct vba_vars_st *v = &mode_lib->vba;
- int dummy1, i, j, k;
+ int dummy1;
+ unsigned int j, k;
+ unsigned int i;
double NormalEfficiency, dummy2, dummy3;
double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];
+ v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]);
}
- for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
+ for (k = 0; k < v->NumberOfActivePlanes; ++k)
NoOfDPPState[k] = v->NoOfDPP[i][j][k];
- }
MinimumTWait = CalculateTWait(MaxPrefetchMode, v->FinalDRAMClockChangeLatency, v->UrgLatency[i], v->SREnterPlusExitTime);
NonDPTEBandwidth = v->TotalVActivePixelBandwidth[i][j] + v->TotalVActiveCursorBandwidth[i][j] + v->TotalMetaRowBandwidth[i][j];
}
}
DCFCLKRequiredForPeakBandwidth = 0;
- for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
+ for (k = 0; k < v->NumberOfActivePlanes; ++k)
DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k];
- }
MinimumTvmPlus2Tr0 = v->UrgLatency[i]
* (v->GPUVMEnable == true ?
(v->HostVMEnable == true ?
struct _vcs_dpi_voltage_scaling_st *clock_limits =
dcn3_14_soc.clock_limits;
unsigned int i, closest_clk_lvl;
- int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
+ unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
int j;
dc_assert_fp_enabled();
display_e2e_pipe_params_st *pipes,
enum dc_validate_mode validate_mode)
{
- int i, pipe_cnt;
+ int pipe_cnt;
+ unsigned int i;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = 0;
bool upscaled = false;
double CursorRequestDeliveryTimePrefetch[]);
static void CalculateMetaAndPTETimes(
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
double detile_buf_vp_horz_limit;
double detile_buf_vp_vert_limit;
- int MAS_vp_horz_limit;
- int MAS_vp_vert_limit;
- int max_vp_horz_width;
- int max_vp_vert_height;
- int eff_surf_width_l;
- int eff_surf_width_c;
- int eff_surf_height_l;
- int eff_surf_height_c;
+ unsigned int MAS_vp_horz_limit;
+ unsigned int MAS_vp_vert_limit;
+ unsigned int max_vp_horz_width;
+ unsigned int max_vp_vert_height;
+ unsigned int eff_surf_width_l;
+ unsigned int eff_surf_width_c;
+ unsigned int eff_surf_height_l;
+ unsigned int eff_surf_height_c;
int full_swath_bytes_horz_wc_l;
int full_swath_bytes_horz_wc_c;
{
struct vba_vars_st *v = &mode_lib->vba;
- int i, j;
+ int j;
+ unsigned int i;
unsigned int k, m;
int ReorderingBytes;
int MinPrefetchMode = 0, MaxPrefetchMode = 2;
}
/*Mode Support, Voltage State and SOC Configuration*/
- for (i = v->soc.num_states - 1; i >= 0; i--) {
+ for (int idx = (int)v->soc.num_states - 1; idx >= 0; idx--) {
for (j = 0; j < 2; j++) {
- if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true && v->ViewportSizeSupport[i][j] == true
- && v->LinkCapacitySupport[i] == true && !P2IWith420 && !DSCOnlyIfNecessaryWithBPP
- && !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[i] == true && v->NotEnoughDSCUnits[i] == false
- && v->DTBCLKRequiredMoreThanSupported[i] == false
- && v->ROBSupport[i][j] == true && v->DISPCLK_DPPCLK_Support[i][j] == true
- && v->TotalAvailablePipesSupport[i][j] == true && EnoughWritebackUnits == true
+ if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true
+ && v->ViewportSizeSupport[idx][j] == true
+ && v->LinkCapacitySupport[idx] == true && !P2IWith420
+ && !DSCOnlyIfNecessaryWithBPP
+ && !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[idx] == true
+ && v->NotEnoughDSCUnits[idx] == false
+ && v->DTBCLKRequiredMoreThanSupported[idx] == false
+ && v->ROBSupport[idx][j] == true && v->DISPCLK_DPPCLK_Support[idx][j] == true
+ && v->TotalAvailablePipesSupport[idx][j] == true && EnoughWritebackUnits == true
&& v->WritebackLatencySupport == true && v->WritebackScaleRatioAndTapsSupport == true
- && v->CursorSupport == true && v->PitchSupport == true && ViewportExceedsSurface == false
- && v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true
- && v->TotalVerticalActiveBandwidthSupport[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true
- && v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false
+ && v->CursorSupport == true && v->PitchSupport == true
+ && ViewportExceedsSurface == false
+ && v->PrefetchSupported[idx][j] == true
+ && v->DynamicMetadataSupported[idx][j] == true
+ && v->TotalVerticalActiveBandwidthSupport[idx][j] == true
+ && v->VRatioInPrefetchSupported[idx][j] == true
+ && v->PTEBufferSizeNotExceeded[idx][j] == true
+ && v->NonsupportedDSCInputBPC == false
&& ((v->HostVMEnable == false
&& v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)
- || v->ImmediateFlipSupportedForState[i][j] == true)
+ || v->ImmediateFlipSupportedForState[idx][j] == true)
&& FMTBufferExceeded == false) {
- v->ModeSupport[i][j] = true;
+ v->ModeSupport[idx][j] = true;
} else {
- v->ModeSupport[i][j] = false;
+ v->ModeSupport[idx][j] = false;
}
}
}
- for (i = v->soc.num_states; i >= 0; i--) {
+ for (int idx = (int)v->soc.num_states; idx >= 0; idx--) {
for (j = 0; j < 2; j++) {
enum dm_validation_status status = DML_VALIDATION_OK;
status = DML_FAIL_SCALE_RATIO_TAP;
} else if (!v->SourceFormatPixelAndScanSupport) {
status = DML_FAIL_SOURCE_PIXEL_FORMAT;
- } else if (!v->ViewportSizeSupport[i][j]) {
+ } else if (!v->ViewportSizeSupport[idx][j]) {
status = DML_FAIL_VIEWPORT_SIZE;
} else if (P2IWith420) {
status = DML_FAIL_P2I_WITH_420;
status = DML_FAIL_DSC_ONLY_IF_NECESSARY_WITH_BPP;
} else if (DSC422NativeNotSupported) {
status = DML_FAIL_NOT_DSC422_NATIVE;
- } else if (!v->ODMCombine4To1SupportCheckOK[i]) {
+ } else if (!v->ODMCombine4To1SupportCheckOK[idx]) {
status = DML_FAIL_ODM_COMBINE4TO1;
- } else if (v->NotEnoughDSCUnits[i]) {
+ } else if (v->NotEnoughDSCUnits[idx]) {
status = DML_FAIL_NOT_ENOUGH_DSC;
- } else if (!v->ROBSupport[i][j]) {
+ } else if (!v->ROBSupport[idx][j]) {
status = DML_FAIL_REORDERING_BUFFER;
- } else if (!v->DISPCLK_DPPCLK_Support[i][j]) {
+ } else if (!v->DISPCLK_DPPCLK_Support[idx][j]) {
status = DML_FAIL_DISPCLK_DPPCLK;
- } else if (!v->TotalAvailablePipesSupport[i][j]) {
+ } else if (!v->TotalAvailablePipesSupport[idx][j]) {
status = DML_FAIL_TOTAL_AVAILABLE_PIPES;
} else if (!EnoughWritebackUnits) {
status = DML_FAIL_ENOUGH_WRITEBACK_UNITS;
status = DML_FAIL_PITCH_SUPPORT;
} else if (ViewportExceedsSurface) {
status = DML_FAIL_VIEWPORT_EXCEEDS_SURFACE;
- } else if (!v->PrefetchSupported[i][j]) {
+ } else if (!v->PrefetchSupported[idx][j]) {
status = DML_FAIL_PREFETCH_SUPPORT;
- } else if (!v->DynamicMetadataSupported[i][j]) {
+ } else if (!v->DynamicMetadataSupported[idx][j]) {
status = DML_FAIL_DYNAMIC_METADATA;
- } else if (!v->TotalVerticalActiveBandwidthSupport[i][j]) {
+ } else if (!v->TotalVerticalActiveBandwidthSupport[idx][j]) {
status = DML_FAIL_TOTAL_V_ACTIVE_BW;
- } else if (!v->VRatioInPrefetchSupported[i][j]) {
+ } else if (!v->VRatioInPrefetchSupported[idx][j]) {
status = DML_FAIL_V_RATIO_PREFETCH;
- } else if (!v->PTEBufferSizeNotExceeded[i][j]) {
+ } else if (!v->PTEBufferSizeNotExceeded[idx][j]) {
status = DML_FAIL_PTE_BUFFER_SIZE;
} else if (v->NonsupportedDSCInputBPC) {
status = DML_FAIL_DSC_INPUT_BPC;
} else if ((v->HostVMEnable
- && !v->ImmediateFlipSupportedForState[i][j])) {
+ && !v->ImmediateFlipSupportedForState[idx][j])) {
status = DML_FAIL_HOST_VM_IMMEDIATE_FLIP;
} else if (FMTBufferExceeded) {
status = DML_FAIL_FMT_BUFFER_EXCEEDED;
}
- mode_lib->vba.ValidationStatus[i] = status;
+ mode_lib->vba.ValidationStatus[idx] = status;
}
}
{
unsigned int MaximumMPCCombine = 0;
-
- for (i = v->soc.num_states; i >= 0; i--) {
- if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {
- v->VoltageLevel = i;
- v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;
- if (v->ModeSupport[i][0] == true) {
+ for (int idx = (int)v->soc.num_states; idx >= 0; idx--) {
+ if (idx == (int)v->soc.num_states || v->ModeSupport[idx][0] == true
+ || v->ModeSupport[idx][1] == true) {
+ v->VoltageLevel = idx;
+ v->ModeIsSupported = v->ModeSupport[idx][0] == true || v->ModeSupport[idx][1] == true;
+ if (v->ModeSupport[idx][0] == true) {
MaximumMPCCombine = 0;
} else {
MaximumMPCCombine = 1;
}
}
v->ImmediateFlipSupport = v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine];
- for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
+ for (k = 0; k < v->NumberOfActivePlanes; k++) {
v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
}
double SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank;
double WritebackDRAMClockChangeLatencyHiding;
double TotalPixelBW = 0.0;
- int k, j;
+ unsigned int k, j;
v->UrgentWatermark = UrgentLatency + ExtraLatency;
double DisplayPipeLineDeliveryTimeLuma;
double DisplayPipeLineDeliveryTimeChroma;
double ReadBandwidth = 0.0;
- int k;
+ unsigned int k;
for (k = 0; k < NumberOfActivePlanes; ++k) {
double CursorRequestDeliveryTimePrefetch[])
{
double req_per_swath_ub;
- int k;
+ unsigned int k;
for (k = 0; k < NumberOfActivePlanes; ++k) {
if (VRatio[k] <= 1) {
}
static void CalculateMetaAndPTETimes(
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
unsigned int dpte_groups_per_row_luma_ub;
unsigned int dpte_group_width_chroma;
unsigned int dpte_groups_per_row_chroma_ub;
- int k;
+ unsigned int k;
for (k = 0; k < NumberOfActivePlanes; ++k) {
DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
(void)dpte_row_width_chroma_ub;
int num_group_per_lower_vm_stage;
int num_req_per_lower_vm_stage;
- int k;
+ unsigned int k;
for (k = 0; k < NumberOfActivePlanes; ++k) {
if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
int MaximumSwathHeightC[DC__NUM_DPP__MAX];
int MinimumSwathHeightY;
int MinimumSwathHeightC;
- int RoundedUpMaxSwathSizeBytesY;
- int RoundedUpMaxSwathSizeBytesC;
- int RoundedUpMinSwathSizeBytesY;
- int RoundedUpMinSwathSizeBytesC;
- int RoundedUpSwathSizeBytesY;
- int RoundedUpSwathSizeBytesC;
+ unsigned int RoundedUpMaxSwathSizeBytesY;
+ unsigned int RoundedUpMaxSwathSizeBytesC;
+ unsigned int RoundedUpMinSwathSizeBytesY;
+ unsigned int RoundedUpMinSwathSizeBytesC;
+ unsigned int RoundedUpSwathSizeBytesY;
+ unsigned int RoundedUpSwathSizeBytesC;
double SwathWidthSingleDPP[DC__NUM_DPP__MAX];
double SwathWidthSingleDPPChroma[DC__NUM_DPP__MAX];
int k;
int ReorderingBytes)
{
struct vba_vars_st *v = &mode_lib->vba;
- int dummy1, i, j, k;
+ int dummy1, j;
+ unsigned int i, k;
double NormalEfficiency, dummy2, dummy3;
double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];
+ v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]);
}
- for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k)
+ for (k = 0; k < v->NumberOfActivePlanes; ++k)
NoOfDPPState[k] = v->NoOfDPP[i][j][k];
MinimumTWait = CalculateTWait(MaxPrefetchMode, v->FinalDRAMClockChangeLatency, v->UrgLatency[i], v->SREnterPlusExitTime);
}
}
DCFCLKRequiredForPeakBandwidth = 0;
- for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k)
+ for (k = 0; k < v->NumberOfActivePlanes; ++k)
DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k];
MinimumTvmPlus2Tr0 = v->UrgLatency[i]
dcn32_subvp_in_use(dc, context))
vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support;
- if (vlevel < context->bw_ctx.dml.vba.soc.num_states &&
+ if (vlevel < (int)context->bw_ctx.dml.vba.soc.num_states &&
vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported)
break;
unsigned int *num_entries,
struct _vcs_dpi_voltage_scaling_st *entry)
{
- int i = 0;
- int index = 0;
+ unsigned int i = 0;
+ unsigned int index = 0;
dc_assert_fp_enabled();
subvp_pipes[1]->stream->timing.h_total) /
(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000);
- if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us &&
- (vactive2_us - vblank1_us) / 2 > max_microschedule_us)
+ if ((vactive1_us - vblank2_us) / 2 > (int32_t)max_microschedule_us &&
+ (vactive2_us - vblank1_us) / 2 > (int32_t)max_microschedule_us)
return true;
return false;
}
if (subvp_count == 2 && ((min_refresh < 120 && max_refresh < 120) ||
- (min_refresh >= subvp_high_refresh_list.min_refresh &&
- max_refresh <= subvp_high_refresh_list.max_refresh)))
+ (min_refresh >= (uint32_t)subvp_high_refresh_list.min_refresh &&
+ max_refresh <= (uint32_t)subvp_high_refresh_list.max_refresh)))
result = true;
return result;
static void assign_subvp_index(struct dc *dc, struct dc_state *context)
{
- int i;
+ unsigned int i;
int index = 0;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
*/
struct pipe_ctx *pipe;
bool odm;
- int dc_pipe_idx, dml_pipe_idx = 0;
+ unsigned int dc_pipe_idx;
+ int dml_pipe_idx = 0;
bool updated = false;
for (dc_pipe_idx = 0;
*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
/* This may adjust vlevel and maxMpcComb */
- if (*vlevel < context->bw_ctx.dml.soc.num_states) {
+ if (*vlevel < (int)context->bw_ctx.dml.soc.num_states) {
*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
vba->VoltageLevel = *vlevel;
}
/* Check that vlevel requested supports pstate or not
* if not, select the lowest vlevel that supports it
*/
- for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) {
+ for (i = *vlevel; i < (int)context->bw_ctx.dml.soc.num_states; i++) {
if (vba->DRAMClockChangeSupport[i][vba->maxMpcComb] != dm_dram_clock_change_unsupported) {
*vlevel = i;
break;
}
}
- if (*vlevel < context->bw_ctx.dml.soc.num_states
+ if (*vlevel < (int)context->bw_ctx.dml.soc.num_states
&& subvp_validate_static_schedulability(dc, context, *vlevel))
found_supported_config = true;
if (found_supported_config) {
*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
/* This may adjust vlevel and maxMpcComb */
- if (*vlevel < context->bw_ctx.dml.soc.num_states) {
+ if (*vlevel < (int)context->bw_ctx.dml.soc.num_states) {
*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
vba->VoltageLevel = *vlevel;
}
static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
{
- int i;
+ unsigned int i;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
if (!context->res_ctx.pipe_ctx[i].stream)
display_e2e_pipe_params_st *pipes,
int pipe_cnt, int vlevel)
{
- int i, pipe_idx, active_hubp_count = 0;
+ int pipe_idx, active_hubp_count = 0;
+ unsigned int i;
bool usr_retraining_support = false;
bool unbounded_req_enabled = false;
struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
ASSERT(usr_retraining_support);
- if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
- context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
+ if ((unsigned int)context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
+ context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)dc->debug.min_disp_clk_khz;
unbounded_req_enabled = get_unbounded_request_enabled(&context->bw_ctx.dml, pipes, pipe_cnt);
int *split,
bool *merge)
{
- int i, pipe_idx;
+ int pipe_idx;
+ unsigned int i;
bool newly_split[MAX_PIPES] = { false };
struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
context->bw_ctx.dml.validate_max_state = false;
- if (vlevel < context->bw_ctx.dml.soc.num_states) {
+ if (vlevel < (int)context->bw_ctx.dml.soc.num_states) {
memset(split, 0, sizeof(split));
memset(merge, 0, sizeof(merge));
vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
if (vlevel == context->bw_ctx.dml.soc.num_states)
goto validate_fail;
- for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+ for (i = 0, pipe_idx = 0; i < (int)dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
flag_max_mpc_comb != context->bw_ctx.dml.vba.maxMpcComb) {
/* check the context constructed with pipe split flags is still valid*/
bool flags_valid = false;
- for (i = flag_vlevel; i < context->bw_ctx.dml.soc.num_states; i++) {
+ for (i = flag_vlevel; i < (int)context->bw_ctx.dml.soc.num_states; i++) {
if (vba->ModeSupport[i][flag_max_mpc_comb]) {
vba->maxMpcComb = flag_max_mpc_comb;
vba->VoltageLevel = i;
int pipe_cnt,
int vlevel)
{
- int i, pipe_idx, vlevel_temp = 0;
+ int pipe_idx, vlevel_temp = 0;
+ unsigned int i;
double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
double dram_speed_from_validation = context->bw_ctx.dml.vba.DRAMSpeed;
static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries,
unsigned int index)
{
- int i;
+ unsigned int i;
if (*num_entries == 0)
return;
unsigned int end_index = 0;
unsigned int current_bw = 0;
- for (int i = 0; i < (*num_entries - 1); i++) {
+ for (unsigned int i = 0; i < (*num_entries - 1); i++) {
if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) {
current_bw = (unsigned int)table[i].net_bw_in_kbytes_sec;
start_index = i;
}
if (start_index != end_index) {
- for (int j = start_index; j < end_index; j++) {
- for (int k = start_index; k < end_index; k++) {
+ for (unsigned int j = start_index; j < end_index; j++) {
+ for (unsigned int k = start_index; k < end_index; k++) {
if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz)
swap_table_entries(&table[k], &table[k+1]);
}
*/
static void remove_inconsistent_entries(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
{
- for (int i = 0; i < (*num_entries - 1); i++) {
+ for (unsigned int i = 0; i < (*num_entries - 1); i++) {
if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) {
if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) ||
(table[i].fabricclk_mhz > table[i+1].fabricclk_mhz))
static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params,
struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
{
- int i, j;
+ int i;
+ unsigned int j;
struct _vcs_dpi_voltage_scaling_st entry = {0};
struct clk_limit_table_entry max_clk_data = {0};
entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
// Insert all the DCFCLK STAs
- for (i = 0; i < num_dcfclk_stas; i++) {
- entry.dcfclk_mhz = dcfclk_sta_targets[i];
+ for (j = 0; j < num_dcfclk_stas; j++) {
+ entry.dcfclk_mhz = dcfclk_sta_targets[j];
entry.fabricclk_mhz = 0;
entry.dram_speed_mts = 0;
insert_entry_into_table_sorted(table, num_entries, &entry);
// Insert the UCLK DPMS
- for (i = 0; i < num_uclk_dpms; i++) {
+ for (j = 0; j < num_uclk_dpms; j++) {
entry.dcfclk_mhz = 0;
entry.fabricclk_mhz = 0;
- entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
+ entry.dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16;
get_optimal_ntuple(&entry);
entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
// If FCLK is coarse grained, insert individual DPMs.
if (num_fclk_dpms > 2) {
- for (i = 0; i < num_fclk_dpms; i++) {
+ for (j = 0; j < num_fclk_dpms; j++) {
entry.dcfclk_mhz = 0;
- entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
+ entry.fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz;
entry.dram_speed_mts = 0;
get_optimal_ntuple(&entry);
// Remove duplicate states, note duplicate states are always neighbouring since table is sorted.
i = 0;
- while (i < *num_entries - 1) {
+ while (i < ((int)*num_entries - 1)) {
if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz &&
table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz &&
table[i].dram_speed_mts == table[i + 1].dram_speed_mts)
void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
{
struct vba_vars_st *v = &mode_lib->vba;
- int i, j, start_state;
+ int i, start_state;
+ unsigned int j;
unsigned int k, m;
unsigned int MaximumMPCCombine;
unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth;
mode_lib->vba.MPCCombineMethodIncompatible = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsNeededForPStateChangeAndVoltage
&& v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsPossible;
- for (i = start_state; i < v->soc.num_states; i++) {
+ for (i = start_state; i < (int)v->soc.num_states; i++) {
for (j = 0; j < 2; j++) {
mode_lib->vba.TotalNumberOfActiveDPP[i][j] = 0;
mode_lib->vba.TotalAvailablePipesSupport[i][j] = true;
}
}
- for (i = start_state; i < v->soc.num_states; ++i) {
+ for (i = start_state; i < (int)v->soc.num_states; ++i) {
mode_lib->vba.ExceededMultistreamSlots[i] = false;
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == k) {
}
}
- for (i = start_state; i < v->soc.num_states; ++i) {
+ for (i = start_state; i < (int)v->soc.num_states; ++i) {
mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] = false;
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
if (mode_lib->vba.BlendingAndTiming[k] == k
}
}
- for (i = start_state; i < v->soc.num_states; ++i) {
+ for (i = start_state; i < (int)v->soc.num_states; ++i) {
mode_lib->vba.ODMCombine2To1SupportCheckOK[i] = true;
mode_lib->vba.ODMCombine4To1SupportCheckOK[i] = true;
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
}
}
- for (i = start_state; i < v->soc.num_states; i++) {
+ for (i = start_state; i < (int)v->soc.num_states; i++) {
mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = false;
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
if (mode_lib->vba.BlendingAndTiming[k] == k) {
/* Check DSC Unit and Slices Support */
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0;
- for (i = start_state; i < v->soc.num_states; ++i) {
+ for (i = start_state; i < (int)v->soc.num_states; ++i) {
mode_lib->vba.NotEnoughDSCUnits[i] = false;
mode_lib->vba.NotEnoughDSCSlices[i] = false;
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0;
}
/*DSC Delay per state*/
- for (i = start_state; i < v->soc.num_states; ++i) {
+ for (i = start_state; i < (int)v->soc.num_states; ++i) {
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
mode_lib->vba.DSCDelayPerState[i][k] = dml32_DSCDelayRequirement(
mode_lib->vba.RequiresDSC[i][k], mode_lib->vba.ODMCombineEnablePerState[i][k],
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
for (m = 0; m <= mode_lib->vba.NumberOfActiveSurfaces - 1; m++) {
- for (j = 0; j <= mode_lib->vba.NumberOfActiveSurfaces - 1; j++) {
+ for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; j++) {
if (mode_lib->vba.BlendingAndTiming[k] == m &&
mode_lib->vba.RequiresDSC[i][m] == true) {
mode_lib->vba.DSCDelayPerState[i][k] =
mode_lib->vba.SurfaceSizeInMALL,
&mode_lib->vba.ExceededMALLSize);
- for (i = start_state; i < v->soc.num_states; i++) {
+ for (i = start_state; i < (int)v->soc.num_states; i++) {
for (j = 0; j < 2; j++) {
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
mode_lib->vba.swath_width_luma_ub_this_state[k] =
enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[],
enum unbounded_requesting_policy UseUnboundedRequesting)
{
- int k;
+ unsigned int k;
double SwathSizeAllSurfaces = 0;
double SwathSizeAllSurfacesInFetchTimeUs;
double DETSwathLatencyHidingUs;
unsigned int *num_entries,
struct _vcs_dpi_voltage_scaling_st *entry)
{
- int i = 0;
- int index = 0;
+ unsigned int i = 0;
+ unsigned int index = 0;
dc_assert_fp_enabled();
static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries,
unsigned int index)
{
- int i;
+ unsigned int i;
if (*num_entries == 0)
return;
unsigned int end_index = 0;
unsigned int current_bw = 0;
- for (int i = 0; i < (*num_entries - 1); i++) {
+ for (unsigned int i = 0; i + 1 < *num_entries; i++) {
if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) {
current_bw = (unsigned int)table[i].net_bw_in_kbytes_sec;
start_index = i;
end_index = ++i;
- while ((i < (*num_entries - 1)) && (table[i+1].net_bw_in_kbytes_sec == current_bw))
+ while ((i + 1 < *num_entries) && (table[i+1].net_bw_in_kbytes_sec == current_bw))
end_index = ++i;
}
if (start_index != end_index) {
- for (int j = start_index; j < end_index; j++) {
- for (int k = start_index; k < end_index; k++) {
+ for (unsigned int j = start_index; j < end_index; j++) {
+ for (unsigned int k = start_index; k < end_index; k++) {
if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz)
swap_table_entries(&table[k], &table[k+1]);
}
*/
static void remove_inconsistent_entries(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
{
- for (int i = 0; i < (*num_entries - 1); i++) {
+ for (unsigned int i = 0; i + 1 < *num_entries; i++) {
if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) {
if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) ||
(table[i].fabricclk_mhz > table[i+1].fabricclk_mhz))
static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params,
struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
{
- int i, j;
+ int i;
+ unsigned int j, k;
struct _vcs_dpi_voltage_scaling_st entry = {0};
struct clk_limit_table_entry max_clk_data = {0};
entry.phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz;
// Insert all the DCFCLK STAs
- for (i = 0; i < num_dcfclk_stas; i++) {
- entry.dcfclk_mhz = dcfclk_sta_targets[i];
+ for (k = 0; k < num_dcfclk_stas; k++) {
+ entry.dcfclk_mhz = dcfclk_sta_targets[k];
entry.fabricclk_mhz = 0;
entry.dram_speed_mts = 0;
dcn321_insert_entry_into_table_sorted(table, num_entries, &entry);
// Insert the UCLK DPMS
- for (i = 0; i < num_uclk_dpms; i++) {
+ for (k = 0; k < num_uclk_dpms; k++) {
entry.dcfclk_mhz = 0;
entry.fabricclk_mhz = 0;
- entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
+ entry.dram_speed_mts = bw_params->clk_table.entries[k].memclk_mhz * 16;
get_optimal_ntuple(&entry);
entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
// If FCLK is coarse grained, insert individual DPMs.
if (num_fclk_dpms > 2) {
- for (i = 0; i < num_fclk_dpms; i++) {
+ for (k = 0; k < num_fclk_dpms; k++) {
entry.dcfclk_mhz = 0;
- entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
+ entry.fabricclk_mhz = bw_params->clk_table.entries[k].fclk_mhz;
entry.dram_speed_mts = 0;
get_optimal_ntuple(&entry);
// ratios (by derate, are exact).
// Remove states that require higher clocks than are supported
- for (i = *num_entries - 1; i >= 0 ; i--) {
+ for (i = (int)*num_entries - 1; i >= 0 ; i--) {
if (table[i].dcfclk_mhz > max_clk_data.dcfclk_mhz ||
table[i].fabricclk_mhz > max_clk_data.fclk_mhz ||
table[i].dram_speed_mts > max_clk_data.memclk_mhz * 16)
// coarse grained DPMs and remove duplicates.
// Round up UCLKs
- for (i = *num_entries - 1; i >= 0 ; i--) {
+ for (i = (int)*num_entries - 1; i >= 0 ; i--) {
for (j = 0; j < num_uclk_dpms; j++) {
if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) {
table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16;
// If FCLK is coarse grained, round up to next DPMs
if (num_fclk_dpms > 2) {
- for (i = *num_entries - 1; i >= 0 ; i--) {
+ for (i = (int)*num_entries - 1; i >= 0 ; i--) {
for (j = 0; j < num_fclk_dpms; j++) {
if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) {
table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz;
}
// Otherwise, round up to minimum.
else {
- for (i = *num_entries - 1; i >= 0 ; i--) {
+ for (i = (int)*num_entries - 1; i >= 0 ; i--) {
if (table[i].fabricclk_mhz < min_fclk_mhz) {
table[i].fabricclk_mhz = min_fclk_mhz;
}
}
// Round DCFCLKs up to minimum
- for (i = *num_entries - 1; i >= 0 ; i--) {
+ for (i = (int)*num_entries - 1; i >= 0 ; i--) {
if (table[i].dcfclk_mhz < min_dcfclk_mhz) {
table[i].dcfclk_mhz = min_dcfclk_mhz;
}
// Remove duplicate states, note duplicate states are always neighbouring since table is sorted.
i = 0;
- while (i < *num_entries - 1) {
+ while (i < (int)*num_entries - 1) {
if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz &&
table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz &&
table[i].dram_speed_mts == table[i + 1].dram_speed_mts)
}
// Fix up the state indicies
- for (i = *num_entries - 1; i >= 0 ; i--) {
+ for (i = (int)*num_entries - 1; i >= 0 ; i--)
table[i].state = i;
- }
return 0;
}
struct clk_limit_table *clk_table = &bw_params->clk_table;
struct _vcs_dpi_voltage_scaling_st *clock_limits =
dc->scratch.update_bw_bounding_box.clock_limits;
- int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
+ unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
dc_assert_fp_enabled();
display_e2e_pipe_params_st *pipes,
enum dc_validate_mode validate_mode)
{
- int i, pipe_cnt;
+ unsigned int i;
+ int pipe_cnt;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = 0;
bool upscaled = false;
struct clk_limit_table *clk_table = &bw_params->clk_table;
struct _vcs_dpi_voltage_scaling_st *clock_limits =
dc->scratch.update_bw_bounding_box.clock_limits;
- int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
+ unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
dc_assert_fp_enabled();
display_e2e_pipe_params_st *pipes,
enum dc_validate_mode validate_mode)
{
- int i, pipe_cnt;
+ int pipe_cnt;
+ unsigned int i;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = 0;
bool upscaled = false;
static void fetch_socbb_params(struct display_mode_lib *mode_lib)
{
soc_bounding_box_st *soc = &mode_lib->vba.soc;
- int i;
+ unsigned int i;
// SOC Bounding Box Parameters
mode_lib->vba.ReturnBusWidth = soc->return_bus_width_bytes;
*/
static void cache_debug_params(struct display_mode_lib *mode_lib)
{
- int k = 0;
+ unsigned int k = 0;
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++)
mode_lib->vba.CachedActiveDRAMClockChangeLatencyMargin[k] = mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
projects / thirdparty / kernel / linux.git / commitdiff
