clk: renesas: r9a09g047: Add support for DSI clocks and resets

Add definitions for DSI clocks and resets on the R9A09G047 cpg driver
to enable proper initialization and control of the DSI hardware.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://patch.msgid.link/21ac6da825e8fad0b0a9d37d6daa955b0d23ce07.1775636898.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index de0b9c071e0e8eea481446749f686fbc58525204..9e7bb65acea6b924eecb6f45f4b5b65dd0a1bd17 100644 (file)
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -508,6 +508,16 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
                                                BUS_MSTOP(9, BIT(4))),
        DEF_MOD("cru_0_pclk",                   CLK_PLLDTY_DIV16, 13, 4, 6, 20,
                                                BUS_MSTOP(9, BIT(4))),
+       DEF_MOD("dsi_0_pclk",                   CLK_PLLDTY_DIV16, 14, 8, 7, 8,
+                                               BUS_MSTOP(9, BIT(15) | BIT(14))),
+       DEF_MOD("dsi_0_aclk",                   CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9,
+                                               BUS_MSTOP(9, BIT(15) | BIT(14))),
+       DEF_MOD("dsi_0_vclk1",                  CLK_SMUX2_DSI0_CLK, 14, 10, 7, 10,
+                                               BUS_MSTOP(9, BIT(15) | BIT(14))),
+       DEF_MOD("dsi_0_lpclk",                  CLK_PLLETH_LPCLK, 14, 11, 7, 11,
+                                               BUS_MSTOP(9, BIT(15) | BIT(14))),
+       DEF_MOD("dsi_0_pllref_clk",             CLK_QEXTAL, 14, 12, 7, 12,
+                                               BUS_MSTOP(9, BIT(15) | BIT(14))),
        DEF_MOD("ge3d_clk",                     CLK_PLLVDO_GPU, 15, 0, 7, 16,
                                                BUS_MSTOP(3, BIT(4))),
        DEF_MOD("ge3d_axi_clk",                 CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
@@ -516,6 +526,8 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
                                                BUS_MSTOP(3, BIT(4))),
        DEF_MOD("tsu_1_pclk",                   CLK_QEXTAL, 16, 10, 8, 10,
                                                BUS_MSTOP(2, BIT(15))),
+       DEF_MOD("dsi_0_vclk2",                  CLK_SMUX2_DSI1_CLK, 25, 0, 10, 21,
+                                               BUS_MSTOP(9, BIT(15) | BIT(14))),
 };
 
 static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
@@ -591,6 +603,8 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
        DEF_RST(12, 5, 5, 22),          /* CRU_0_PRESETN */
        DEF_RST(12, 6, 5, 23),          /* CRU_0_ARESETN */
        DEF_RST(12, 7, 5, 24),          /* CRU_0_S_RESETN */
+       DEF_RST(13, 7, 6, 8),           /* DSI_0_PRESETN */
+       DEF_RST(13, 8, 6, 9),           /* DSI_0_ARESETN */
        DEF_RST(13, 13, 6, 14),         /* GE3D_RESETN */
        DEF_RST(13, 14, 6, 15),         /* GE3D_AXI_RESETN */
        DEF_RST(13, 15, 6, 16),         /* GE3D_ACE_RESETN */