#define FASTIO_ADDRESS_MASK GENMASK(15, 0)
#define SEQ_PARAM_PROFILE_MASK GENMASK(30, 24)
+#define SEQ_BG_PARAM_REG_DATA 0x3800410
static void _wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason,
const char *func);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_ROT_PARAM, rot_mir_mode);
- vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_BG_PARAM, 0);
+ vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_BG_PARAM,
+ SEQ_BG_PARAM_REG_DATA | p_param->bg_detection);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT,
p_param->conf_win_bot << 16 | p_param->conf_win_top);
case V4L2_CID_MPEG_VIDEO_BITRATE:
inst->bit_rate = ctrl->val;
break;
+ case V4L2_CID_MPEG_VIDEO_BACKGROUND_DETECTION:
+ inst->enc_param.bg_detection = ctrl->val;
+ break;
case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
inst->enc_param.avc_idr_period = ctrl->val;
break;
open_param->wave_param.beta_offset_div2 = input.beta_offset_div2;
open_param->wave_param.decoding_refresh_type = input.decoding_refresh_type;
open_param->wave_param.intra_period = input.intra_period;
+ open_param->wave_param.bg_detection = input.bg_detection;
if (inst->std == W_HEVC_ENC) {
if (input.intra_period == 0) {
open_param->wave_param.decoding_refresh_type = DEC_REFRESH_TYPE_IDR;
v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_AU_DELIMITER,
0, 1, 1, 1);
+ v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
+ V4L2_CID_MPEG_VIDEO_BACKGROUND_DETECTION,
+ 0, 1, 1, 0);
v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
V4L2_CID_HFLIP,
0, 1, 1, 0);
u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */
u32 mb_level_rc_enable: 1; /* enable MB-level rate control */
u32 forced_idr_header_enable: 1; /* enable header encoding before IDR frame */
+ u32 bg_detection: 1; /* enable background detection */
};
struct enc_open_param {