gpio-ranges = <&an7583_pinctrl 0 2 53>;
mdio0_pins: mdio0-pins {
+ mux {
+ function = "mdio";
+ groups = "mdio";
+ };
conf {
pins = "mdio_0";
output-high;
gpio-ranges = <&an7583_pinctrl 0 2 53>;
mdio0_pins: mdio0-pins {
+ mux {
+ function = "mdio";
+ groups = "mdio";
+ };
conf {
pins = "mdio_0";
output-high;
};
};
+ spi_pins: spi-pins {
+ mux {
+ function = "spi";
+ groups = "spi";
+ };
+ };
+
pcie0_rst_pins: pcie0-rst-pins {
conf {
pins = "pcie_reset0";
};
&snfi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_pins>;
status = "okay";
};
gpio-ranges = <&an7583_pinctrl 0 2 53>;
mdio0_pins: mdio0-pins {
+ mux {
+ function = "mdio";
+ groups = "mdio";
+ };
conf {
pins = "mdio_0";
output-high;
};
};
+ spi_pins: spi-pins {
+ mux {
+ function = "spi";
+ groups = "spi";
+ };
+ };
+
pcie0_rst_pins: pcie0-rst-pins {
conf {
pins = "pcie_reset0";
};
};
+&snfi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_pins>;
+};
+
&mdio_0 {
/* Airoha EN8811 2.5Gbps phy */
en8811: ethernet-phy@f {
--- /dev/null
+From 69b8875f6290a1518131e4a1c7fb8b73bc8ea6be Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Date: Thu, 12 Mar 2026 19:13:39 +0100
+Subject: [PATCH] pinctrl: airoha: fix setting of GPIO direction
+
+The GPIO_CTRL registers have two bits per GPIO where the values 0x2 and 0x3
+are reserved. It can happen that both bits in GPIO_CTRL of a GPIO are set when
+the pinctrl driver is probed (e.g. modified by bootloader), but the current
+code just clears the LSB. Thus when switching a certain GPIO to output,
+the updated GPIO_CTRL register can contain the reserved value 0x2 for that
+GPIO. This can result in not driving the GPIO pin at all.
+
+Always clear both bits per GPIO and just set the LSB when the GPIO is configured
+for output.
+
+Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -2627,7 +2627,7 @@ static int airoha_pinmux_set_direction(s
+ {
+ struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+ u32 mask, index;
+- int err, pin;
++ int err, pin, offset;
+
+ pin = airoha_convert_pin_to_reg_offset(pctrl_dev, range, p);
+ if (pin < 0)
+@@ -2642,11 +2642,12 @@ static int airoha_pinmux_set_direction(s
+ return err;
+
+ /* set direction */
+- mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN));
++ offset = 2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN);
++ mask = GENMASK(offset + 1, offset); /* always clear the two bits per GPIO */
+ index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN;
+ return regmap_update_bits(pinctrl->regmap,
+ pinctrl->gpiochip.dir[index], mask,
+- !input ? mask : 0);
++ !input ? BIT(offset) : 0);
+ }
+
+ static const struct pinmux_ops airoha_pmxops = {
--- /dev/null
+From e39b75a93f37d7ea948ddc02749229742b2aa3a0 Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Date: Fri, 3 Jul 2026 21:36:00 +0200
+Subject: [PATCH] pinctrl: airoha: reset SCU IOMUX registers at probe
+
+Add a per-variant table of SCU registers to reset at probe time, so
+bootloader modifications to IOMUX configuration don't silently shadow
+Linux GPIO or func_group writes.
+
+On AN7581 all mux registers use positive polarity (0 = GPIO mode), so
+simply write 0 to each. On AN7583 the high bits 15-26 of REG_GPIO_PON_MODE
+(0x021c) have inverted polarity (1 = GPIO mode), so write
+GPIO_MODE_MASK for those bits, leaving bits 23-24 at 0 so the kernel
+console UART stays active without a pinctrl-0 declaration.
+
+Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 46 +++++++++++++++++++++++++
+ 1 file changed, 46 insertions(+)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -84,6 +84,7 @@
+ #define GPIO_SPI_CS1_MODE_MASK BIT(0)
+
+ #define REG_GPIO_PON_MODE 0x021c
++#define AN7583_GPIO_MODE_MASK (GENMASK(22, 15) | GENMASK(26, 25))
+ #define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
+ #define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
+ #define GPIO_PCIE_RESET2_MASK BIT(12)
+@@ -107,6 +108,9 @@
+ #define REG_FORCE_GPIO_EN 0x0228
+ #define FORCE_GPIO_EN(n) BIT(n)
+
++/* AN7583-only */
++#define REG_FORCE_GPIO32_EN 0x022C
++
+ /* LED MAP */
+ #define REG_LAN_LED0_MAPPING 0x027c
+ #define REG_LAN_LED1_MAPPING 0x0280
+@@ -403,6 +407,11 @@ struct airoha_pinctrl {
+ struct airoha_pinctrl_gpiochip gpiochip;
+ };
+
++struct airoha_pinctrl_hwinit_regs {
++ u32 offset;
++ u32 val;
++};
++
+ struct airoha_pinctrl_match_data {
+ const struct pinctrl_pin_desc *pins;
+ const unsigned int num_pins;
+@@ -411,6 +420,8 @@ struct airoha_pinctrl_match_data {
+ const struct airoha_pinctrl_func *funcs;
+ const unsigned int num_funcs;
+ const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
++ const struct airoha_pinctrl_hwinit_regs *hwinit_regs;
++ const unsigned int num_hwinit_regs;
+ };
+
+ static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
+@@ -2981,6 +2992,23 @@ static const struct pinctrl_ops airoha_p
+ .dt_free_map = pinconf_generic_dt_free_map,
+ };
+
++static const struct airoha_pinctrl_hwinit_regs en7581_hwinit_regs[] = {
++ { REG_GPIO_2ND_I2C_MODE, 0 },
++ { REG_GPIO_SPI_CS1_MODE, 0 },
++ { REG_GPIO_PON_MODE, 0 },
++ { REG_NPU_UART_EN, 0 },
++ { REG_FORCE_GPIO_EN, 0 },
++};
++
++static const struct airoha_pinctrl_hwinit_regs an7583_hwinit_regs[] = {
++ { REG_GPIO_2ND_I2C_MODE, 0 },
++ { REG_GPIO_SPI_CS1_MODE, 0 },
++ { REG_GPIO_PON_MODE, AN7583_GPIO_MODE_MASK },
++ { REG_NPU_UART_EN, 0 },
++ { REG_FORCE_GPIO_EN, 0 },
++ { REG_FORCE_GPIO32_EN, 0 },
++};
++
+ static int airoha_pinctrl_probe(struct platform_device *pdev)
+ {
+ const struct airoha_pinctrl_match_data *data;
+@@ -3005,6 +3033,20 @@ static int airoha_pinctrl_probe(struct p
+
+ pinctrl->chip_scu = map;
+
++ /*
++ * Reset all SCU mux register to reset defaults to undo bootloader modifications.
++ * For AN7583 set default mux config to GPIO to get same behavior as on AN7581.
++ */
++ for (i = 0; i < data->num_hwinit_regs; i++) {
++ err = regmap_write(pinctrl->chip_scu,
++ data->hwinit_regs[i].offset,
++ data->hwinit_regs[i].val);
++ if (err)
++ return dev_err_probe(dev, err,
++ "Failed to reset SCU IOMUX register 0x%x\n",
++ data->hwinit_regs[i].offset);
++ }
++
+ /* Init pinctrl desc struct */
+ pinctrl->desc.name = KBUILD_MODNAME;
+ pinctrl->desc.owner = THIS_MODULE;
+@@ -3067,6 +3109,8 @@ static const struct airoha_pinctrl_match
+ .num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
+ .funcs = en7581_pinctrl_funcs,
+ .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
++ .hwinit_regs = en7581_hwinit_regs,
++ .num_hwinit_regs = ARRAY_SIZE(en7581_hwinit_regs),
+ .confs_info = {
+ [AIROHA_PINCTRL_CONFS_PULLUP] = {
+ .confs = en7581_pinctrl_pullup_conf,
+@@ -3098,6 +3142,8 @@ static const struct airoha_pinctrl_match
+ .num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
+ .funcs = an7583_pinctrl_funcs,
+ .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
++ .hwinit_regs = an7583_hwinit_regs,
++ .num_hwinit_regs = ARRAY_SIZE(an7583_hwinit_regs),
+ .confs_info = {
+ [AIROHA_PINCTRL_CONFS_PULLUP] = {
+ .confs = an7583_pinctrl_pullup_conf,
--- /dev/null
+From 4d69bddfbe9d8cf41e7d370472b247b6409b2735 Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Date: Fri, 3 Jul 2026 22:20:28 +0200
+Subject: [PATCH] pinctrl: airoha: fix I2C1 pin mux config for AN7581
+
+The pin mux on GPIOs 1 and 2 on AN7581 supports I2C in master and
+slave mode. When selecting I2C the according bits (bit 13 for master,
+bit 11 for slave) must be set in REG_GPIO_2ND_I2C_MODE.
+
+Fix the i2c1 pin group to set bits 0 and 13 to set I2C1 master mode by
+default.
+
+Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -1142,8 +1142,8 @@ static const struct airoha_pinctrl_func_
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+- GPIO_2ND_I2C_MODE_MASK,
+- GPIO_2ND_I2C_MODE_MASK
++ GPIO_2ND_I2C_MODE_MASK | GPIO_I2C_MASTER_MODE_MODE,
++ GPIO_2ND_I2C_MODE_MASK | GPIO_I2C_MASTER_MODE_MODE,
+ },
+ .regmap_size = 1,
+ },
--- /dev/null
+From 2d3405f300d79e12dbd5e259f660016f5f985b35 Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Date: Fri, 3 Jul 2026 22:20:28 +0200
+Subject: [PATCH] pinctrl: airoha: fix I2C pin mux config for AN7583
+
+On AN7583 both I2C busses have a pin sharing with GPIO. Also the pin mux
+setting is done in REG_GPIO_PON_MODE instead of REG_GPIO_2ND_I2C_MODE.
+
+Add dedicated I2C pin groups and function groups for AN7583. The new
+groups must support i2c0 and i2c1.
+
+Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 29 ++++++++++++++++++++++++-
+ 1 file changed, 28 insertions(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -85,6 +85,10 @@
+
+ #define REG_GPIO_PON_MODE 0x021c
+ #define AN7583_GPIO_MODE_MASK (GENMASK(22, 15) | GENMASK(26, 25))
++#define AN7583_I2C1_SDA_GPIO_MODE_MASK BIT(18)
++#define AN7583_I2C1_SCL_GPIO_MODE_MASK BIT(17)
++#define AN7583_I2C0_SDA_GPIO_MODE_MASK BIT(16)
++#define AN7583_I2C0_SCL_GPIO_MODE_MASK BIT(15)
+ #define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
+ #define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
+ #define GPIO_PCIE_RESET2_MASK BIT(12)
+@@ -880,6 +884,7 @@ static const char *const uart_groups[] =
+ "hsuart_cts_rts", "uart4",
+ "uart5" };
+ static const char *const i2c_groups[] = { "i2c1" };
++static const char *const an7583_i2c_groups[] = { "i2c0", "i2c1" };
+ static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
+ static const char *const pcm_groups[] = { "pcm1", "pcm2" };
+ static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
+@@ -1149,6 +1154,28 @@ static const struct airoha_pinctrl_func_
+ },
+ };
+
++static const struct airoha_pinctrl_func_group an7583_i2c_func_group[] = {
++ {
++ .name = "i2c0",
++ .regmap[0] = {
++ AIROHA_FUNC_MUX,
++ REG_GPIO_PON_MODE,
++ AN7583_I2C0_SCL_GPIO_MODE_MASK | AN7583_I2C0_SDA_GPIO_MODE_MASK,
++ 0
++ },
++ .regmap_size = 1,
++ }, {
++ .name = "i2c1",
++ .regmap[0] = {
++ AIROHA_FUNC_MUX,
++ REG_GPIO_PON_MODE,
++ AN7583_I2C1_SCL_GPIO_MODE_MASK | AN7583_I2C1_SDA_GPIO_MODE_MASK,
++ 0
++ },
++ .regmap_size = 1,
++ },
++};
++
+ static const struct airoha_pinctrl_func_group jtag_func_group[] = {
+ {
+ .name = "jtag_udi",
+@@ -1872,7 +1899,7 @@ static const struct airoha_pinctrl_func
+ PINCTRL_FUNC_DESC("sipo", sipo),
+ PINCTRL_FUNC_DESC("mdio", an7583_mdio),
+ PINCTRL_FUNC_DESC("uart", uart),
+- PINCTRL_FUNC_DESC("i2c", i2c),
++ PINCTRL_FUNC_DESC("i2c", an7583_i2c),
+ PINCTRL_FUNC_DESC("jtag", jtag),
+ PINCTRL_FUNC_DESC("pcm", pcm),
+ PINCTRL_FUNC_DESC("spi", spi),
--- /dev/null
+From 614954a5df7505f68727ea920bce362c58a1fbdb Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Date: Sat, 4 Jul 2026 00:14:10 +0200
+Subject: [PATCH] pinctrl: airoha: fix AN7583 MDIO pin mux config
+
+an7583_mdio_pins[] pointed at pins 43/44 (I2C1_SDA/I2C1_SCL) instead of
+pins 53/54 (MDC_0/MDIO_0 respectively GPIO 51/52). Also the MDIO function
+group wrote GPIO_SGMII_MDIO_MODE_MASK (bit 13 of REG_GPIO_PON_MODE, an
+unrelated SGMII MDIO mode) and GPIO_MDC_IO_MASTER_MODE_MODE (BIT(14),
+an EN7581 specific bit from REG_GPIO_2ND_I2C_MODE).
+
+Fix both by setting an7583_mdio_pins[] to { 53, 54 } and rewriting the
+function group to clear AN7583_MDC_0_GPIO_MODE_MASK (bit 25) and
+AN7583_MDIO_0_GPIO_MODE_MASK (bit 26) of REG_GPIO_PON_MODE. Both bits
+are cleared by the hwinit at probe.
+
+Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 16 ++++++----------
+ 1 file changed, 6 insertions(+), 10 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -85,6 +85,8 @@
+
+ #define REG_GPIO_PON_MODE 0x021c
+ #define AN7583_GPIO_MODE_MASK (GENMASK(22, 15) | GENMASK(26, 25))
++#define AN7583_MDC_0_GPIO_MODE_MASK BIT(25)
++#define AN7583_MDIO_0_GPIO_MODE_MASK BIT(26)
+ #define AN7583_I2C1_SDA_GPIO_MODE_MASK BIT(18)
+ #define AN7583_I2C1_SCL_GPIO_MODE_MASK BIT(17)
+ #define AN7583_I2C0_SDA_GPIO_MODE_MASK BIT(16)
+@@ -720,7 +722,7 @@ static const int an7583_pon_tod_1pps_pin
+ static const int an7583_gsw_tod_1pps_pins[] = { 32 };
+ static const int an7583_sipo_pins[] = { 34, 35 };
+ static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
+-static const int an7583_mdio_pins[] = { 43, 44 };
++static const int an7583_mdio_pins[] = { 53, 54 };
+ static const int an7583_uart2_pins[] = { 34, 35 };
+ static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
+ static const int an7583_hsuart_pins[] = { 30, 31 };
+@@ -1069,16 +1071,10 @@ static const struct airoha_pinctrl_func_
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+- GPIO_SGMII_MDIO_MODE_MASK,
+- GPIO_SGMII_MDIO_MODE_MASK
++ AN7583_MDC_0_GPIO_MODE_MASK | AN7583_MDIO_0_GPIO_MODE_MASK,
++ 0
+ },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_SPI_CS1_MODE,
+- GPIO_MDC_IO_MASTER_MODE_MODE,
+- GPIO_MDC_IO_MASTER_MODE_MODE
+- },
+- .regmap_size = 2,
++ .regmap_size = 1,
+ },
+ };
+
--- /dev/null
+From c4ecab08e53151f7bc39ca4604124acf85cd7595 Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Date: Sat, 4 Jul 2026 00:52:18 +0200
+Subject: [PATCH] pinctrl: airoha: fix AN7583 SPI pin mux config
+
+The AN7583 "spi" group pointed at pins 28-31 (2nd SPI extension bus)
+instead of pins 45-48 (1st SPI boot-flash bus). Additionally the
+"spi" func_group entry was missing, so any board DTS referencing
+function = "spi"; groups = "spi" would fail with -EINVAL.
+
+On AN7583, the 1st SPI pins 45-48 are muxed with GPIOs via
+REG_GPIO_PON_MODE bits 19-22 (inverted polarity, hw_init puts them
+in GPIO mode by default), so the func_group entry must clear those
+bits to enable the SPI function. EN7581 SPI pins are dedicated-
+function pads with no GPIO alternative and need no register write.
+
+Fix this by correcting an7583_spi_pins[], adding
+AN7583_SPI_GPIO_MODE_MASK (GENMASK(22,19)), and splitting
+spi_func_group[] into shared (EN7581) and AN7583-specific variants.
+The new an7583_spi_func_group[] adds the "spi" entry that clears
+bits 19-22 of REG_GPIO_PON_MODE.
+
+Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 37 +++++++++++++++++++++++--
+ 1 file changed, 35 insertions(+), 2 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -87,6 +87,7 @@
+ #define AN7583_GPIO_MODE_MASK (GENMASK(22, 15) | GENMASK(26, 25))
+ #define AN7583_MDC_0_GPIO_MODE_MASK BIT(25)
+ #define AN7583_MDIO_0_GPIO_MODE_MASK BIT(26)
++#define AN7583_SPI_GPIO_MODE_MASK GENMASK(22, 19)
+ #define AN7583_I2C1_SDA_GPIO_MODE_MASK BIT(18)
+ #define AN7583_I2C1_SCL_GPIO_MODE_MASK BIT(17)
+ #define AN7583_I2C0_SDA_GPIO_MODE_MASK BIT(16)
+@@ -736,7 +737,7 @@ static const int an7583_jtag_udi_pins[]
+ static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
+ static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
+ static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
+-static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
++static const int an7583_spi_pins[] = { 45, 46, 47, 48 };
+ static const int an7583_spi_quad_pins[] = { 25, 26 };
+ static const int an7583_spi_cs1_pins[] = { 27 };
+ static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
+@@ -890,6 +891,7 @@ static const char *const an7583_i2c_grou
+ static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
+ static const char *const pcm_groups[] = { "pcm1", "pcm2" };
+ static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
++static const char *const an7583_spi_groups[] = { "spi", "spi_quad", "spi_cs1" };
+ static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
+ "pcm_spi_rst", "pcm_spi_cs1",
+ "pcm_spi_cs2_p156",
+@@ -1265,6 +1267,37 @@ static const struct airoha_pinctrl_func_
+ },
+ };
+
++static const struct airoha_pinctrl_func_group an7583_spi_func_group[] = {
++ {
++ .name = "spi",
++ .regmap[0] = {
++ AIROHA_FUNC_MUX,
++ REG_GPIO_PON_MODE,
++ AN7583_SPI_GPIO_MODE_MASK,
++ 0
++ },
++ .regmap_size = 1,
++ }, {
++ .name = "spi_quad",
++ .regmap[0] = {
++ AIROHA_FUNC_MUX,
++ REG_GPIO_SPI_CS1_MODE,
++ GPIO_SPI_QUAD_MODE_MASK,
++ GPIO_SPI_QUAD_MODE_MASK
++ },
++ .regmap_size = 1,
++ }, {
++ .name = "spi_cs1",
++ .regmap[0] = {
++ AIROHA_FUNC_MUX,
++ REG_GPIO_SPI_CS1_MODE,
++ GPIO_SPI_CS1_MODE_MASK,
++ GPIO_SPI_CS1_MODE_MASK
++ },
++ .regmap_size = 1,
++ },
++};
++
+ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
+ {
+ .name = "pcm_spi",
+@@ -1898,7 +1931,7 @@ static const struct airoha_pinctrl_func
+ PINCTRL_FUNC_DESC("i2c", an7583_i2c),
+ PINCTRL_FUNC_DESC("jtag", jtag),
+ PINCTRL_FUNC_DESC("pcm", pcm),
+- PINCTRL_FUNC_DESC("spi", spi),
++ PINCTRL_FUNC_DESC("spi", an7583_spi),
+ PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
+ PINCTRL_FUNC_DESC("emmc", emmc),
+ PINCTRL_FUNC_DESC("pnand", pnand),
--- /dev/null
+From 90b810be65087288a2262ec6428ad64a8bdcf77c Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Date: Sat, 4 Jul 2026 01:23:28 +0200
+Subject: [PATCH] pinctrl: airoha: remove nonexistent AN7583 PCM SPI groups
+
+The an7583_pcm_spi_groups[] references "pcm_spi_int", "pcm_spi_cs2",
+"pcm_spi_cs3" and "pcm_spi_cs4". None of these groups are defined in
+an7583_pinctrl_groups[], they exist only on AN7581. The PCM SPI interface
+on AN7583 only supports CLK, CS0, CS1, MOSI, MISO and RESET. Any board
+DTS referencing these groups would silently get -EINVAL from
+airoha_pinmux_set_mux().
+
+Remove the nonexistent group names from an7583_pcm_spi_groups[] and
+their matching regmap entries from an7583_pcm_spi_func_group[].
+
+Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 36 -------------------------
+ 1 file changed, 36 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -1385,15 +1385,6 @@ static const struct airoha_pinctrl_func_
+ },
+ .regmap_size = 1,
+ }, {
+- .name = "pcm_spi_int",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_SPI_CS1_MODE,
+- GPIO_PCM_INT_MODE_MASK,
+- GPIO_PCM_INT_MODE_MASK
+- },
+- .regmap_size = 1,
+- }, {
+ .name = "pcm_spi_rst",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+@@ -1411,33 +1402,6 @@ static const struct airoha_pinctrl_func_
+ GPIO_PCM_SPI_CS1_MODE_MASK
+ },
+ .regmap_size = 1,
+- }, {
+- .name = "pcm_spi_cs2",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_SPI_CS1_MODE,
+- AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
+- AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "pcm_spi_cs3",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_SPI_CS1_MODE,
+- GPIO_PCM_SPI_CS3_MODE_MASK,
+- GPIO_PCM_SPI_CS3_MODE_MASK
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "pcm_spi_cs4",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_SPI_CS1_MODE,
+- GPIO_PCM_SPI_CS4_MODE_MASK,
+- GPIO_PCM_SPI_CS4_MODE_MASK
+- },
+- .regmap_size = 1,
+ },
+ };
+
projects / thirdparty / openwrt.git / commitdiff
