From: Tommaso Merciai Date: Wed, 8 Apr 2026 10:36:49 +0000 (+0200) Subject: clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_DIV7 clocks X-Git-Url: http://git.ipfire.org/gitweb/index.cgi?a=commitdiff_plain;h=0e1597c688880c2b916401c88afcd476a4e912a2;p=thirdparty%2Fkernel%2Flinux.git clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_DIV7 clocks Add the CLK_PLLDSI0_DIV7 and CLK_PLLDSI1_DIV7 fixed-factor clocks to the r9a09g047 SoC clock driver. These clocks are required to enable LVDS0 and LVDS1 output support. Reviewed-by: Geert Uytterhoeven Signed-off-by: Tommaso Merciai Link: https://patch.msgid.link/e50c1721e1dc160e8b4518e8c5172f10cba4b58b.1775636898.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c index 87d5924f7e79..fd9b49c39dac 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -69,6 +69,8 @@ enum clk_ids { CLK_PLLVDO_GPU, CLK_PLLETH_DIV4_LPCLK, CLK_PLLETH_LPCLK, + CLK_PLLDSI0_DIV7, + CLK_PLLDSI1_DIV7, /* Module Clocks */ MOD_CLK_BASE, @@ -196,6 +198,9 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { DEF_CSDIV(".plleth_lpclk", CLK_PLLETH_LPCLK, CLK_PLLETH_DIV4_LPCLK, CSDIV0_DIVCTL2, dtable_16_128), + DEF_FIXED(".plldsi0_div7", CLK_PLLDSI0_DIV7, CLK_PLLDSI0, 1, 7), + DEF_FIXED(".plldsi1_div7", CLK_PLLDSI1_DIV7, CLK_PLLDSI1, 1, 7), + /* Core Clocks */ DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1), DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55,