From: Cosmin Tanislav Date: Fri, 10 Apr 2026 16:35:21 +0000 (+0300) Subject: clk: renesas: r9a09g077: Add MTU3 module clock X-Git-Url: http://git.ipfire.org/gitweb/index.cgi?a=commitdiff_plain;h=38acb2a1a0ced15f61342347bba8aa57775802ea;p=thirdparty%2Fkernel%2Flinux.git clk: renesas: r9a09g077: Add MTU3 module clock The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a MTU3 block connected to the PCLKH and with a module clock controlled by register 0x308, bit 0. Add support for the module clock. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260410163530.383818-2-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c index 93b15e06a19b..f777601a23b9 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -257,6 +257,7 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = { DEF_MOD("spi0", 104, CLK_SPI0ASYNC), DEF_MOD("spi1", 105, CLK_SPI1ASYNC), DEF_MOD("spi2", 106, CLK_SPI2ASYNC), + DEF_MOD("mtu3", 200, R9A09G077_CLK_PCLKH), DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH), DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH), DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM),