From: Ankit Nautiyal Date: Tue, 28 Apr 2026 07:44:49 +0000 (+0530) Subject: drm/dp: Rename and relocate AS SDP payload field masks X-Git-Url: http://git.ipfire.org/gitweb/index.cgi?a=commitdiff_plain;h=59e5e15fef9c3045b16f73419d68b8f6da2c3bc9;p=thirdparty%2Fkernel%2Flinux.git drm/dp: Rename and relocate AS SDP payload field masks The AS SDP payload field masks were misnamed and placed under the DPRX feature enumeration list. These are not DPRX capability bits, but are payload field masks for the Adaptive Sync SDP. Relocate both masks next to the AS SDP definitions. Update users to the corrected names. No functional change. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä Signed-off-by: Suraj Kandpal Link: https://patch.msgid.link/20260428074457.3566918-2-ankit.k.nautiyal@intel.com --- diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 86123614b7ba..ed17f6beae9a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5374,8 +5374,8 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, if ((sdp->sdp_header.HB3 & 0x3F) != 9) return -EINVAL; - as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH; - as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE; + as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK; + as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK; as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1]; as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3); as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false; diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 8b15d3eeb716..4ea3b5b08a12 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -1204,8 +1204,6 @@ #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */ # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED (1 << 0) -# define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE GENMASK(1, 0) -# define DP_ADAPTIVE_SYNC_SDP_LENGTH GENMASK(5, 0) # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1) # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED (1 << 4) @@ -1870,4 +1868,7 @@ enum operation_mode { DP_AS_SDP_FAVT_TRR_REACHED = 0x03 }; +#define DP_AS_SDP_OPERATION_MODE_MASK GENMASK(1, 0) +#define DP_AS_SDP_LENGTH_MASK GENMASK(5, 0) + #endif /* _DRM_DP_H_ */