From: Alexander Stein Date: Thu, 26 Mar 2026 13:02:22 +0000 (+0100) Subject: arm64: dts: imx8qm-tqma8qm-mba8x: Disable Cortex-A72 cluster X-Git-Url: http://git.ipfire.org/gitweb/index.cgi?a=commitdiff_plain;h=5d20f1ccb3393a2ccb3f3505891066ddff39167a;p=thirdparty%2Flinux.git arm64: dts: imx8qm-tqma8qm-mba8x: Disable Cortex-A72 cluster Due to missing workaround for "ERR050104: Arm/A53: Cache coherency issue" disable the whole Cortex-A72 cluster. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- diff --git a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts index bf972010a88e..ab3b244b684f 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts @@ -298,45 +298,6 @@ }; }; }; - - cpu1-thermal { - trips { - soc_active1_0: trip-active0 { - temperature = <40000>; - hysteresis = <5000>; - type = "active"; - }; - - soc_active1_1: trip-active1 { - temperature = <48000>; - hysteresis = <3000>; - type = "active"; - }; - - soc_active1_2: trip-active2 { - temperature = <60000>; - hysteresis = <10000>; - type = "active"; - }; - }; - - cooling-maps { - map1 { - trip = <&soc_active1_0>; - cooling-device = <&fan0 1 1>; - }; - - map2 { - trip = <&soc_active1_1>; - cooling-device = <&fan0 2 2>; - }; - - map3 { - trip = <&soc_active1_2>; - cooling-device = <&fan0 3 3>; - }; - }; - }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi index d94605c99991..f0e398eb2aad 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi @@ -15,6 +15,13 @@ model = "TQ-Systems i.MX8QM TQMa8QM"; compatible = "tq,imx8qm-tqma8qm", "fsl,imx8qm"; + /* Due to missing workaround for ERR050104 */ + cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + /delete-node/ cpu@101; + }; + memory@80000000 { device_type = "memory"; /* @@ -174,6 +181,8 @@ }; &thermal_zones { + /delete-node/ cpu1-thermal; + pmic0-thermal { polling-delay-passive = <250>; polling-delay = <2000>; @@ -199,9 +208,7 @@ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; };