From: Harshal Dev Date: Tue, 5 May 2026 07:40:04 +0000 (+0530) Subject: arm64: dts: qcom: glymur: Add crypto engine and BAM X-Git-Url: http://git.ipfire.org/gitweb/index.cgi?a=commitdiff_plain;h=93e08fdc55f227847dc9b249fd5eb43403e7e8b9;p=thirdparty%2Fkernel%2Flinux.git arm64: dts: qcom: glymur: Add crypto engine and BAM On almost all Qualcomm platforms, including Glymur, there is a Crypto engine IP block to which the CPU can off-load cryptographic computations for achieving acceleration. The engine is also DMA capable due to the presence of an associated Bus Access Manager (BAM) module. Describe the Crypto engine and its BAM. Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260505-glymur_crypto_enablement-v2-2-bf115aeb1459@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 0c5cb8532b202..c8f7eab296066 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3675,6 +3675,32 @@ status = "disabled"; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + interrupts = ; + #dma-cells = <1>; + iommus = <&apps_smmu 0x80 0x0>, + <&apps_smmu 0x81 0x0>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <20>; + qcom,num-ees = <4>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,glymur-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", + "tx"; + iommus = <&apps_smmu 0x80 0x0>, + <&apps_smmu 0x81 0x0>; + interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>;