From: Dillon Varone Date: Thu, 9 Apr 2026 20:45:51 +0000 (-0400) Subject: drm/amd/display: Add minimum vfp requirement X-Git-Tag: v7.2-rc1~141^2~24^2~148 X-Git-Url: http://git.ipfire.org/gitweb/index.cgi?a=commitdiff_plain;h=a7a2cbc6b08654ffa6f1e15fa6ff0e058d4fcbd9;p=thirdparty%2Flinux.git drm/amd/display: Add minimum vfp requirement [WHY&HOW] Vertical front porch (vfp) must be greater than 1, and must be patched if it isn't. This must be done pre-DML so the DLG programming remains consistent with the OTG programming. Reviewed-by: Austin Zheng Signed-off-by: Dillon Varone Signed-off-by: Chenyu Chen Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c index 476030193f149..9031fd582ec78 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c @@ -90,6 +90,8 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf struct pipe_ctx *pipe_ctx, struct dml2_context *dml_ctx) { + const unsigned int min_v_front_porch = (stream->timing.flags.INTERLACE != 0) ? 2 : 1; + unsigned int hblank_start, vblank_start; uint64_t min_hardware_refresh_in_uhz; uint32_t pix_clk_100hz; @@ -97,7 +99,8 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding; timing->v_active = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; timing->h_front_porch = stream->timing.h_front_porch; - timing->v_front_porch = stream->timing.v_front_porch; + timing->v_front_porch = stream->timing.v_front_porch > min_v_front_porch ? + stream->timing.v_front_porch : min_v_front_porch; timing->pixel_clock_khz = stream->timing.pix_clk_100hz / 10; if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0) timing->pixel_clock_khz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz / 10; @@ -116,7 +119,7 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf if (hblank_start < stream->timing.h_addressable) timing->h_blank_end = 0; - vblank_start = stream->timing.v_total - stream->timing.v_front_porch; + vblank_start = timing->v_total - timing->v_front_porch; timing->v_blank_end = vblank_start - stream->timing.v_addressable - stream->timing.v_border_top - stream->timing.v_border_bottom;