From: Nazim Amirul Date: Thu, 7 May 2026 03:32:02 +0000 (-0700) Subject: arm64: dts: socfpga: agilex5: Fix phy-mode to rgmii as HW provides clock delay X-Git-Url: http://git.ipfire.org/gitweb/index.cgi?a=commitdiff_plain;h=c5637e5ceb4b4bbe80fceec77f5e663c4ff7b508;p=thirdparty%2Flinux.git arm64: dts: socfpga: agilex5: Fix phy-mode to rgmii as HW provides clock delay The Agilex5 SoC provides RGMII TX/RX clock delay compensation through its integrated I/O hardware. Using phy-mode = "rgmii-id" instructs the MAC driver to additionally insert internal TX/RX delays, resulting in double delay being applied and causing Ethernet link timing issues. Change phy-mode to "rgmii" across all Agilex5 device tree files to reflect that the clock delay is already handled by the hardware and no additional software-inserted delay is required. Add an inline comment to satisfy checkpatch and document the hardware-provided delay. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen --- diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts index dae0db9f8819..57d3c5807c65 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -44,7 +44,7 @@ &gmac2 { status = "okay"; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */ phy-handle = <&emac2_phy0>; max-frame-size = <9000>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts index 86137380df04..82cd4115746e 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts @@ -43,7 +43,7 @@ &gmac2 { status = "okay"; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */ phy-handle = <&emac2_phy0>; max-frame-size = <9000>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts index e728cedb4cbd..4d32b6928ce1 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts @@ -46,7 +46,7 @@ &gmac2 { status = "okay"; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */ phy-handle = <&emac2_phy0>; max-frame-size = <9000>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts index 21faa47681fa..81443096cf99 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts @@ -41,7 +41,7 @@ &gmac0 { status = "okay"; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */ phy-handle = <&emac0_phy0>; max-frame-size = <9000>;