From: Val Packett Date: Wed, 4 Mar 2026 19:06:23 +0000 (-0300) Subject: phy: qcom: qmp-combo: Move pipe_clk on/off to common X-Git-Url: http://git.ipfire.org/gitweb/index.cgi?a=commitdiff_plain;h=f546912bcac6463a22c5825e27a7952f8b48c887;p=thirdparty%2Fkernel%2Flinux.git phy: qcom: qmp-combo: Move pipe_clk on/off to common Keep the USB pipe clock working when the phy is in DP-only mode, because the dwc controller still needs it for USB 2.0 over the same Type-C port. Tested with the BenQ RD280UA monitor which has a downstream-facing port for data passthrough that's manually switchable between USB 2 and 3, corresponding to 4-lane and 2-lane DP respectively. Note: the suspend/resume callbacks were already gating the enable/disable of this clock only on init_count and not usb_init_count! Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Signed-off-by: Val Packett Link: https://patch.msgid.link/20260304190827.176988-1-val@packett.cool Signed-off-by: Vinod Koul --- diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 93f1aa10d4008..cdcfad2e86b1d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -3691,6 +3691,13 @@ static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) if (ret) goto err_assert_reset; + /* In DP-only mode, the pipe clk is still required for USB2 */ + ret = clk_prepare_enable(qmp->pipe_clk); + if (ret) { + dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); + goto err_disable_clocks; + } + qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); /* override hardware control for reset of qmp phy */ @@ -3749,6 +3756,8 @@ static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) return 0; +err_disable_clocks: + clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); err_assert_reset: reset_control_bulk_assert(cfg->num_resets, qmp->resets); err_disable_regulators: @@ -3768,6 +3777,7 @@ static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force) reset_control_bulk_assert(cfg->num_resets, qmp->resets); + clk_disable_unprepare(qmp->pipe_clk); clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); regulator_bulk_disable(cfg->num_vregs, qmp->vregs); @@ -3871,12 +3881,6 @@ static int qmp_combo_usb_power_on(struct phy *phy) qmp_configure(qmp->dev, serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); - ret = clk_prepare_enable(qmp->pipe_clk); - if (ret) { - dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); - return ret; - } - /* Tx, Rx, and PCS configurations */ qmp_configure_lane(qmp->dev, tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); qmp_configure_lane(qmp->dev, tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); @@ -3922,8 +3926,6 @@ static int qmp_combo_usb_power_off(struct phy *phy) struct qmp_combo *qmp = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qmp->cfg; - clk_disable_unprepare(qmp->pipe_clk); - /* PHY reset */ qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);