From: CL Wang <cl634@andestech.com>
Date: Thu, 15 Jan 2026 08:14:42 +0000 (+0800)
Subject: dt-bindings: watchdog: Add support for Andes ATCWDT200
X-Git-Url: http://git.ipfire.org/gitweb/index.cgi?a=commitdiff_plain;h=fec053e452a5e859cf6e8aa2c9d44d78fed60034;p=thirdparty%2Fkernel%2Flinux.git

dt-bindings: watchdog: Add support for Andes ATCWDT200

Add the devicetree binding documentation for the Andes ATCWDT200
watchdog timer.

ATCWDT200 is the IP name, which is embedded in AndesCore-based
platforms or SoCs such as AE350 and Qilai.

Signed-off-by: CL Wang <cl634@andestech.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20260115081444.2452357-2-cl634@andestech.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---

diff --git a/Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml b/Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml
new file mode 100644
index 0000000000000..f1107c5527887
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/andestech,ae350-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes ATCWDT200 Watchdog Timer
+
+maintainers:
+  - CL Wang <cl634@andestech.com>
+
+allOf:
+  - $ref: watchdog.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - andestech,qilai-wdt
+          - const: andestech,ae350-wdt
+      - const: andestech,ae350-wdt
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  andestech,clock-source:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1]
+    description: |
+      Select the clock source for the watchdog timer.
+      0 - External clock
+      1 - P clock
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - andestech,clock-source
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    watchdog@f0500000 {
+        compatible = "andestech,ae350-wdt";
+        reg = <0xf0500000 0x20>;
+        clocks = <&clk_wdt>;
+        andestech,clock-source = <0>;
+    };