Sparsh Kumar [Wed, 25 Feb 2026 13:24:19 +0000 (18:54 +0530)]
board: ti: am62x: tifs-rm-cfg: Add the missing tifs-rm-cfg:
The am62x platform was originally introduced without a
tifs-rm-cfg.yaml file. Add the tifs-rm-cfg to bring am62x
in line with other am62 family of devices (am62px and am62a)
which all include this file.
This complements the rm-cfg update earlier in this series.
Sparsh Kumar [Wed, 25 Feb 2026 13:24:17 +0000 (18:54 +0530)]
board: ti: rm-cfg: Update rm-cfg to reflect new resource reservation
With the latest v11.02.09 TIFS firmware, an additional
virtual interrupt and event is reserved for MCU cores
to DM usage on am62x, am62ax and am62px devices.
Update the rm-cfg to reflect this new reservation.
Updates the polarities for the GPIOs on the sc594
EZKIT carrier board for the newest revision, Rev D.
The new carrier board revision has different polarities
for some GPIOs. This patch updates the sc594 entries
to match the sc598 entries that were updated in a previous
commit, as both SOMs can utilize the EZKIT.
Note that these updates are for the EZKIT carrier
board used by both sc598 and sc594 SOMs, not the SOMs themselves.
Fixes: be79378 ("board: adi: Add support for SC594") Signed-off-by: Caleb Ethridge <caleb.ethridge@analog.com> Reviewed-by: Greg Malysa <malysagreg@gmail.com>
Anton Moryakov [Thu, 26 Feb 2026 21:27:28 +0000 (00:27 +0300)]
linux_compat: fix NULL pointer dereference in get_mem()
Add NULL check after memalign() call in get_mem() to prevent
potential NULL pointer dereference (CWE-476).
The function memalign() can return NULL on allocation failure.
Dereferencing the returned pointer without checking for NULL
may cause a crash in low-memory conditions.
Changes:
- Add NULL check after memalign() allocation
- Return NULL on failure, consistent with function semantics
This fixes the static analyzer warning:
linux_compat.c:34: dereference of memalign return value without NULL check
Reported-by: static analyzer Svace Signed-off-by: Anton Moryakov <ant.v.moryakov@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Nikita Shubin [Thu, 26 Feb 2026 16:39:10 +0000 (19:39 +0300)]
serial: ns16550: Fix return-type warning
Fix compiler warning:
drivers/serial/ns16550.c: In function ‘serial_in_dynamic’:
drivers/serial/ns16550.c:153:1: warning: control reaches end
of non-void function [-Wreturn-type]
153 | }
| ^
Anurag Dutta [Thu, 26 Feb 2026 09:05:24 +0000 (14:35 +0530)]
arm: dts: k3-j721s2*: Enable OSPI1 with 32-bit address mappings for R5 SPL
The R5 SPL requires 32-bit address mappings for OSPI1(QSPI) access.
Override the OSPI1 node with appropriate 32-bit register ranges to
enable proper address translation on the 32-bit R5 core, while
preserving 64-bit mappings for A72 cores. While at it, remove the
disabled status override for ospi1 node to support booting from
qspi.
Michal Simek [Thu, 26 Feb 2026 09:27:16 +0000 (10:27 +0100)]
spl: Remake SPL elf from bin
On Xilinx MB-V there is a need to use ELF file for SPL which is placed
in BRAM (Block RAM) because tools for placing code to bitstream requires to
use ELF. That's why introduce SPL_REMAKE_ELF similar to REMAKE_ELF option
as was originally done by commit f4dc714aaa2d ("arm64: Turn u-boot.bin back
into an ELF file after relocate-rela").
There is already generic and simple linker script (arch/u-boot-elf.lds)
which can be also used without any modification.
Signed-off-by: Michal Simek <michal.simek@amd.com>
spl: spi: fix loss of spl_load() error on soft reset
When CONFIG_SPI_FLASH_SOFT_RESET is enabled, spi_nor_remove() is called
after spl_load() to switch the flash back to legacy SPI mode. However,
the return value of spi_nor_remove() unconditionally overwrites the
return value of spl_load(), discarding any load error.
Fix this by preserving the spl_load() error and only propagating the
spi_nor_remove() error as a fallback. Also log a message when
spi_nor_remove() fails, since in the case where spl_load() already
failed its error would otherwise be silently discarded.
Marek Vasut [Tue, 27 Jan 2026 23:48:40 +0000 (00:48 +0100)]
lmb: Reinstate access to memory above ram_top
Revert commit eb052cbb896f ("lmb: add and reserve memory above ram_top")
and commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from
same bank"). These are based on incorrect premise of the first commit, that
"U-Boot does not use memory above ram_top". While U-Boot itself indeed does
not and should not use memory above ram_top, user can perfectly well use
that memory from the U-Boot shell, for example to load content in there.
Currently, attempt to use that memory to load large image using TFTP ends
with "TFTP error: trying to overwrite reserved memory...". With this change
in place, the memory can be used again.
Fixes: eb052cbb896f ("lmb: add and reserve memory above ram_top") Fixes: 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank") Reported-by: Yuya Hamamachi <yuya.hamamachi.sx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
net:
- Move network PHY under NETDEVICES
- s/DM_CLK/CLK/ in HIFEMAC_{ETH,MDIO}
- Add support for Airoha AN8811HB PHY
- airoha: PCS and MDIO support for Airoha AN7581 SoC
net-lwip:
- Fix issue when TFTP blocksize is >8192
- Adjust PBUF_POOL_SIZE/IP_REASS_MAX_PBUFS for better performance and
resource usage.
- Enable mii command for NET_LWIP
Tom Rini [Tue, 10 Mar 2026 16:26:14 +0000 (10:26 -0600)]
net: Move network PHY under NETDEVICES
A number of network PHY drivers have Kconfig dependencies on various
network drivers under NETDEVICES. This is in addition to logical
dependencies of network PHYs needing network drivers. Resolve the
Kconfig problems by moving the network PHY lines to be after the network
devices, within the overall NETDEVICES guard.
Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Jerome Forissier <jerome.forissier@arm.com>
Pranav Tilak [Tue, 10 Mar 2026 12:58:25 +0000 (18:28 +0530)]
net: lwip: scale buffer pool size with TFTP block size
TFTP transfers fail when tftpblocksize is set to 8192 or larger due to
insufficient buffer resources for IP fragment reassembly.
Calculate PBUF_POOL_SIZE and IP_REASS_MAX_PBUFS dynamically based on
CONFIG_TFTP_BLOCKSIZE using IP fragmentation boundaries (1480 usable
bytes per fragment at 1500 MTU). The pool size includes headroom for
TX, ARP, and protocol overhead, while ensuring PBUF_POOL_SIZE remains
greater than IP_REASS_MAX_PBUFS as required by lwIP.
Jonas Karlman [Mon, 9 Mar 2026 21:06:39 +0000 (21:06 +0000)]
net: lwip: Fix PBUF_POOL_BUFSIZE when PROT_TCP_LWIP is disabled
The PBUF_POOL_BUFSIZE ends up being only 592 bytes, instead of 1514,
when PROT_TCP_LWIP Kconfig option is disabled. This results in a full
Ethernet frame requiring three PBUFs instead of just one.
This happens because the PBUF_POOL_BUFSIZE constant depends on the value
of a TCP_MSS constant, something that defaults to 536 when PROT_TCP_LWIP
is disabled.
Tommy Shih [Thu, 26 Feb 2026 08:52:00 +0000 (16:52 +0800)]
net: phy: air_en8811: add support for Airoha AN8811HB PHY
Add support for the Airoha AN8811HB 2.5 Gigabit PHY to the existing
en8811h driver. This PHY supports 10/100/1000/2500 Mbps speeds.
Update the driver to recognize the AN8811HB PHY ID and handle its
specific firmware loading requirements. The firmware loading mechanism
remains consistent with the existing implementation.
This driver is based on:
- Linux upstream PHY subsystem (v7.0-rc1)
- air_an8811hb v0.0.4 out-of-tree uboot driver written by
"Lucien.Jheng <lucien.jheng@airoha.com>"
Tom Rini [Thu, 12 Mar 2026 22:10:46 +0000 (16:10 -0600)]
Merge tag 'rpi-2026.04-rc4' of https://source.denx.de/u-boot/custodians/u-boot-raspberrypi
Updates for RPi for 2026.04-rc4:
- board/raspberrypi: add bcm2712d0-rpi-5-b for Raspberry Pi 5
- board/raspberrypi: add multi-FDT support
- rpi: pass the Video Core logs DT parameter through
- pinctrl: bcm283x: Fix GPIO pull state register values for BCM2711
Current code just bind mt7531 mdio with it's driver, so mdio device may
not be probed and hense not usable.
This patch:
* Forces probing of mt7531 mdio for GDM1 port
* Renames the mt7531 mdio bus interface to 'mt7531-mdio'. We may have
multiple available MDIO, so the name 'mdio' isn't descriptive enough.
* Sets mdio bus for the GDM port device
net: airoha: fill in support for PCS/PHY in Airoha Ethernet driver
Add required changes to call PCS function to configure the Serdes Port.
The Ethernet driver is adapted following Upstream Kernel node structure.
Function calling order is the same of Phylink upstream kernel.
With the PCS support, also add support for attaching PHY. With
"in-band-status" set in DT for the managed property, a rudimental
support for SFP module is present.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
net: airoha-pcs: an7581: sync with linux code a bit
based on linux kernel patches from
https://github.com/Ansuel/openwrt/commits/openwrt-24.10-airoha-an7581-stable/
created by Christian Marangi <ansuelsmth@gmail.com>
Tom Rini [Thu, 12 Mar 2026 13:45:29 +0000 (07:45 -0600)]
Merge tag 'mediatek-for-next-2026-03-11' of https://source.denx.de/u-boot/custodians/u-boot-mediatek into next
A fix:
* Fixing compiling MT8195 due to some independent changes that were applied
around the same time as MT8195 support was merged. (CI would not have caught
this since we didn't have a defconfig until now).
And few small features:
* New defconfig for MT8395/Genio 1200 EVK.
* pinctrl support for MT8189-compatible SoCs.
Filip Kokosiński [Mon, 16 Feb 2026 18:44:52 +0000 (19:44 +0100)]
board/raspberrypi: add bcm2712d0-rpi-5-b for Raspberry Pi 5
This commit adds an FDT entry for the d0 stepping of the BCM2712 SoC.
This entry is used by the v1.1 revision of the board
(revision & 0x0f == 1).
Signed-off-by: Filip Kokosiński <filip.kokosinski@gmail.com> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
Filip Kokosiński [Mon, 16 Feb 2026 18:44:51 +0000 (19:44 +0100)]
board/raspberrypi: add multi-FDT support
This patch adds support for multiple FDT files per board model. This is
done by adding the FDTFILES macro, which initializes two rpi_model
struct members: fdtfiles and fdtcount.
The new-style revision codes designate LSB bits as board revision; this
value is used to choose between provided FDTs. The first element of the
fdtfiles list is used should no revision match.
Signed-off-by: Filip Kokosiński <filip.kokosinski@gmail.com> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
net: airoha: add initial support for multiple GDM port
Rework the driver to support multiple GDM port. The driver is split to
main driver as a MISC driver with forced probe (by using the
DM_FLAG_PROBE_AFTER_BIND) and each GDM port register a ETH driver.
This permit a 1:1 implementation with the linux kernel driver and permit
to use the same exact DT nodes.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
common: spl: spl_dfu.c: Fix warning associated with PCI subclass_code
The subclass_code member of the pci_ep_header structure is a 1-byte
field. The macro PCI_CLASS_MEMORY_RAM is a concetation of baseclass_code
and subclass_code as follows:
PCI_BASE_CLASS_MEMORY: 0x05
Subclass Code for RAM: 0x00
PCI_CLASS_MEMORY_RAM: 0x0500
Hence, instead of extracting it via an implicity type conversion from int
to u8 which throws a warning, explicitly mask the bits to extract the
subclass_code.
Alexey Charkov [Tue, 20 Jan 2026 18:09:02 +0000 (22:09 +0400)]
spl: Make UFS available for SPL builds
Add minimal infrastructure to build SPL images with support for UFS
storage devices. This also pulls in SCSI support and charset functions,
which are dependencies of the UFS code.
With this, only a fixed offset is supported for loading the next image,
which should be specified in CONFIG_SPL_UFS_RAW_U_BOOT_SECTOR as the
number of 4096-byte sectors into the UFS block device.
David Lechner [Mon, 9 Feb 2026 23:34:18 +0000 (17:34 -0600)]
pinctl: mediatek: increase max number of base addresses
Increase the maximum number of base addresses that can be handled by the
mediatek pinctrl driver from 10 to 15. This is needed for the MT8189
which has 15 base addresses.
Shiva Tripathi [Wed, 25 Feb 2026 11:24:38 +0000 (16:54 +0530)]
arm: k3: Kconfig: Enable fTPM and RPMB support
Enable firmware TPM (fTPM) support via OP-TEE for K3 platforms with
MMC hardware. This provides TPM 2.0 functionality through
Microsoft's fTPM Trusted Application running in OP-TEE secure world,
using eMMC RPMB as persistent storage.
fTPM support in U-Boot provides the foundation for measured boot
and disk encryption use cases.
The ARM64 condition ensures these apply only to A53/A72 cores and the
MMC condition ensures fTPM is enabled only on platforms with eMMC
hardware support.
Signed-off-by: Shiva Tripathi <s-tripathi1@ti.com> Acked-by: Andrew Davis <afd@ti.com>
Add checkkconfigsymbols.py from Linux 7.0-rc1 (unchanged since v6.2).
This tool allows to identify the usage of symbols that are not defined
in Kconfig.
We removed configuration symbol CONFIG_DM_PCI with
commit 3232bdf0b30b ("pci: Drop DM_PCI").
Don't select it for TARGET_POMELO.
Fixes: b9d0f00a9d3f ("arm: add initial support for the Phytium Pomelo Board") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Tom Rini <trini@konsulko.com>
The disk_read() and disk_write() functions of the FAT driver use the
blk_dread() and blk_dwrite() respectively. The blk_* APIs read and write
to the devices in terms of the device block size. However, the FAT
driver reads in terms of the device block size (from fat_set_blk_dev and
read_bootsectandvi) and sector size in the rest of the places.
This causes buffer overflows or partial reads when the FAT sector size
is not equal to device block size. Fix this by using blk_dread in
fat_set_blk_dev and read_bootsectandvi instead of disk_read. And update
disk_read/disk_write to handle FAT sector size and block size mismatch.
CI test results
---------------
https://github.com/u-boot/u-boot/pull/871
All checks have passed
93 successful checks
No conflicts with base branch
Code size change info
---------------------
arm: (for 1/1 boards) all +32.0 text +32.0
qemu_arm : all +32 text +32
u-boot: add: 0/0, grow: 2/0 bytes: 24/0 (24)
function old new delta
read_bootsectandvi 420 432 +12
fat_set_blk_dev 204 216 +12
aarch64: (for 1/1 boards) all +12.0 rodata -8.0 text +20.0
qemu_arm64 : all +12 rodata -8 text +20
u-boot: add: 0/0, grow: 2/0 bytes: 20/0 (20)
function old new delta
read_bootsectandvi 408 420 +12
fat_set_blk_dev 204 212 +8
The disk_read() and disk_write() functions of the FAT driver use the
blk_dread() and blk_dwrite() respectively. The blk_* APIs read and write
to the devices in terms of the device block size. However, the FAT
driver reads in terms of the device block size (from fat_set_blk_dev and
read_bootsectandvi) and sector size in the rest of the places.
This causes buffer overflows or partial reads when the FAT sector size
is not equal to device block size. Fix this by using blk_dread in
fat_set_blk_dev and read_bootsectandvi instead of disk_read. And update
disk_read/disk_write to handle FAT sector size and block size mismatch.
Jonas Karlman [Wed, 4 Feb 2026 21:29:20 +0000 (21:29 +0000)]
rockchip: Reduce size of ramboot usb472 payload
Booting into SPL using ramboot can take several seconds on some SoCs due
to the large size of the usb472 payload sent over USB to BootROM.
A large chunk of the usb472 payload, around 1-2 MiB, is padding used to
avoid overlapping when loading e.g. TF-A to 0x40000.
BootROM is likely wasting unnecessary time crc16 validating the padding
of the payload.
Place the FIT payload directly after SPL and memmove it to the expected
memory location, SPL_LOAD_FIT_ADDRESS, to avoid excessive padding and
help speed up ramboot.
Binman symbols are used to get the position and size of the FIT payload
that is initially loaded into DRAM by the BootROM.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Tue, 3 Feb 2026 09:58:06 +0000 (10:58 +0100)]
rockchip: rk3588: include all addressable DRAM in memory map
The ATAGS set by Rockchip DDR init blob[1] specify DRAM banks above the
first addressable 4GiB which we haven't done in the mem_map for RK3588
yet.
For 4GiB DRAM, the 256MiB missing from the first addressable 4GiB (due
to MMIO) are accessible at the end of the 8GiB address space. For 8GiB,
4-8GiB address space is used for the additional 4GiB and the missing
256MiB are at the end of 12GiB address space. For 12, 4-12GiB and the
missing 256MiB at the end of 20GiB address space. For 16GiB, 4-~16GiB
with two holes (reasons unknown) around 16GiB and the missing 256MiB is
at the end of 20GiB address space. For 32GiB, 4-16~GiB with two holes
and then 16GiB to 32GiB address space (so likely missing 256MiB from
MMIO address space).
(cherry picked from commit 516951213a82094f7f49f149cbf3c66dfb14c65d) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 31 Jan 2026 23:38:13 +0000 (23:38 +0000)]
rockchip: mkimage: Re-sort the spl_infos list alphanumerically
The first RK35xx SoC was initially appended to the end of the otherwise
alphanumerically sorted spl_infos list, possible because it was using a
new header structure.
Re-sort the spl_infos list to keep it alphanumerically ordered based
on imagename.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 31 Jan 2026 23:38:12 +0000 (23:38 +0000)]
rockchip: spl: Add common handling of USB bootsource_id 0x81
Multiple newer Rockchip SoCs report 0x81 instead of 0xa when booting
from USB, i.e. on RK3576, RK3528, RK3506 and RV1106.
Move the bootsource_id 0x81 handling currently only used for RK3528 to
the common read_brom_bootsource_id() to reduce the need to override this
function when support for newer SoCs is introduced.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Fri, 16 Jan 2026 22:12:20 +0000 (23:12 +0100)]
ARM: dts: rockchip: move edp assigned-clocks to edp node on rk3288
The rk3288 power-controller node contains an assigned-clocks property
that conflicts with the bindings. From the git history it shows that they
wanted to assign the rk3288 EDP_24M clock input centrally before an edp
node was available. Move the edp assigned-clocks property to the edp node
to reduce dtbs_check output.
Johan Jonker [Fri, 16 Jan 2026 22:12:08 +0000 (23:12 +0100)]
ARM: dts: rockchip: Add spi_flash label to rk3288-veyron
The u-boot,spl-boot-order property requires a label at a boot
device node. In order to migrate to OF_UPSTREAM more easier
add a spi_flash label to the rk3288-veyron.dtsi file.
Quentin Schulz [Fri, 9 Jan 2026 11:17:48 +0000 (12:17 +0100)]
rockchip: tiger-rk3588: disable HS400
Tiger suffers from eMMC signal integrity issues which means we can only
run it at HS200 max.
The Device Tree has these properties removed since v6.18 (commit baa18d577cd4 ("arm64: dts: rockchip: disable HS400 on RK3588 Tiger")),
which has now merged in U-Boot.
Since the controller side doesn't support HS400 anymore, let's not
confuse users as to why HS400 is enabled in the config but not working
as we know it cannot work (and won't be used anyway since the controller
doesn't advertise support for it in the Device Tree).
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Thu, 8 Jan 2026 13:32:29 +0000 (13:32 +0000)]
rockchip: rk3576: Allow pmu sram access for non-secure masters
The firewall block access to pmu sram for non-secure masters by default
after reset (0xffffbfff).
Change the pmu lookup configuration to match the default lookup config
for ddr and system sram (0xffff3fff) to allow loading TF-A using DMA.
Mainline TF-A will re-configure the firewall to use an even less
restrictive lookup (0xbffe3ff0), so this change is not expected to have
any real security implication.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: Alexey Charkov <alchark@gmail.com> # UFS Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 7 Jan 2026 23:07:41 +0000 (23:07 +0000)]
rockchip: rk3588s-rock-5c: Add support for ROCK 5C Lite variant
Add Kconfig option OF_SYSTEM_SETUP=y to support booting ROCK 5C Lite
boards with a RK3582 SoC. CPU and GPU cores are failed based on ip-state
and policy.
Tested on a ROCK 5C Lite v1.1:
cpu-code: 35 82
ip-state: 00 80 00 (otp)
ip-state: c0 9e 04 (policy)
remove cpu-map cluster2
fail gpu
fail rkvdec1
fail rkvenc1
fail cpu cpu@600
fail cpu cpu@700
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Simon Glass [Fri, 6 Mar 2026 01:20:09 +0000 (18:20 -0700)]
boot: Add fit_config_get_hash_list() to build signed node list
The hashed-nodes property in a FIT signature node lists which FDT paths
are included in the signature hash. It is intended as a hint so should
not be used for verification.
Add a function to build the node list from scratch by iterating the
configuration's image references. Skip properties known not to be image
references. For each image, collect the path plus all hash and cipher
subnodes.
Use the new function in fit_config_check_sig() instead of reading
'hashed-nodes'.
Update the test_vboot kernel@ test case: fit_check_sign now catches the
attack at signature-verification time (the @-suffixed node is hashed
instead of the real one, causing a mismatch) rather than at
fit_check_format() time.
Update the docs to cover this. The FIT spec can be updated separately.
Signed-off-by: Simon Glass <simon.glass@canonical.com> Closes: https://lore.kernel.org/u-boot/20260302220937.3682128-1-trini@konsulko.com/ Reported-by: Apple Security Engineering and Architecture (SEAR) Tested-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 9 Mar 2026 15:12:43 +0000 (09:12 -0600)]
Merge patch series "64-bit PCIe for AM64, AM69, J7200, J722S and J784S4"
Siddharth Vadapalli <s-vadapalli@ti.com> says:
Since Linux device-tree has switched to 64-bit Address space for the
PCIe Controllers on TI SoCs, currently, U-Boot needs to support the
same. This series adds support for 64-bit addressing for PCIe along with
enabling Root-Complex mode of operation for AM69 and J784S4 SoCs.
configs: j722s_evm_a53_defconfig: enable 64-bit addressing for PCIe
The PCIe0 instance of PCIe on the J722S SoC uses the 4 GB Address Window
starting from 0x6_0000_0000 to map System Addresses to PCIe Bus Addresses.
Hence, enable CONFIG_SYS_PCI_64BIT.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Fixes: 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
configs: j7200_evm_a72_defconfig: enable 64-bit addressing for PCIe
The PCIe1 instance of PCIe on the J7200 SoC uses the 4 GB Address Window
starting from 0x41_0000_0000 to map System Addresses to PCIe Bus Addresses.
Hence, enable CONFIG_SYS_PCI_64BIT.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Fixes: 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
projects / thirdparty / u-boot.git / log
