Tom Rini [Tue, 12 Jun 2012 21:54:32 +0000 (14:54 -0700)]
am335x_evm: Update config for common usage
- Add default commands
- Add HUSH parser
- Make environment, malloc areas larger
- Add ATAGS and OF_LIBFDT
- Add defaults to boot ramdisk and MMC, use uEnv.txt
This patch adds board-specific initialization for CPSW on
TI AM335X based boards. Tested on BeagleBone.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
[Ilya: split board-specific part into separate patch] Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Read the on-board EEPROM during startup to detect the version
of the board we are running on (as for now only BeagleBone vs
EVM detection is supported).
CPSW is an on-chip ethernet switch that is found on various SoCs from Texas
Instruments. This patch adds a simple driver (based on the Linux driver) for
this hardware module.
This patch also adds support to clean and flush dcache during packet send
and receive.
Changes by Sandhya: Added support to clean and flush dcache during packet
send/receive and added timeouts.
Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
[Ilya: Cleaned cache handling, some style cleanup, some small
fixes, use of internal RAM for descriptors] Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Albert ARIBAUD [Fri, 20 Jul 2012 06:51:26 +0000 (08:51 +0200)]
Revert "arm: armv7: add compile option -mno-unaligned-access if available"
This reverts commit 5347560f5427bcdd48a563b62180481606ac8044,
which was applied only to get release 2012.07 functional on as
many ARM targets as possible despite mis-aligned accesses.
omap2plus_defconfig now has built-in compile support for EXT4 enabled
by default now. So, we can use EXT4 as the default root file system
type for MMC.
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
An OMAP specific serial driver was merged on the Linux kenel a long
time ago. So, it makes sense to default the console name to OMAP
ttyO instead of the generic ttyS naming.
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Lad, Prabhakar [Sun, 24 Jun 2012 21:35:21 +0000 (21:35 +0000)]
da850/omap-l138: Fix NAND flash timings
Though Commit id a3f88293ddd13facd734769c1664d35ab4ed681f (da850evm:
setup the NAND flash timings) has configured the AEMIF timings, they
are not exactly in sync with the timings used in Linux. Linux is
configuring the timing register as 0x08222204, where as currently it
configured to 0x00100084 in U-Boot. This issue was found out when
support for NAND SPL is added in U-Boot. Without this patch U-Boot
does not come up with SPL.
Lad, Prabhakar [Sun, 24 Jun 2012 21:35:20 +0000 (21:35 +0000)]
da850/omap-l138: Add support to read u-boot image from MMC/SD
DA850/OMAP-L138 does not support strict MMC/SD boot mode. SPL will
be in SPI flash and U-Boot image will be in MMC/SD card. SPL will
do the low level initialization and then loads the u-boot image
from MMC/SD card.
Define CONFIG_SPL_MMC_LOAD macro in the DA850/OMAP-L138
configuration file to enable this feature.
da850/omap-l138: Make MMC and NOR support mutually exclusive
On Logic PD Rev.3 DA850/OMAP-L138 EVM, NOR and MMC/SD cannot
work together. This patch enables the MMC/SD support only
when NOR support is disabled. NOR Flash identification works
even without this patch, but erase and write will have issues.
da850/omap-l138: modifications for Logic PD Rev.3 AM18xx EVM
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
MMC and NOR to work on DA850/OMAP-L138 Rev.3 EVM. When
GP0[11] is low, the SD0 interface will not work, but NOR
flash will. When GP0[11] is high, SD0 will work but NOR
flash will not.
Steve Sakoman [Mon, 4 Jun 2012 05:35:34 +0000 (05:35 +0000)]
omap: am33xx: enable gpio support
This patch uses the code in omap-common to support gpio modules 1-3
on am33xx based boards.
It adds base address and register definitions, enables clocks to the
modules, and enables building the common gpio code for CONFIG_AM33XX
as well as CONFIG_OMAP
Sughosh Ganu [Wed, 13 Jun 2012 08:39:06 +0000 (08:39 +0000)]
hawkboard/omapl-138: Add support for generating ais image for hawkboard
Parameters used for configuring certain SoC peripherals are parsed
from the cfg file and appended as part of the ais image's header. The
u-boot-spl.ais generated is flashed separately to the nand, so do not
delete the file after generation of u-boot.ais.
Ilya Yanok [Fri, 8 Jun 2012 03:12:09 +0000 (03:12 +0000)]
omap24xx_i2c: add 2-byte address support
Various devices like EEPROMs require 2-byte address support to
be properly accessed. This patch adds this support for OMAP2/3/4
I2C controller driver.
I've tested it with EEPROM (16 bit address) and TPS65217 chip
(8 bit address) on TI Beaglebone board.
Unfortunately I don't have access to any compatible hardware
with 16bit data register so I can't test if those #ifdef
clauses really work.
CC: Tom Rini <trini@ti.com> Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Stefan Roese [Thu, 16 Aug 2012 17:55:41 +0000 (17:55 +0000)]
Consolidate bootcount code into drivers/bootcount
This patch moves all bootcount implementations into a common
directory: drivers/bootcount. The generic bootcount driver
is now usable not only by powerpc platforms, but others as well.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Christian Riesch <christian.riesch@omicron.at> Cc: Manfred Rudigier <manfred.rudigier@omicron.at> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de> Tested-by: Valentin Longchamp <valentin.longchamp@keymile.com> Tested-by: Christian Riesch <christian.riesch@omicron.at> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
Wolfgang Denk [Sat, 1 Sep 2012 10:22:31 +0000 (12:22 +0200)]
Merge branch 'sf' of git://git.denx.de/u-boot-blackfin
* 'sf' of git://git.denx.de/u-boot-blackfin:
sf: spansion: Add support for S25FL256S
sf: winbond: fix page_size
sf: stmicro: add support for N25Q128A
sf: stmicro: add support N25Q128 parts
sf: stmicro: support JEDEC standard two-byte signature
sf: winbond: add W25Q32
cmd_spi: remove superfluous semicolon
Scott Wood [Wed, 8 Aug 2012 15:06:18 +0000 (15:06 +0000)]
powerpc/mpc85xx/p1_p2_rdb: add all LAWs during SPL
LAW init is skipped in the SPL payload because it's assumed that the SPL
has taken care of it -- so make sure the SPL loads all the LAWs as is
done on other boards.
Scott Wood [Mon, 20 Aug 2012 13:16:30 +0000 (13:16 +0000)]
powerpc/p1_p2_rdb_pc: print -PC suffix in board name
Currently the -PC variants of the P1/P2 RDB boards do not print it on boot --
e.g. a P2020RDB-PC will claim to be a plain P2020RDB. Besides being incorrect,
this can confuse a user into building U-Boot for P2020RDB rather than P2020RDB-PC,
resulting in a board that does not boot.
P1024RDB and P1025RDB are not included, as these boards apparently do not
have -PC as part of their name, even though they are supported by p1_p2_rdb_pc.
The P2020RDB variant covered by this is apparently P2020RDB-PCA rather
than P2020RDB-PC.
Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 17 Aug 2012 09:00:54 +0000 (09:00 +0000)]
powerpc/mpc8xxx: Move HWCONFIG_BUFFER_SIZE into config.h
Before proper environment is setup, we extract hwconfig and put it into a
buffer with size HWCONFIG_BUFFER_SIZE. We need to enlarge the buffer to
accommodate longer string. Since this macro is used in multiple files, we
move it into arch/powerpc/include/asm/config.h.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 17 Aug 2012 08:22:36 +0000 (08:22 +0000)]
powerpc/mpc85xx: Skip zero values for DDR debug registers
Some debug registers have non-zero default out of reset. If software is
not setting debug registers, skip writing to them to avoid unnecessary
overriding.
Also add debug messages for workarounds and debug registers.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 17 Aug 2012 08:20:26 +0000 (08:20 +0000)]
powerpc/mpc8xxx: fix core id for multicore booting
For the cores with multiple threads, we need to figure out which physical
core a thread belongs. To match the core ids, update PIR registers and
spin tables.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
Kumar Gala [Fri, 17 Aug 2012 08:20:25 +0000 (08:20 +0000)]
Added new ext fields to IFC
In case more than 32 bit address is used, the EXT bit should be set.
Need to fix up address map for IFC #CS for 4, also need to move # of IFC
banks into config_mpc85xx.h
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Kumar Gala [Fri, 17 Aug 2012 08:20:24 +0000 (08:20 +0000)]
Add IFC offset for DPAA/Corenet platforms
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 17 Aug 2012 08:20:22 +0000 (08:20 +0000)]
powerpc/mpc8xxx: use topology registers to calculate number of cores
We have actual topology infomation to find out exactly which core is present.
Calculate the number of cores if not specified.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 17 Aug 2012 08:20:21 +0000 (08:20 +0000)]
powerpc/mpc8xxx: Add immap for topology and rcpm registers
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/mpc85xx:Enable debugger support to missed e500v2 SoC
Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
restrictions on external debugging (JTAG). Need to define define
CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be
used during boot to work around the limitations.
Enable missed e500v2 SoC i.e. MPC8536, MPC8544, MPC8548 and MPC8572 for
debug support.
Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Cc: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Erratum A004510 says that under certain load conditions, modified
cache lines can be discarded, causing data corruption.
To work around this, several CCSR and DCSR register updates need to be
made in a careful manner, so that there is no other transaction in
corenet when the update is made.
The update is made from a locked cacheline, with a delay before to flush
any previous activity, and a delay after to flush the CCSR/DCSR update.
We can't use a readback because that would be another corenet
transaction, which is not allowed.
We lock the subsequent cacheline to prevent it from being fetched while
we're executing the previous cacheline. It is filled with nops so that a
branch doesn't cause us to fetch another cacheline.
Ordinarily we are running in a cache-inhibited mapping at this point, so
we temporarily change that. We make it guarded so that we should never
see a speculative load, and we never do an explicit load. Thus, only the
I-cache should ever fill from this mapping, and we flush/unlock it
afterward. Thus we should avoid problems from any potential cache
aliasing between inhibited and non-inhibited mappings.
NOTE that if PAMU is used with this patch, it will need to use a
dedicated LAW as described in the erratum. This is the responsibility
of the OS that sets up PAMU.
Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Scott Wood [Tue, 14 Aug 2012 10:14:51 +0000 (10:14 +0000)]
powerpc/fsl-corenet: remove dead variant symbols
These are not supported as individual build targets, but instead
are supported by another target.
The dead p4040 defines in particular had bitrotted significantly.
Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
Timur Tabi [Tue, 14 Aug 2012 06:47:25 +0000 (06:47 +0000)]
powerpc/85xx: get rid of enum board_slots in P4080 MDIO driver
enum board_slots contained six values, where SLOT1 == 1, SLOT2 == 2, and
so on. This is pointless, so remove it. Also move the lane_to_slot[]
array to the top of the file so that it can be used by other functions.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Timur Tabi [Tue, 14 Aug 2012 06:47:23 +0000 (06:47 +0000)]
powerpc/85xx: introduce function serdes_device_from_fm_port()
In order to figure out which SerDes lane a given Fman port is connected
to, we need a function that maps the fm_port namespace to the srds_prtcl
namespace.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Timur Tabi [Tue, 14 Aug 2012 06:47:22 +0000 (06:47 +0000)]
fm-eth: add function fm_info_get_phy_address()
Function fm_info_get_phy_address() returns the PHY address for a given
Fman port. This is handy when the MDIO code needs to fixup the Ethernet
nodes in the device tree to point to PHY nodes for a specific PHY address.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Paul Gortmaker [Mon, 13 Aug 2012 13:48:57 +0000 (13:48 +0000)]
mpc85xx: use LCRR_DBYP define instead of raw constant
Using the raw value of 0x80000000 directly in the code can
lead to "count the zeros" bugs like that fixed in commit 718e9d13b98 ("MPC85xxCDS: Fix missing LCRR_DBYP bits for
66-133MHz LBC")
Change all existing raw values to use the symbolic value of
LCRR_DBYP instead.
Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Let's use the more appropriate udelay for the nand_spl. While we
can't make use of u-boot's full udelay we can atl east use a for
loop that won't get optimized away .Since we have the bus clock
we can use the timebase to calculate wall time.
Looked at reusing the u-boot udelay functions but it pulls in a lot
of code and would require quite a bit of work to keep us within the
very small space constrains we currently have
Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
p1014rdb: set ddr bus width properly depending on SVR
Currently, for NAND boot for the P1010/4RDB we hard code the DDR
configuration. We can still dynamically set the DDR bus width in
the nand spl so the P1010/4RDB boards can boot from the same
u-boot image
Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Shaohui Xie [Fri, 10 Aug 2012 02:49:35 +0000 (02:49 +0000)]
powerpc/CoreNet: add tool to support pbl image build.
Provides a tool to build boot Image for PBL(Pre boot loader) which is
used on Freescale CoreNet SoCs, PBL can be used to load some instructions
and/or data for pre-initialization. The default output image is u-boot.pbl,
for more details please refer to doc/README.pblimage.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Thu, 9 Aug 2012 05:10:03 +0000 (05:10 +0000)]
powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using "saveenv" or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
"xxxx_SRIO_PCIE_BOOT", and the image builded with
"xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Thu, 9 Aug 2012 05:10:02 +0000 (05:10 +0000)]
powerpc/corenet_ds: Master module for boot from PCIE
For the powerpc processors with PCIE interface, boot location can be
configured from one PCIE interface by RCW. The processor booting from PCIE
can do without flash for u-boot image. The image can be fetched from another
processor's memory space by PCIE link connected between them.
The processor booting from PCIE is slave, the processor booting from normal
flash memory space is master, and it can help slave to boot from master's
memory space.
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the master module, need to finish these processes:
1. Initialize the PCIE port and address space.
2. Set inbound PCIE windows covered slave's u-boot image stored in
master's NOR flash.
3. Set outbound windows in order to configure slave's registers
for the core's releasing.
4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2"
or "PCIE3" using the following command:
setenv bootmaster PCIE1
saveenv
Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Thu, 9 Aug 2012 05:10:01 +0000 (05:10 +0000)]
powerpc/corenet_ds: Update README and README.srio-pcie-boot-corenet
Added descriptions about boot from PCIE in the files README and
doc/README.srio-pcie-boot-corenet, and changed the name of the
doc/README.srio-boot-corenet to doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Thu, 9 Aug 2012 05:10:00 +0000 (05:10 +0000)]
powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro
When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.
This has the following advantages:
1. No longer need to rebuild an image when change the SRIO port for
boot from SRIO, just rewrite the new RCW with selected port,
then the code will get the port information by reading new RCW.
2. It will be easier to support other boot location options, for
example, boot from PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Thu, 9 Aug 2012 05:09:59 +0000 (05:09 +0000)]
powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build target
Get rid of the SRIOBOOT_MASTER build target, and to support for serving as
a SRIO boot master via environment variable. Set the environment variable
"bootmaster" to "SRIO1" or "SRIO2" using the following command:
setenv bootmaster SRIO1
saveenv
The "bootmaster" will enable the function of the SRIO boot master, and
this has the following advantages compared with SRIOBOOT_MASTER build
configuration:
1. Reduce a build configuration item in boards.cfg file.
No longer need to build a special image for master, just use a
normal target image and set the "bootmaster" variable.
2. No longer need to rebuild an image when change the SRIO port for
boot from SRIO, just set the corresponding value to "bootmaster"
based on the using SRIO port.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Update some descriptions due to the implementation changes:
For master:
Get rid of the SRIOBOOT_MASTER build target, and to support
for serving as a SRIO boot master via environment variable.
For slave:
1. When compile the slave image for boot from SRIO, no longer
need to specify which SRIO port it will boot from.
2. All slave's cores should be in hold off.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Wed, 8 Aug 2012 18:04:53 +0000 (18:04 +0000)]
powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditional
This erratum applies to the following SoCs:
P4080 rev 1.0, 2.0, fixed in rev 3.0
P2041 rev 1.0, 1.1, fixed in rev 2.0
P3041 rev 1.0, 1.1, fixed in rev 2.0.
Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround
may degrade performance. P4080 erratum CPU22 shares the same workaround.
So it is always enabled for P4080. For other SoCs, it can be disabled by
hwconfig with syntax:
fsl_cpu_a011:disable
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Scott Wood [Wed, 8 Aug 2012 15:03:33 +0000 (15:03 +0000)]
nand/fsl_elbc: shrink SPL a bit by converting out_be32() to __raw_writel()
This is needed to make room for a bugfix on p1_p2_rdb_pc. A sync is used
before the final write to LSOR that initiates the transaction, to ensure
all the other set up has been completed.
Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
PowerPC mandates SP to be 16 bytes aligned.
Furthermore, a stack frame is added, pointing to the reset vector
which may in the way when gdb is walking the stack because
the reset vector may not accessible depending on emulator settings.
Also use a temp register so gdb doesn't pick up intermediate values.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
asm/clk.h was included get_peripheral_clk_rate function. But this
is not used from anywhere.
This removed asm/clk.h, and deleted include line from arch/sh/lib/time.c
projects / u-boot.git / log
