RISC-V: Support Zvabd extension instructions.

This patch adds support for the Zvabd extension instructions:
https://github.com/riscv/integer-vector-absolute-difference

The Zvabd extension provides RISC-V vector integer absolute difference
operations.

The widening accumulate mnemonics follow the current frozen specification
are vwabda.vv and vwabdau.vv.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add Zvabd implication
  of zve32x.
	(riscv_multi_subset_supports_ext): Add Zvabd.

gas/ChangeLog:

	* NEWS:
	* testsuite/gas/riscv/march-help.l: Add Zvabd.
	* testsuite/gas/riscv/zvabd.d: New test.
	* testsuite/gas/riscv/zvabd.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VABS_V): New macro.
	(MASK_VABS_V): Ditto.
	(MATCH_VABD_VV): Ditto.
	(MASK_VABD_VV): Ditto.
	(MATCH_VABDU_VV): Ditto.
	(MASK_VABDU_VV): Ditto.
	(MATCH_VWABDA_VV): Ditto.
	(MASK_VWABDA_VV): Ditto.
	(MATCH_VWABDAU_VV): Ditto.
	(MASK_VWABDAU_VV): Ditto.
	* opcode/riscv.h (enum riscv_insn_class): New extension.

opcodes/ChangeLog:

	* riscv-opc.c: New instructions.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 6bb5e32c8a0f8c2cd3e9495c7ddcbea6d64d7b1b..19e97776f1f58885794df256ccd7a9c7e195cd08 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1234,6 +1234,7 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"xsmtvdotii", "+xsmtvdot", check_implicit_always},
 
   {"v", "+zve64d,+zvl128b", check_implicit_always},
+  {"zvabd", "+zve32x", check_implicit_always},
   {"zvfh", "+zvfhmin,+zfhmin", check_implicit_always},
   {"zvfhmin", "+zve32f", check_implicit_always},
   {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always},
@@ -1516,6 +1517,7 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64x",           ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"zve64f",           ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"zve64d",           ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
+  {"zvabd",            ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"zvbb",             ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"zvbc",             ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"zvfbfmin",         ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
@@ -2972,6 +2974,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
              || riscv_subset_supports (rps, "zve64d")
              || riscv_subset_supports (rps, "zve64f")
              || riscv_subset_supports (rps, "zve32f"));
+    case INSN_CLASS_ZVABD:
+      return riscv_subset_supports (rps, "zvabd");
     case INSN_CLASS_ZVBB:
       return riscv_subset_supports (rps, "zvbb");
     case INSN_CLASS_ZVBC:
@@ -3297,6 +3301,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("v' or `zve64x' or `zve32x");
     case INSN_CLASS_ZVEF:
       return _("v' or `zve64d' or `zve64f' or `zve32f");
+    case INSN_CLASS_ZVABD:
+      return _("zvabd");
     case INSN_CLASS_ZVBB:
       return _("zvbb");
     case INSN_CLASS_ZVBC:

diff --git a/gas/NEWS b/gas/NEWS
index cace494e8ce237ca3aba81642e6893438260147a..186ee96c68772219dc8e7ee346ee822b161c4694 100644 (file)
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -6,7 +6,7 @@
   and will be removed in a future release.
 
 * Add support for RISC-V standard extensions:
-  zalasr v1.0, svrsw60t59b v1.0.
+  zalasr v1.0, svrsw60t59b v1.0, zvabd v1.0.
 
 * Add support for RISC-V vendor extensions:
   SpacemiT: xsmtvdot v1.0, xsmtvdotii v1.0.

diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 6fafe1849c52a4e6ff7efedd821d11296238ca53..df970a5c75d2ae3ea22599d69348d1347b8a2469 100644 (file)
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -69,6 +69,7 @@ All available -march extensions for RISC-V:
        zve64x                                  1.0
        zve64f                                  1.0
        zve64d                                  1.0
+       zvabd                                   1.0
        zvbb                                    1.0
        zvbc                                    1.0
        zvfbfmin                                1.0

diff --git a/gas/testsuite/gas/riscv/zvabd.d b/gas/testsuite/gas/riscv/zvabd.d
new file mode 100644 (file)
index 0000000..8e5f119
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvabd.d
@@ -0,0 +1,13 @@
+#as: -march=rv64gc_zvabd
+#objdump: -dr
+
+.*:[   ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[      ]+[0-9a-f]+:[   ]+4a282257[     ]+vabs.v[       ]+v4,v2
+[      ]+[0-9a-f]+:[   ]+4620a257[     ]+vabd.vv[      ]+v4,v2,v1
+[      ]+[0-9a-f]+:[   ]+4e20a257[     ]+vabdu.vv[     ]+v4,v2,v1
+[      ]+[0-9a-f]+:[   ]+5620a257[     ]+vwabda.vv[    ]+v4,v2,v1
+[      ]+[0-9a-f]+:[   ]+5a20a257[     ]+vwabdau.vv[   ]+v4,v2,v1

diff --git a/gas/testsuite/gas/riscv/zvabd.s b/gas/testsuite/gas/riscv/zvabd.s
new file mode 100644 (file)
index 0000000..4a93070
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvabd.s
@@ -0,0 +1,6 @@
+target:
+       vabs.v           v4, v2
+       vabd.vv          v4, v2, v1
+       vabdu.vv                 v4, v2, v1
+       vwabda.vv                v4, v2, v1
+       vwabdau.vv               v4, v2, v1

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 845bfd6e09362b78bf4c84f3dd29496530f4d1fd..eebf8f2a4356e9bfb3bbc84e491182dcb1f66253 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2275,6 +2275,17 @@
 #define MASK_VSM3C_VI 0xfe00707f
 #define MATCH_VSM3ME_VV 0x82002077
 #define MASK_VSM3ME_VV 0xfe00707f
+/* Zvabd instructions.  */
+#define MATCH_VABS_V 0x48082057
+#define MASK_VABS_V 0xfc0ff07f
+#define MATCH_VABD_VV 0x44002057
+#define MASK_VABD_VV 0xfc00707f
+#define MATCH_VABDU_VV 0x4c002057
+#define MASK_VABDU_VV 0xfc00707f
+#define MATCH_VWABDA_VV 0x54002057
+#define MASK_VWABDA_VV 0xfc00707f
+#define MATCH_VWABDAU_VV 0x58002057
+#define MASK_VWABDAU_VV 0xfc00707f
 /* Zcb instructions.  */
 #define MATCH_C_LBU 0x8000
 #define MASK_C_LBU 0xfc03

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index a6416a17193103d3c5aecfea219104675f02ff91..b4587976ea2e35007849742b0316011614cf0ab3 100644 (file)
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -566,6 +566,7 @@ enum riscv_insn_class
   INSN_CLASS_ZVKNHA_OR_ZVKNHB,
   INSN_CLASS_ZVKSED,
   INSN_CLASS_ZVKSH,
+  INSN_CLASS_ZVABD,
   INSN_CLASS_ZICFISS,
   INSN_CLASS_ZICFISS_AND_ZCMOP,
   INSN_CLASS_ZICFILP,

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index a7c953f00a296c637e6533d4cc8c60d0f9551018..589495ac6c7adb74d8ca0952d6bc4af44efd7a19 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2299,6 +2299,13 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vsm3c.vi",     0, INSN_CLASS_ZVKSH, "Vd,Vt,Vj", MATCH_VSM3C_VI, MASK_VSM3C_VI, match_opcode, 0},
 {"vsm3me.vv",    0, INSN_CLASS_ZVKSH, "Vd,Vt,Vs", MATCH_VSM3ME_VV, MASK_VSM3ME_VV, match_opcode, 0},
 
+/* Zvabd instructions.  */
+{"vabs.v",       0, INSN_CLASS_ZVABD, "Vd,VtVm",    MATCH_VABS_V,     MASK_VABS_V,     match_opcode, 0},
+{"vabd.vv",      0, INSN_CLASS_ZVABD, "Vd,Vt,VsVm", MATCH_VABD_VV,    MASK_VABD_VV,    match_opcode, 0},
+{"vabdu.vv",     0, INSN_CLASS_ZVABD, "Vd,Vt,VsVm", MATCH_VABDU_VV,   MASK_VABDU_VV,   match_opcode, 0},
+{"vwabda.vv",    0, INSN_CLASS_ZVABD, "Vd,Vt,VsVm", MATCH_VWABDA_VV,  MASK_VWABDA_VV,  match_opcode, 0},
+{"vwabdau.vv",   0, INSN_CLASS_ZVABD, "Vd,Vt,VsVm", MATCH_VWABDAU_VV, MASK_VWABDAU_VV, match_opcode, 0},
+
 /* ZCB instructions.  */
 {"c.lbu",      0, INSN_CLASS_ZCB, "Ct,Wcb(Cs)", MATCH_C_LBU, MASK_C_LBU, match_opcode, INSN_DREF|INSN_1_BYTE },
 {"c.lhu",      0, INSN_CLASS_ZCB, "Ct,Wch(Cs)", MATCH_C_LHU, MASK_C_LHU, match_opcode, INSN_DREF|INSN_2_BYTE },