.os_hint = MSG_OS_HINT_RN,
};
+static const struct amd_pmc_cpu_info amd_1ah_m80_cpu_info = {
+ .smu_msg = AMD_PMC_REGISTER_MSG_1AH_80H,
+ .smu_arg = AMD_PMC_REGISTER_ARG_1AH_80H,
+ .smu_rsp = AMD_PMC_REGISTER_RSP_1AH_80H,
+ .num_ips = ARRAY_SIZE(soc15_ip_blk),
+ .scratch_reg = AMD_PMC_SCRATCH_REG_1AH,
+ .ips_ptr = soc15_ip_blk,
+ .os_hint = MSG_OS_HINT_RN,
+};
+
static const struct pci_device_id pmc_pci_ids[] = {
{ PCI_DEVICE_DATA(AMD, CPU_ID_PCO, &amd_pco_cpu_info) },
{ PCI_DEVICE_DATA(AMD, CPU_ID_CZN, &amd_czn_cpu_info) },
{ PCI_DEVICE_DATA(AMD, CPU_ID_SHP, NULL) },
{ PCI_DEVICE_DATA(AMD, 1AH_M20H_ROOT, NULL) },
{ PCI_DEVICE_DATA(AMD, 1AH_M60H_ROOT, NULL) },
+ { PCI_DEVICE_DATA(AMD, 1AH_M80H_ROOT, &amd_1ah_m80_cpu_info) },
{ }
};
{"AMDI0009", 0},
{"AMDI000A", 0},
{"AMDI000B", 0},
+ {"AMDI000C", 0},
{"AMD0004", 0},
{"AMD0005", 0},
{ }
/* SMU communication registers for 1Ah 20h SoC */
#define AMD_PMC_REGISTER_MSG_1AH_20H 0x938
+/* SMU communication registers for 1Ah 80h SoC */
+#define AMD_PMC_REGISTER_MSG_1AH_80H 0xA10
+#define AMD_PMC_REGISTER_ARG_1AH_80H 0xA18
+#define AMD_PMC_REGISTER_RSP_1AH_80H 0xA14
+
/* PMC Scratch Registers */
#define AMD_PMC_SCRATCH_REG_CZN 0x94
#define AMD_PMC_SCRATCH_REG_YC 0xD14
#define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507
#define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122
+#define PCI_DEVICE_ID_AMD_1AH_M80H_ROOT 0x115b
#define PCI_DEVICE_ID_AMD_MP2_STB 0x172c
int amd_stb_s2d_init(struct amd_pmc_dev *dev);