--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,nord-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on Nord SoC
+
+maintainers:
+ - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on Nord SoC.
+
+ See also: include/dt-bindings/clock/qcom,nord-gcc.h
+
+properties:
+ compatible:
+ const: qcom,nord-gcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+ - description: PCIE A Pipe clock source
+ - description: PCIE B Pipe clock source
+ - description: PCIE C Pipe clock source
+ - description: PCIE D Pipe clock source
+
+required:
+ - compatible
+ - clocks
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@100000 {
+ compatible = "qcom,nord-gcc";
+ reg = <0x00100000 0x1f4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <&pcie_a_pipe_clk>,
+ <&pcie_b_pipe_clk>,
+ <&pcie_c_pipe_clk>,
+ <&pcie_d_pipe_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,nord-negcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global North East Clock & Reset Controller on Nord SoC
+
+maintainers:
+ - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description: |
+ Qualcomm global clock control (NE) module provides the clocks, resets
+ and power domains on Nord SoC.
+
+ See also: include/dt-bindings/clock/qcom,nord-negcc.h
+
+properties:
+ compatible:
+ const: qcom,nord-negcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+ - description: UFS Phy Rx symbol 0 clock source
+ - description: UFS Phy Rx symbol 1 clock source
+ - description: UFS Phy Tx symbol 0 clock source
+ - description: USB3 Phy sec wrapper pipe clock source
+ - description: USB3 Phy wrapper pipe clock source
+
+required:
+ - compatible
+ - clocks
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@8900000 {
+ compatible = "qcom,nord-negcc";
+ reg = <0x08900000 0xf4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <&ufs_phy_rx_symbol_0_clk>,
+ <&ufs_phy_rx_symbol_1_clk>,
+ <&ufs_phy_tx_symbol_0_clk>,
+ <&usb3_phy_sec_pipe_clk>,
+ <&usb3_phy_pipe_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,nord-nwgcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global North West and South East Clock & Reset Controller
+ on Nord SoC
+
+maintainers:
+ - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description: |
+ Qualcomm global clock control (NW, SE) module provides the clocks, resets
+ and power domains on Nord SoC.
+
+ See also:
+ include/dt-bindings/clock/qcom,nord-nwgcc.h
+ include/dt-bindings/clock/qcom,nord-segcc.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,nord-nwgcc
+ - qcom,nord-segcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+
+required:
+ - compatible
+ - clocks
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@8b00000 {
+ compatible = "qcom,nord-nwgcc";
+ reg = <0x08b00000 0xf4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+...
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_NORD_H
+
+/* GCC clocks */
+#define GCC_BOOT_ROM_AHB_CLK 0
+#define GCC_GP1_CLK 1
+#define GCC_GP1_CLK_SRC 2
+#define GCC_GP2_CLK 3
+#define GCC_GP2_CLK_SRC 4
+#define GCC_GPLL0 5
+#define GCC_GPLL0_OUT_EVEN 6
+#define GCC_MMU_0_TCU_VOTE_CLK 7
+#define GCC_PCIE_A_AUX_CLK 8
+#define GCC_PCIE_A_AUX_CLK_SRC 9
+#define GCC_PCIE_A_CFG_AHB_CLK 10
+#define GCC_PCIE_A_DTI_QTC_CLK 11
+#define GCC_PCIE_A_MSTR_AXI_CLK 12
+#define GCC_PCIE_A_PHY_AUX_CLK 13
+#define GCC_PCIE_A_PHY_AUX_CLK_SRC 14
+#define GCC_PCIE_A_PHY_RCHNG_CLK 15
+#define GCC_PCIE_A_PHY_RCHNG_CLK_SRC 16
+#define GCC_PCIE_A_PIPE_CLK 17
+#define GCC_PCIE_A_PIPE_CLK_SRC 18
+#define GCC_PCIE_A_SLV_AXI_CLK 19
+#define GCC_PCIE_A_SLV_Q2A_AXI_CLK 20
+#define GCC_PCIE_B_AUX_CLK 21
+#define GCC_PCIE_B_AUX_CLK_SRC 22
+#define GCC_PCIE_B_CFG_AHB_CLK 23
+#define GCC_PCIE_B_DTI_QTC_CLK 24
+#define GCC_PCIE_B_MSTR_AXI_CLK 25
+#define GCC_PCIE_B_PHY_AUX_CLK 26
+#define GCC_PCIE_B_PHY_AUX_CLK_SRC 27
+#define GCC_PCIE_B_PHY_RCHNG_CLK 28
+#define GCC_PCIE_B_PHY_RCHNG_CLK_SRC 29
+#define GCC_PCIE_B_PIPE_CLK 30
+#define GCC_PCIE_B_PIPE_CLK_SRC 31
+#define GCC_PCIE_B_SLV_AXI_CLK 32
+#define GCC_PCIE_B_SLV_Q2A_AXI_CLK 33
+#define GCC_PCIE_C_AUX_CLK 34
+#define GCC_PCIE_C_AUX_CLK_SRC 35
+#define GCC_PCIE_C_CFG_AHB_CLK 36
+#define GCC_PCIE_C_DTI_QTC_CLK 37
+#define GCC_PCIE_C_MSTR_AXI_CLK 38
+#define GCC_PCIE_C_PHY_AUX_CLK 39
+#define GCC_PCIE_C_PHY_AUX_CLK_SRC 40
+#define GCC_PCIE_C_PHY_RCHNG_CLK 41
+#define GCC_PCIE_C_PHY_RCHNG_CLK_SRC 42
+#define GCC_PCIE_C_PIPE_CLK 43
+#define GCC_PCIE_C_PIPE_CLK_SRC 44
+#define GCC_PCIE_C_SLV_AXI_CLK 45
+#define GCC_PCIE_C_SLV_Q2A_AXI_CLK 46
+#define GCC_PCIE_D_AUX_CLK 47
+#define GCC_PCIE_D_AUX_CLK_SRC 48
+#define GCC_PCIE_D_CFG_AHB_CLK 49
+#define GCC_PCIE_D_DTI_QTC_CLK 50
+#define GCC_PCIE_D_MSTR_AXI_CLK 51
+#define GCC_PCIE_D_PHY_AUX_CLK 52
+#define GCC_PCIE_D_PHY_AUX_CLK_SRC 53
+#define GCC_PCIE_D_PHY_RCHNG_CLK 54
+#define GCC_PCIE_D_PHY_RCHNG_CLK_SRC 55
+#define GCC_PCIE_D_PIPE_CLK 56
+#define GCC_PCIE_D_PIPE_CLK_SRC 57
+#define GCC_PCIE_D_SLV_AXI_CLK 58
+#define GCC_PCIE_D_SLV_Q2A_AXI_CLK 59
+#define GCC_PCIE_LINK_AHB_CLK 60
+#define GCC_PCIE_LINK_XO_CLK 61
+#define GCC_PCIE_NOC_ASYNC_BRIDGE_CLK 62
+#define GCC_PCIE_NOC_CNOC_SF_QX_CLK 63
+#define GCC_PCIE_NOC_M_CFG_CLK 64
+#define GCC_PCIE_NOC_M_PDB_CLK 65
+#define GCC_PCIE_NOC_MSTR_AXI_CLK 66
+#define GCC_PCIE_NOC_PWRCTL_CLK 67
+#define GCC_PCIE_NOC_QOSGEN_EXTREF_CLK 68
+#define GCC_PCIE_NOC_REFGEN_CLK 69
+#define GCC_PCIE_NOC_REFGEN_CLK_SRC 70
+#define GCC_PCIE_NOC_S_CFG_CLK 71
+#define GCC_PCIE_NOC_S_PDB_CLK 72
+#define GCC_PCIE_NOC_SAFETY_CLK 73
+#define GCC_PCIE_NOC_SAFETY_CLK_SRC 74
+#define GCC_PCIE_NOC_SLAVE_AXI_CLK 75
+#define GCC_PCIE_NOC_TSCTR_CLK 76
+#define GCC_PCIE_NOC_XO_CLK 77
+#define GCC_PDM2_CLK 78
+#define GCC_PDM2_CLK_SRC 79
+#define GCC_PDM_AHB_CLK 80
+#define GCC_PDM_XO4_CLK 81
+#define GCC_QUPV3_WRAP3_CORE_2X_CLK 82
+#define GCC_QUPV3_WRAP3_CORE_CLK 83
+#define GCC_QUPV3_WRAP3_M_CLK 84
+#define GCC_QUPV3_WRAP3_QSPI_REF_CLK 85
+#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 86
+#define GCC_QUPV3_WRAP3_S0_CLK 87
+#define GCC_QUPV3_WRAP3_S0_CLK_SRC 88
+#define GCC_QUPV3_WRAP3_S_AHB_CLK 89
+#define GCC_SMMU_PCIE_QTC_VOTE_CLK 90
+
+/* GCC power domains */
+#define GCC_PCIE_A_GDSC 0
+#define GCC_PCIE_A_PHY_GDSC 1
+#define GCC_PCIE_B_GDSC 2
+#define GCC_PCIE_B_PHY_GDSC 3
+#define GCC_PCIE_C_GDSC 4
+#define GCC_PCIE_C_PHY_GDSC 5
+#define GCC_PCIE_D_GDSC 6
+#define GCC_PCIE_D_PHY_GDSC 7
+#define GCC_PCIE_NOC_GDSC 8
+
+/* GCC resets */
+#define GCC_PCIE_A_BCR 0
+#define GCC_PCIE_A_LINK_DOWN_BCR 1
+#define GCC_PCIE_A_NOCSR_COM_PHY_BCR 2
+#define GCC_PCIE_A_PHY_BCR 3
+#define GCC_PCIE_A_PHY_CFG_AHB_BCR 4
+#define GCC_PCIE_A_PHY_COM_BCR 5
+#define GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR 6
+#define GCC_PCIE_B_BCR 7
+#define GCC_PCIE_B_LINK_DOWN_BCR 8
+#define GCC_PCIE_B_NOCSR_COM_PHY_BCR 9
+#define GCC_PCIE_B_PHY_BCR 10
+#define GCC_PCIE_B_PHY_CFG_AHB_BCR 11
+#define GCC_PCIE_B_PHY_COM_BCR 12
+#define GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR 13
+#define GCC_PCIE_C_BCR 14
+#define GCC_PCIE_C_LINK_DOWN_BCR 15
+#define GCC_PCIE_C_NOCSR_COM_PHY_BCR 16
+#define GCC_PCIE_C_PHY_BCR 17
+#define GCC_PCIE_C_PHY_CFG_AHB_BCR 18
+#define GCC_PCIE_C_PHY_COM_BCR 19
+#define GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR 20
+#define GCC_PCIE_D_BCR 21
+#define GCC_PCIE_D_LINK_DOWN_BCR 22
+#define GCC_PCIE_D_NOCSR_COM_PHY_BCR 23
+#define GCC_PCIE_D_PHY_BCR 24
+#define GCC_PCIE_D_PHY_CFG_AHB_BCR 25
+#define GCC_PCIE_D_PHY_COM_BCR 26
+#define GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR 27
+#define GCC_PCIE_NOC_BCR 28
+#define GCC_PDM_BCR 29
+#define GCC_QUPV3_WRAPPER_3_BCR 30
+#define GCC_TCSR_PCIE_BCR 31
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H
+
+/* NE_GCC clocks */
+#define NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK 0
+#define NE_GCC_AGGRE_NOC_USB2_AXI_CLK 1
+#define NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK 2
+#define NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK 3
+#define NE_GCC_AHB2PHY_CLK 4
+#define NE_GCC_CNOC_USB2_AXI_CLK 5
+#define NE_GCC_CNOC_USB3_PRIM_AXI_CLK 6
+#define NE_GCC_CNOC_USB3_SEC_AXI_CLK 7
+#define NE_GCC_FRQ_MEASURE_REF_CLK 8
+#define NE_GCC_GP1_CLK 9
+#define NE_GCC_GP1_CLK_SRC 10
+#define NE_GCC_GP2_CLK 11
+#define NE_GCC_GP2_CLK_SRC 12
+#define NE_GCC_GPLL0 13
+#define NE_GCC_GPLL0_OUT_EVEN 14
+#define NE_GCC_GPLL2 15
+#define NE_GCC_GPU_2_CFG_CLK 16
+#define NE_GCC_GPU_2_GPLL0_CLK_SRC 17
+#define NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC 18
+#define NE_GCC_GPU_2_HSCNOC_GFX_CLK 19
+#define NE_GCC_GPU_2_SMMU_VOTE_CLK 20
+#define NE_GCC_QUPV3_WRAP2_CORE_2X_CLK 21
+#define NE_GCC_QUPV3_WRAP2_CORE_CLK 22
+#define NE_GCC_QUPV3_WRAP2_M_AHB_CLK 23
+#define NE_GCC_QUPV3_WRAP2_S0_CLK 24
+#define NE_GCC_QUPV3_WRAP2_S0_CLK_SRC 25
+#define NE_GCC_QUPV3_WRAP2_S1_CLK 26
+#define NE_GCC_QUPV3_WRAP2_S1_CLK_SRC 27
+#define NE_GCC_QUPV3_WRAP2_S2_CLK 28
+#define NE_GCC_QUPV3_WRAP2_S2_CLK_SRC 29
+#define NE_GCC_QUPV3_WRAP2_S3_CLK 30
+#define NE_GCC_QUPV3_WRAP2_S3_CLK_SRC 31
+#define NE_GCC_QUPV3_WRAP2_S4_CLK 32
+#define NE_GCC_QUPV3_WRAP2_S4_CLK_SRC 33
+#define NE_GCC_QUPV3_WRAP2_S5_CLK 34
+#define NE_GCC_QUPV3_WRAP2_S5_CLK_SRC 35
+#define NE_GCC_QUPV3_WRAP2_S6_CLK 36
+#define NE_GCC_QUPV3_WRAP2_S6_CLK_SRC 37
+#define NE_GCC_QUPV3_WRAP2_S_AHB_CLK 38
+#define NE_GCC_SDCC4_APPS_CLK 39
+#define NE_GCC_SDCC4_APPS_CLK_SRC 40
+#define NE_GCC_SDCC4_AXI_CLK 41
+#define NE_GCC_UFS_PHY_AHB_CLK 42
+#define NE_GCC_UFS_PHY_AXI_CLK 43
+#define NE_GCC_UFS_PHY_AXI_CLK_SRC 44
+#define NE_GCC_UFS_PHY_ICE_CORE_CLK 45
+#define NE_GCC_UFS_PHY_ICE_CORE_CLK_SRC 46
+#define NE_GCC_UFS_PHY_PHY_AUX_CLK 47
+#define NE_GCC_UFS_PHY_PHY_AUX_CLK_SRC 48
+#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK 49
+#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 50
+#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK 51
+#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 52
+#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK 53
+#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 54
+#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK 55
+#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 56
+#define NE_GCC_USB20_MASTER_CLK 57
+#define NE_GCC_USB20_MASTER_CLK_SRC 58
+#define NE_GCC_USB20_MOCK_UTMI_CLK 59
+#define NE_GCC_USB20_MOCK_UTMI_CLK_SRC 60
+#define NE_GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 61
+#define NE_GCC_USB20_SLEEP_CLK 62
+#define NE_GCC_USB31_PRIM_ATB_CLK 63
+#define NE_GCC_USB31_PRIM_EUD_AHB_CLK 64
+#define NE_GCC_USB31_PRIM_MASTER_CLK 65
+#define NE_GCC_USB31_PRIM_MASTER_CLK_SRC 66
+#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK 67
+#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK_SRC 68
+#define NE_GCC_USB31_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 69
+#define NE_GCC_USB31_PRIM_SLEEP_CLK 70
+#define NE_GCC_USB31_SEC_ATB_CLK 71
+#define NE_GCC_USB31_SEC_EUD_AHB_CLK 72
+#define NE_GCC_USB31_SEC_MASTER_CLK 73
+#define NE_GCC_USB31_SEC_MASTER_CLK_SRC 74
+#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK 75
+#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK_SRC 76
+#define NE_GCC_USB31_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 77
+#define NE_GCC_USB31_SEC_SLEEP_CLK 78
+#define NE_GCC_USB3_PRIM_PHY_AUX_CLK 79
+#define NE_GCC_USB3_PRIM_PHY_AUX_CLK_SRC 80
+#define NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK 81
+#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK 82
+#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 83
+#define NE_GCC_USB3_SEC_PHY_AUX_CLK 84
+#define NE_GCC_USB3_SEC_PHY_AUX_CLK_SRC 85
+#define NE_GCC_USB3_SEC_PHY_COM_AUX_CLK 86
+#define NE_GCC_USB3_SEC_PHY_PIPE_CLK 87
+#define NE_GCC_USB3_SEC_PHY_PIPE_CLK_SRC 88
+
+/* NE_GCC power domains */
+#define NE_GCC_UFS_MEM_PHY_GDSC 0
+#define NE_GCC_UFS_PHY_GDSC 1
+#define NE_GCC_USB20_PRIM_GDSC 2
+#define NE_GCC_USB31_PRIM_GDSC 3
+#define NE_GCC_USB31_SEC_GDSC 4
+#define NE_GCC_USB3_PHY_GDSC 5
+#define NE_GCC_USB3_SEC_PHY_GDSC 6
+
+/* NE_GCC resets */
+#define NE_GCC_GPU_2_BCR 0
+#define NE_GCC_QUPV3_WRAPPER_2_BCR 1
+#define NE_GCC_SDCC4_BCR 2
+#define NE_GCC_UFS_PHY_BCR 3
+#define NE_GCC_USB20_PRIM_BCR 4
+#define NE_GCC_USB31_PRIM_BCR 5
+#define NE_GCC_USB31_SEC_BCR 6
+#define NE_GCC_USB3_DP_PHY_PRIM_BCR 7
+#define NE_GCC_USB3_DP_PHY_SEC_BCR 8
+#define NE_GCC_USB3_PHY_PRIM_BCR 9
+#define NE_GCC_USB3_PHY_SEC_BCR 10
+#define NE_GCC_USB3PHY_PHY_PRIM_BCR 11
+#define NE_GCC_USB3PHY_PHY_SEC_BCR 12
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H
+
+/* NW_GCC clocks */
+#define NW_GCC_ACMU_MUX_CLK 0
+#define NW_GCC_CAMERA_AHB_CLK 1
+#define NW_GCC_CAMERA_HF_AXI_CLK 2
+#define NW_GCC_CAMERA_SF_AXI_CLK 3
+#define NW_GCC_CAMERA_TRIG_CLK 4
+#define NW_GCC_CAMERA_XO_CLK 5
+#define NW_GCC_DISP_0_AHB_CLK 6
+#define NW_GCC_DISP_0_HF_AXI_CLK 7
+#define NW_GCC_DISP_0_TRIG_CLK 8
+#define NW_GCC_DISP_1_AHB_CLK 9
+#define NW_GCC_DISP_1_HF_AXI_CLK 10
+#define NW_GCC_DISP_1_TRIG_CLK 11
+#define NW_GCC_DPRX0_AXI_HF_CLK 12
+#define NW_GCC_DPRX0_CFG_AHB_CLK 13
+#define NW_GCC_DPRX1_AXI_HF_CLK 14
+#define NW_GCC_DPRX1_CFG_AHB_CLK 15
+#define NW_GCC_EVA_AHB_CLK 16
+#define NW_GCC_EVA_AXI0_CLK 17
+#define NW_GCC_EVA_AXI0C_CLK 18
+#define NW_GCC_EVA_TRIG_CLK 19
+#define NW_GCC_EVA_XO_CLK 20
+#define NW_GCC_FRQ_MEASURE_REF_CLK 21
+#define NW_GCC_GP1_CLK 22
+#define NW_GCC_GP1_CLK_SRC 23
+#define NW_GCC_GP2_CLK 24
+#define NW_GCC_GP2_CLK_SRC 25
+#define NW_GCC_GPLL0 26
+#define NW_GCC_GPLL0_OUT_EVEN 27
+#define NW_GCC_GPU_2_CFG_AHB_CLK 28
+#define NW_GCC_GPU_2_GPLL0_CLK_SRC 29
+#define NW_GCC_GPU_2_GPLL0_DIV_CLK_SRC 30
+#define NW_GCC_GPU_2_HSCNOC_GFX_CLK 31
+#define NW_GCC_GPU_CFG_AHB_CLK 32
+#define NW_GCC_GPU_GPLL0_CLK_SRC 33
+#define NW_GCC_GPU_GPLL0_DIV_CLK_SRC 34
+#define NW_GCC_GPU_HSCNOC_GFX_CLK 35
+#define NW_GCC_GPU_SMMU_VOTE_CLK 36
+#define NW_GCC_HSCNOC_GPU_2_AXI_CLK 37
+#define NW_GCC_HSCNOC_GPU_AXI_CLK 38
+#define NW_GCC_MMU_1_TCU_VOTE_CLK 39
+#define NW_GCC_VIDEO_AHB_CLK 40
+#define NW_GCC_VIDEO_AXI0_CLK 41
+#define NW_GCC_VIDEO_AXI0C_CLK 42
+#define NW_GCC_VIDEO_AXI1_CLK 43
+#define NW_GCC_VIDEO_XO_CLK 44
+
+/* NW_GCC power domains */
+
+/* NW_GCC resets */
+#define NW_GCC_CAMERA_BCR 0
+#define NW_GCC_DISPLAY_0_BCR 1
+#define NW_GCC_DISPLAY_1_BCR 2
+#define NW_GCC_DPRX0_BCR 3
+#define NW_GCC_DPRX1_BCR 4
+#define NW_GCC_EVA_BCR 5
+#define NW_GCC_GPU_2_BCR 6
+#define NW_GCC_GPU_BCR 7
+#define NW_GCC_VIDEO_BCR 8
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H
+
+/* SE_GCC clocks */
+#define SE_GCC_EEE_EMAC0_CLK 0
+#define SE_GCC_EEE_EMAC0_CLK_SRC 1
+#define SE_GCC_EEE_EMAC1_CLK 2
+#define SE_GCC_EEE_EMAC1_CLK_SRC 3
+#define SE_GCC_EMAC0_AXI_CLK 4
+#define SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK 5
+#define SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK 6
+#define SE_GCC_EMAC0_PHY_AUX_CLK 7
+#define SE_GCC_EMAC0_PHY_AUX_CLK_SRC 8
+#define SE_GCC_EMAC0_PTP_CLK 9
+#define SE_GCC_EMAC0_PTP_CLK_SRC 10
+#define SE_GCC_EMAC0_RGMII_CLK 11
+#define SE_GCC_EMAC0_RGMII_CLK_SRC 12
+#define SE_GCC_EMAC0_RPCS_RX_CLK 13
+#define SE_GCC_EMAC0_RPCS_TX_CLK 14
+#define SE_GCC_EMAC0_XGXS_RX_CLK 15
+#define SE_GCC_EMAC0_XGXS_TX_CLK 16
+#define SE_GCC_EMAC1_AXI_CLK 17
+#define SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK 18
+#define SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK 19
+#define SE_GCC_EMAC1_PHY_AUX_CLK 20
+#define SE_GCC_EMAC1_PHY_AUX_CLK_SRC 21
+#define SE_GCC_EMAC1_PTP_CLK 22
+#define SE_GCC_EMAC1_PTP_CLK_SRC 23
+#define SE_GCC_EMAC1_RGMII_CLK 24
+#define SE_GCC_EMAC1_RGMII_CLK_SRC 25
+#define SE_GCC_EMAC1_RPCS_RX_CLK 26
+#define SE_GCC_EMAC1_RPCS_TX_CLK 27
+#define SE_GCC_EMAC1_XGXS_RX_CLK 28
+#define SE_GCC_EMAC1_XGXS_TX_CLK 29
+#define SE_GCC_FRQ_MEASURE_REF_CLK 30
+#define SE_GCC_GP1_CLK 31
+#define SE_GCC_GP1_CLK_SRC 32
+#define SE_GCC_GP2_CLK 33
+#define SE_GCC_GP2_CLK_SRC 34
+#define SE_GCC_GPLL0 35
+#define SE_GCC_GPLL0_OUT_EVEN 36
+#define SE_GCC_GPLL2 37
+#define SE_GCC_GPLL4 38
+#define SE_GCC_GPLL5 39
+#define SE_GCC_MMU_2_TCU_VOTE_CLK 40
+#define SE_GCC_QUPV3_WRAP0_CORE_2X_CLK 41
+#define SE_GCC_QUPV3_WRAP0_CORE_CLK 42
+#define SE_GCC_QUPV3_WRAP0_M_AHB_CLK 43
+#define SE_GCC_QUPV3_WRAP0_S0_CLK 44
+#define SE_GCC_QUPV3_WRAP0_S0_CLK_SRC 45
+#define SE_GCC_QUPV3_WRAP0_S1_CLK 46
+#define SE_GCC_QUPV3_WRAP0_S1_CLK_SRC 47
+#define SE_GCC_QUPV3_WRAP0_S2_CLK 48
+#define SE_GCC_QUPV3_WRAP0_S2_CLK_SRC 49
+#define SE_GCC_QUPV3_WRAP0_S3_CLK 50
+#define SE_GCC_QUPV3_WRAP0_S3_CLK_SRC 51
+#define SE_GCC_QUPV3_WRAP0_S4_CLK 52
+#define SE_GCC_QUPV3_WRAP0_S4_CLK_SRC 53
+#define SE_GCC_QUPV3_WRAP0_S5_CLK 54
+#define SE_GCC_QUPV3_WRAP0_S5_CLK_SRC 55
+#define SE_GCC_QUPV3_WRAP0_S6_CLK 56
+#define SE_GCC_QUPV3_WRAP0_S6_CLK_SRC 57
+#define SE_GCC_QUPV3_WRAP0_S_AHB_CLK 58
+#define SE_GCC_QUPV3_WRAP1_CORE_2X_CLK 59
+#define SE_GCC_QUPV3_WRAP1_CORE_CLK 60
+#define SE_GCC_QUPV3_WRAP1_M_AHB_CLK 61
+#define SE_GCC_QUPV3_WRAP1_S0_CLK 62
+#define SE_GCC_QUPV3_WRAP1_S0_CLK_SRC 63
+#define SE_GCC_QUPV3_WRAP1_S1_CLK 64
+#define SE_GCC_QUPV3_WRAP1_S1_CLK_SRC 65
+#define SE_GCC_QUPV3_WRAP1_S2_CLK 66
+#define SE_GCC_QUPV3_WRAP1_S2_CLK_SRC 67
+#define SE_GCC_QUPV3_WRAP1_S3_CLK 68
+#define SE_GCC_QUPV3_WRAP1_S3_CLK_SRC 69
+#define SE_GCC_QUPV3_WRAP1_S4_CLK 70
+#define SE_GCC_QUPV3_WRAP1_S4_CLK_SRC 71
+#define SE_GCC_QUPV3_WRAP1_S5_CLK 72
+#define SE_GCC_QUPV3_WRAP1_S5_CLK_SRC 73
+#define SE_GCC_QUPV3_WRAP1_S6_CLK 74
+#define SE_GCC_QUPV3_WRAP1_S6_CLK_SRC 75
+#define SE_GCC_QUPV3_WRAP1_S_AHB_CLK 76
+
+/* SE_GCC power domains */
+#define SE_GCC_EMAC0_GDSC 0
+#define SE_GCC_EMAC1_GDSC 1
+
+/* SE_GCC resets */
+#define SE_GCC_EMAC0_BCR 0
+#define SE_GCC_EMAC1_BCR 1
+#define SE_GCC_QUPV3_WRAPPER_0_BCR 2
+#define SE_GCC_QUPV3_WRAPPER_1_BCR 3
+
+#endif
projects / thirdparty / kernel / linux.git / commitdiff
