riscv: smp: Clarify comment "cache" -> "instruction cache"

local_flush_icache_all() only flushes and synchronizes the *instruction*
cache, not the data cache. Since RISC-V does have a cbo.flush
instruction for data cache flush, clarify the comment to avoid
confusion.

Fixes: 58661a30f1bc ("riscv: Flush the instruction cache during SMP bringup")
Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
Link: https://patch.msgid.link/20260204-riscv-smp-comment-update-2026-01-v1-2-8b77aa181530@iscas.ac.cn
Signed-off-by: Paul Walmsley <pjw@kernel.org>

diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 0e6fe20c69a22e06baf42c770f1d08ea3fa30d2b..8b628580fe118e713873d04056938235ec39cb5d 100644 (file)
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -251,8 +251,8 @@ asmlinkage __visible void smp_callin(void)
        set_cpu_online(curr_cpuid, true);
 
        /*
-        * Remote cache and TLB flushes are ignored while the CPU is offline,
-        * so flush them both right now just in case.
+        * Remote instruction cache and TLB flushes are ignored while the CPU
+        * is offline, so flush them both right now just in case.
         */
        local_flush_icache_all();
        local_flush_tlb_all();