{
u32 reg;
- /* Set RX and TX tigger levels, flush FIFOs */
+ /* Set RX and TX trigger levels, flush FIFOs */
reg = SVC_I3C_MDATACTRL_FLUSHTB |
SVC_I3C_MDATACTRL_FLUSHRB |
SVC_I3C_MDATACTRL_UNLOCK_TRIG |
* 3. IBI isr writes an AutoIBI request.
* 4. The controller will not start AutoIBI process because SDA is not low.
* 5. IBIWON polling times out.
- * 6. Controller reamins in AutoIBI state and doesn't accept EmitStop request.
+ * 6. Controller remains in AutoIBI state and doesn't accept EmitStop request.
*/
writel(SVC_I3C_MCTRL_REQUEST_START_ADDR |
SVC_I3C_MCTRL_TYPE_I3C |
/*
* Using I3C Open-Drain mode, target is 4.17MHz/240ns with a
- * duty-cycle tuned so that high levels are filetered out by
+ * duty-cycle tuned so that high levels are filtered out by
* the 50ns filter (target being 40ns).
*/
odhpp = 1;