clk: rockchip: rk3568: Add PCIe pipe clock gates

The PCIe pipe clocks are currently left as orphan clocks and remain
enabled indefinitely, which is suboptimal. Add the missing clock gates
so the PCIe driver can explicitly manage them when not in use. In order
not to break compatibility with old DTB, mark them as CLK_IGNORE_UNUSED.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://patch.msgid.link/1772799641-32164-1-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 74eabf9b2ae2e1414bfd1ee9b5b97180cefe6e8e..d571c4b0c35f7e3b1936b20ecc73f3f01eae7515 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -827,6 +827,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
                        RK3568_CLKGATE_CON(12), 3, GFLAGS),
        GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0,
                        RK3568_CLKGATE_CON(12), 4, GFLAGS),
+       GATE(CLK_PCIE20_PIPE_DFT, "clk_pcie20_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
+                       RK3568_CLKGATE_CON(12), 5, GFLAGS),
        GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0,
                        RK3568_CLKGATE_CON(12), 8, GFLAGS),
        GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0,
@@ -837,6 +839,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
                        RK3568_CLKGATE_CON(12), 11, GFLAGS),
        GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0,
                        RK3568_CLKGATE_CON(12), 12, GFLAGS),
+       GATE(CLK_PCIE30X1_PIPE_DFT, "clk_pcie30x1_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
+                       RK3568_CLKGATE_CON(12), 13, GFLAGS),
        GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0,
                        RK3568_CLKGATE_CON(13), 0, GFLAGS),
        GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0,
@@ -847,6 +851,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
                        RK3568_CLKGATE_CON(13), 3, GFLAGS),
        GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0,
                        RK3568_CLKGATE_CON(13), 4, GFLAGS),
+       GATE(CLK_PCIE30X2_PIPE_DFT, "clk_pcie30x2_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
+                       RK3568_CLKGATE_CON(13), 5, GFLAGS),
        GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0,
                        RK3568_CLKGATE_CON(11), 0, GFLAGS),
        GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0,