7.1-stable patches

added patches:
	kvm-arm64-vgic-avoid-double-deactivate-of-irqs-in-the-nested-context.patch

diff --git a/queue-7.1/kvm-arm64-vgic-avoid-double-deactivate-of-irqs-in-the-nested-context.patch b/queue-7.1/kvm-arm64-vgic-avoid-double-deactivate-of-irqs-in-the-nested-context.patch
new file mode 100644 (file)
index 0000000..055cccd
--- /dev/null
+++ b/queue-7.1/kvm-arm64-vgic-avoid-double-deactivate-of-irqs-in-the-nested-context.patch
@@ -0,0 +1,66 @@
+From 8a570b19b4b16a8a3b5ffa2b332bd5613110b2d8 Mon Sep 17 00:00:00 2001
+From: D Scott Phillips <scott@os.amperecomputing.com>
+Date: Tue, 14 Jul 2026 16:11:58 -0700
+Subject: KVM: arm64: vgic: Avoid double-deactivate of IRQs in the nested context
+
+From: D Scott Phillips <scott@os.amperecomputing.com>
+
+commit 8a570b19b4b16a8a3b5ffa2b332bd5613110b2d8 upstream.
+
+In the nested state, the physical interrupt has already been
+deactivated through the HW bit in the LR. The extra deactivation
+would be harmless but can hit an errata case on AmpereOne, so
+avoid it here.
+
+On AmpereOne, deactivating a physical interrupt through
+ICC_DIR_EL1 or ICC_EOIR1_EL1 (depending on EOImode) which is not
+active, but is the highest priority pending interrupt causes the
+cpu to lose the interrupt pending state and also prevents the
+delivery of future interrupts.
+
+Fixes: 6dd333c8942b2 ("KVM: arm64: GICv3: nv: Plug L1 LR sync into deactivation primitive")
+Signed-off-by: D Scott Phillips <scott@os.amperecomputing.com>
+Cc: stable@vger.kernel.org
+Link: https://lore.kernel.org/linux-arm-kernel/20260710222128.416581-1-scott@os.amperecomputing.com/
+Link: https://patch.msgid.link/20260714231158.496808-1-scott@os.amperecomputing.com
+Signed-off-by: Marc Zyngier <maz@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ Documentation/arch/arm64/silicon-errata.rst |    4 ++++
+ arch/arm64/kvm/vgic/vgic-v3.c               |    8 +++++++-
+ 2 files changed, 11 insertions(+), 1 deletion(-)
+
+--- a/Documentation/arch/arm64/silicon-errata.rst
++++ b/Documentation/arch/arm64/silicon-errata.rst
+@@ -55,10 +55,14 @@ stable kernels.
+ +----------------+-----------------+-----------------+-----------------------------+
+ | Ampere         | AmpereOne       | AC03_CPU_38     | AMPERE_ERRATUM_AC03_CPU_38  |
+ +----------------+-----------------+-----------------+-----------------------------+
++| Ampere         | AmpereOne       | AC03_CPU_57     | N/A                         |
+++----------------+-----------------+-----------------+-----------------------------+
+ | Ampere         | AmpereOne AC04  | AC04_CPU_10     | AMPERE_ERRATUM_AC03_CPU_38  |
+ +----------------+-----------------+-----------------+-----------------------------+
+ | Ampere         | AmpereOne AC04  | AC04_CPU_23     | AMPERE_ERRATUM_AC04_CPU_23  |
+ +----------------+-----------------+-----------------+-----------------------------+
++| Ampere         | AmpereOne AC04  | AC04_CPU_29     | N/A                         |
+++----------------+-----------------+-----------------+-----------------------------+
+ +----------------+-----------------+-----------------+-----------------------------+
+ | ARM            | Cortex-A510     | #2457168        | ARM64_ERRATUM_2457168       |
+ +----------------+-----------------+-----------------+-----------------------------+
+--- a/arch/arm64/kvm/vgic/vgic-v3.c
++++ b/arch/arm64/kvm/vgic/vgic-v3.c
+@@ -275,7 +275,13 @@ void vgic_v3_deactivate(struct kvm_vcpu
+               lr = vgic_v3_compute_lr(vcpu, irq) & ~ICH_LR_ACTIVE_BIT;
+       }
+ 
+-      if (lr & ICH_LR_HW)
++      /*
++       * In the nested state, the irq has already been deactivated via the HW
++       * bit in the LR. Deactivating again would be harmless except AmpereOne
++       * errata AC03_CPU_57, AC04_CPU_29 could cause irq delivery to break if
++       * the deactivation hits the highest priority pending irq.
++       */
++      if ((lr & ICH_LR_HW) && !vgic_state_is_nested(vcpu))
+               vgic_v3_deactivate_phys(FIELD_GET(ICH_LR_PHYS_ID_MASK, lr));
+ 
+       vgic_v3_fold_lr(vcpu, lr);

diff --git a/queue-7.1/series b/queue-7.1/series
index 2c17f6cba6c8bbae3408eae72dd94a5fce535d85..09f543485f5d1547a50a527a7e3427ecaac28da3 100644 (file)
--- a/queue-7.1/series
+++ b/queue-7.1/series
@@ -4,6 +4,7 @@ lib-alloc_tag-introduce-mem_alloc_profiling_permanen.patch
 mm-slab-prevent-unbounded-recursion-in-free-path-wit.patch
 alsa-hda-realtek-add-quirk-for-hp-dragonfly-folio-g3.patch
 thunderbolt-prevent-xdomain-delayed-work-use-after-f.patch
+kvm-arm64-vgic-avoid-double-deactivate-of-irqs-in-the-nested-context.patch
 dmaengine-switchtec-dma-fix-field_get-misuse-when-pr.patch
 pinctrl-qcom-unconditionally-mark-gpio-as-wakeup-ena.patch
 pinctrl-qcom-sc8280xp-add-missing-wakeup-entries-for.patch