Merge tag 'renesas-clk-for-v7.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel...

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add Ethernet, GPIO, CPU core, watchdog, serial, I2C, sound, and SPI
   clocks and resets on Renesas RZ/G3L
 - Add the timer (MTU3) clock on Renesas RZ/T2H and RZ/N2H
 - Add Coresight trace clocks on Renesas R-Mobile A1 and APE6
 - Add display clocks and resets on Renesas RZ/G3E

* tag 'renesas-clk-for-v7.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (29 commits)
  clk: renesas: r8a73a4: Add ZT/ZTR trace clocks
  dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile APE6
  clk: renesas: r9a08g046: Add RSPI clocks and resets
  clk: renesas: r9a08g046: Add SSIF-2 clocks and resets
  clk: renesas: r9a08g046: Add RSCI clocks and resets
  clk: renesas: cpg-mssr: Add number of clock cells check
  clk: renesas: rzg2l: Refactor rzg3l_cpg_pll_clk_endisable()
  clk: renesas: rzg2l: Consolidate DEF_MUX() and DEF_MUX_FLAGS()
  clk: renesas: r9a08g046: Add IA55_PCLK to critical module clocks
  clk: renesas: r9a09g047: Add support for LCDC{0,1} clocks and resets
  clk: renesas: r9a09g047: Add support for DSI clocks and resets
  clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLK
  clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocks
  clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_DIV7 clocks
  clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1} clocks
  clk: renesas: r9a09g047: Add CLK_PLLETH_LPCLK support
  clk: renesas: rzv2h: Add PLLDSI clk mux support
  clk: renesas: r8a7740: Add ZT/ZTR trace clocks
  dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile A1
  clk: renesas: r9a09g077: Add MTU3 module clock
  ...