dmaengine: dw-edma: Add Xilinx CPM6-DMA DeviceID

Add Device ID for AMD (Xilinx) CPM6 DMA IP. This IP enables
64 Read and 64 Write Channels.

Adding the relevant dw_edma_pcie_data to use 8 Read and 8 Write
channels for initial commit.

Signed-off-by: Devendra K Verma <devendra.verma@amd.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260605112829.679697-1-devendra.verma@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
index 0b30ce138503613624c2fd8d1e84d9902675fe3f..2082d0021a8d91ef6baedb746ec5b32d3897cd1d 100644 (file)
--- a/drivers/dma/dw-edma/dw-edma-pcie.c
+++ b/drivers/dma/dw-edma/dw-edma-pcie.c
@@ -27,6 +27,7 @@
 
 /* AMD MDB (Xilinx) specific defines */
 #define PCI_DEVICE_ID_XILINX_B054              0xb054
+#define PCI_DEVICE_ID_XILINX_B00F              0xb00f
 
 #define DW_PCIE_XILINX_MDB_VSEC_DMA_ID         0x6
 #define DW_PCIE_XILINX_MDB_VSEC_ID             0x20
@@ -125,6 +126,19 @@ static const struct dw_edma_pcie_data xilinx_mdb_data = {
        .rd_ch_cnt                      = 8,
 };
 
+static const struct dw_edma_pcie_data xilinx_cpm6_dma_data = {
+       /* MDB registers location */
+       .rg.bar                         = BAR_0,
+       .rg.off                         = SZ_4K,        /*  4 Kbytes */
+       .rg.sz                          = SZ_8K,        /*  8 Kbytes */
+
+       /* Other */
+       .mf                             = EDMA_MF_HDMA_NATIVE,
+       .irqs                           = 1,
+       .wr_ch_cnt                      = 8,
+       .rd_ch_cnt                      = 8,
+};
+
 static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data *pdata,
                                           enum pci_barno bar, off_t start_off,
                                           off_t ll_off_gap, size_t ll_size,
@@ -547,6 +561,8 @@ static const struct pci_device_id dw_edma_pcie_id_table[] = {
        { PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) },
        { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_XILINX_B054),
          (kernel_ulong_t)&xilinx_mdb_data },
+       { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_XILINX_B00F),
+         .driver_data = (kernel_ulong_t)&xilinx_cpm6_dma_data },
        { }
 };
 MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table);