In DMA mode, transfer lists are currently completed only when the final
transfer in the list completes. If an earlier transfer fails, the list is
left incomplete and callers wait until timeout.
There is no need to wait for a timeout, as the completion path in
i3c_hci_process_xfer() already checks for error status. Complete the
transfer list as soon as any transfer in the list reports an error.
This avoids unnecessary delays and spurious timeouts on error.
Complete a transfer list completion immediately there is an error.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260603090754.16252-8-adrian.hunter@intel.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
struct hci_xfer *xfer = xfer_list + i;
u32 *ring_data = rh->xfer + rh->xfer_struct_sz * enqueue_ptr;
+ xfer->final_xfer = xfer_list + n - 1;
+
/* store cmd descriptor */
*ring_data++ = xfer->cmd_desc[0];
*ring_data++ = xfer->cmd_desc[1];
tid, xfer->cmd_tid);
/* TODO: do something about it? */
}
- if (xfer->completion)
- complete(xfer->completion);
+ if (xfer == xfer->final_xfer || RESP_STATUS(resp))
+ complete(xfer->final_xfer->completion);
if (RESP_STATUS(resp))
hci->enqueue_blocked = true;
}
struct {
/* DMA specific */
struct i3c_dma *dma;
+ struct hci_xfer *final_xfer;
int ring_number;
int ring_entry;
};