]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/amdgpu: add support for GC IP version 11.7.0
authorGranthali Vinodkumar Dhandar <granthali.vinodkumardhandar@amd.com>
Wed, 17 Jun 2026 12:09:58 +0000 (17:39 +0530)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Jul 2026 17:01:42 +0000 (13:01 -0400)
Initialize GC IP 11_7_0

Signed-off-by: Granthali Vinodkumar Dhandar <granthali.vinodkumardhandar@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit cf591e67c095542a16475df293ec7bc9a118e4ee)

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
drivers/gpu/drm/amd/amdgpu/soc21.c
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
drivers/gpu/drm/amd/amdkfd/kfd_device.c

index be5069642a9076bb067dd051d66e1030d463f160..3b93c264c60e5dd3ee81e234d5bdd215fdac4597 100644 (file)
@@ -2119,6 +2119,7 @@ static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 3):
        case IP_VERSION(11, 5, 4):
        case IP_VERSION(11, 5, 6):
+       case IP_VERSION(11, 7, 0):
                amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);
                break;
        case IP_VERSION(12, 0, 0):
@@ -2180,6 +2181,7 @@ static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 3):
        case IP_VERSION(11, 5, 4):
        case IP_VERSION(11, 5, 6):
+       case IP_VERSION(11, 7, 0):
                amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);
                break;
        case IP_VERSION(12, 0, 0):
@@ -2506,6 +2508,7 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 3):
        case IP_VERSION(11, 5, 4):
        case IP_VERSION(11, 5, 6):
+       case IP_VERSION(11, 7, 0):
                amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);
                break;
        case IP_VERSION(12, 0, 0):
@@ -2719,6 +2722,7 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 3):
        case IP_VERSION(11, 5, 4):
        case IP_VERSION(11, 5, 6):
+       case IP_VERSION(11, 7, 0):
                amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);
                adev->enable_mes = true;
                adev->enable_mes_kiq = true;
@@ -3127,6 +3131,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 3):
        case IP_VERSION(11, 5, 4):
        case IP_VERSION(11, 5, 6):
+       case IP_VERSION(11, 7, 0):
                adev->family = AMDGPU_FAMILY_GC_11_5_0;
                break;
        case IP_VERSION(12, 0, 0):
@@ -3156,6 +3161,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 3):
        case IP_VERSION(11, 5, 4):
        case IP_VERSION(11, 5, 6):
+       case IP_VERSION(11, 7, 0):
                adev->flags |= AMD_IS_APU;
                break;
        default:
index 5f7745143f5664050fd3271d4f37e1681f194d48..d4ca889be416d2c0347cfa7c85667e8e25a6b0b5 100644 (file)
@@ -977,6 +977,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 3):
        case IP_VERSION(11, 5, 4):
        case IP_VERSION(11, 5, 6):
+       case IP_VERSION(11, 7, 0):
                /* Don't enable it by default yet.
                 */
                if (amdgpu_tmz < 1) {
index e60ae566b5f80167f7295f24f829988c66c436d8..6004750cd9b0a21eced2a0f59144b768af4f19bd 100644 (file)
@@ -133,6 +133,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_6_pfp.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_6_me.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mec.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_6_rlc.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_7_0_pfp.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_7_0_me.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_7_0_mec.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_7_0_rlc.bin");
 
 static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = {
        SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
@@ -1128,6 +1132,7 @@ static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 3):
        case IP_VERSION(11, 5, 4):
        case IP_VERSION(11, 5, 6):
+       case IP_VERSION(11, 7, 0):
                adev->gfx.config.max_hw_contexts = 8;
                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -1612,6 +1617,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
        case IP_VERSION(11, 5, 3):
        case IP_VERSION(11, 5, 4):
        case IP_VERSION(11, 5, 6):
+       case IP_VERSION(11, 7, 0):
                adev->gfx.me.num_me = 1;
                adev->gfx.me.num_pipe_per_me = 1;
                adev->gfx.me.num_queue_per_pipe = 2;
@@ -3085,7 +3091,8 @@ static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
                    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2) ||
                    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 3) ||
                    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 4) ||
-                   amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 6))
+                   amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 6) ||
+                   amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 7, 0))
                        bootload_status = RREG32_SOC15(GC, 0,
                                        regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);
                else
@@ -5758,6 +5765,7 @@ static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)
                case IP_VERSION(11, 5, 3):
                case IP_VERSION(11, 5, 4):
                case IP_VERSION(11, 5, 6):
+               case IP_VERSION(11, 7, 0):
                        WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);
                        break;
                default:
@@ -5798,6 +5806,7 @@ static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
        case IP_VERSION(11, 5, 3):
        case IP_VERSION(11, 5, 4):
        case IP_VERSION(11, 5, 6):
+       case IP_VERSION(11, 7, 0):
                if (!enable)
                        amdgpu_gfx_off_ctrl(adev, false);
 
@@ -5834,6 +5843,7 @@ static int gfx_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
        case IP_VERSION(11, 5, 3):
        case IP_VERSION(11, 5, 4):
        case IP_VERSION(11, 5, 6):
+       case IP_VERSION(11, 7, 0):
                gfx_v11_0_update_gfx_clock_gating(adev,
                                state ==  AMD_CG_STATE_GATE);
                break;
index 8eb9847d9e1e059ed5f5e2d75adf814af00f2219..8a0a88551461cfa22106c76eff3033e82224b885 100644 (file)
@@ -606,6 +606,7 @@ static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 3):
        case IP_VERSION(11, 5, 4):
        case IP_VERSION(11, 5, 6):
+       case IP_VERSION(11, 7, 0):
                adev->gfxhub.funcs = &gfxhub_v11_5_0_funcs;
                break;
        default:
@@ -781,6 +782,7 @@ static int gmc_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
        case IP_VERSION(11, 5, 3):
        case IP_VERSION(11, 5, 4):
        case IP_VERSION(11, 5, 6):
+       case IP_VERSION(11, 7, 0):
                set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
                set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
                /*
index f5927c3553ce8cee0118b3f4cd64fd992f8a555e..177d702e612a9601e24d8224a1c6e3975841ee0e 100644 (file)
@@ -43,6 +43,7 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_2_imu.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_3_imu.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_4_imu.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_6_imu.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_7_0_imu.bin");
 
 static int imu_v11_0_init_microcode(struct amdgpu_device *adev)
 {
index 4d133c481b2610d55b4ec10c5b453e728a5aa3f7..3ca2ee3e9202990a69fc24175cf61ae85cd2f649 100644 (file)
@@ -60,6 +60,8 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes_2.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes1.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes_2.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes1.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes_2.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes1.bin");
 
 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block);
 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block);
index 963659deeaffe9c3a04086944f39fe3dc6dc92c1..9b9b13e327d80fbf79a3143e55e24f826846f826 100644 (file)
@@ -838,6 +838,34 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block)
                adev->pg_flags = 0;
                adev->external_rev_id = adev->rev_id + 0xd0;
                break;
+       case IP_VERSION(11, 7, 0):
+               adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
+                       AMD_CG_SUPPORT_JPEG_MGCG |
+                       AMD_CG_SUPPORT_GFX_CGCG |
+                       AMD_CG_SUPPORT_GFX_CGLS |
+                       AMD_CG_SUPPORT_GFX_MGCG |
+                       AMD_CG_SUPPORT_GFX_FGCG |
+                       AMD_CG_SUPPORT_REPEATER_FGCG |
+                       AMD_CG_SUPPORT_GFX_PERF_CLK |
+                       AMD_CG_SUPPORT_GFX_3D_CGCG |
+                       AMD_CG_SUPPORT_GFX_3D_CGLS |
+                       AMD_CG_SUPPORT_MC_MGCG |
+                       AMD_CG_SUPPORT_MC_LS |
+                       AMD_CG_SUPPORT_HDP_LS |
+                       AMD_CG_SUPPORT_HDP_DS |
+                       AMD_CG_SUPPORT_HDP_SD |
+                       AMD_CG_SUPPORT_ATHUB_MGCG |
+                       AMD_CG_SUPPORT_ATHUB_LS |
+                       AMD_CG_SUPPORT_IH_CG |
+                       AMD_CG_SUPPORT_BIF_MGCG |
+                       AMD_CG_SUPPORT_BIF_LS;
+               adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
+                       AMD_PG_SUPPORT_VCN |
+                       AMD_PG_SUPPORT_JPEG_DPG |
+                       AMD_PG_SUPPORT_JPEG |
+                       AMD_PG_SUPPORT_GFX_PG;
+               adev->external_rev_id = adev->rev_id + 0xF;
+               break;
        default:
                /* FIXME: not supported yet */
                return -EINVAL;
index f28259d138182469fc1b2ecab443018808658139..a6a7888c7a8d6923d9a3622428695dba1fbcbea0 100644 (file)
@@ -1715,6 +1715,7 @@ int kfd_get_gpu_cache_info(struct kfd_node *kdev, struct kfd_gpu_cache_info **pc
                case IP_VERSION(11, 5, 3):
                case IP_VERSION(11, 5, 4):
                case IP_VERSION(11, 5, 6):
+               case IP_VERSION(11, 7, 0):
                        /* Cacheline size not available in IP discovery for gc11.
                         * kfd_fill_gpu_cache_info_from_gfx_config to hard code it
                         */
index 5eb863dec8f4d6975ffe3429a6831d19c6299b76..47de7702c39e476795fc5e74387e171efd0daeca 100644 (file)
@@ -169,6 +169,7 @@ static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd)
        case IP_VERSION(11, 5, 3):
        case IP_VERSION(11, 5, 4):
        case IP_VERSION(11, 5, 6):
+       case IP_VERSION(11, 7, 0):
                kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
                break;
        case IP_VERSION(12, 0, 0):
@@ -451,6 +452,10 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
                         gfx_target_version = 110504;
                         f2g = &gfx_v11_kfd2kgd;
                         break;
+               case IP_VERSION(11, 7, 0):
+                       gfx_target_version = 110700;
+                       f2g = &gfx_v11_kfd2kgd;
+                       break;
                case IP_VERSION(12, 0, 0):
                        gfx_target_version = 120000;
                        f2g = &gfx_v12_kfd2kgd;