From: Mikhail Kshevetskiy Date: Sun, 9 Aug 2026 18:39:30 +0000 (+0300) Subject: uboot-airoha: update an7583 patches X-Git-Url: http://git.ipfire.org/index.cgi?a=commitdiff_plain;ds=inline;p=thirdparty%2Fopenwrt.git uboot-airoha: update an7583 patches The same patches were submitted to upstream U-Boot. Signed-off-by: Mikhail Kshevetskiy Link: https://github.com/openwrt/openwrt/pull/24646 Signed-off-by: Robert Marko --- diff --git a/package/boot/uboot-airoha/patches/300-airoha-add-support-for-Airoha-AN7583-SoC.patch b/package/boot/uboot-airoha/patches/300-airoha-add-support-for-Airoha-AN7583-SoC.patch index 43b7651b9c0..40d041b4b17 100644 --- a/package/boot/uboot-airoha/patches/300-airoha-add-support-for-Airoha-AN7583-SoC.patch +++ b/package/boot/uboot-airoha/patches/300-airoha-add-support-for-Airoha-AN7583-SoC.patch @@ -1,7 +1,7 @@ -From 8f8f6a330755301d247768af13cb53c5c325579c Mon Sep 17 00:00:00 2001 +From 05ecfc09cfcc4b3562ea7ed1d21a654d27f21610 Mon Sep 17 00:00:00 2001 From: Christian Marangi -Date: Tue, 29 Apr 2025 13:06:59 +0200 -Subject: [PATCH 12/29] airoha: add support for Airoha AN7583 SoC +Date: Fri, 31 Jul 2026 08:54:15 +0200 +Subject: [PATCH 01/16] airoha: add support for Airoha AN7583 SoC Add support for Airoha AN7583 SoC. This adds the Kconfig and Makefile entry for the SoC, DTSI and initial config for it. Also add the code for @@ -15,13 +15,13 @@ Signed-off-by: Christian Marangi arch/arm/mach-airoha/Kconfig | 14 + arch/arm/mach-airoha/Makefile | 1 + arch/arm/mach-airoha/an7583/Makefile | 3 + - arch/arm/mach-airoha/an7583/init.c | 47 ++++ + arch/arm/mach-airoha/an7583/init.c | 66 +++++ board/airoha/an7583/MAINTAINERS | 5 + board/airoha/an7583/Makefile | 3 + board/airoha/an7583/an7583_rfb.c | 16 ++ configs/an7583_evb_defconfig | 79 ++++++ include/configs/an7583.h | 19 ++ - 11 files changed, 641 insertions(+) + 11 files changed, 660 insertions(+) create mode 100644 arch/arm/dts/an7583-evb.dts create mode 100644 arch/arm/dts/an7583.dtsi create mode 100644 arch/arm/mach-airoha/an7583/Makefile @@ -107,7 +107,7 @@ index 00000000000..d02cd194e8a +}; diff --git a/arch/arm/dts/an7583.dtsi b/arch/arm/dts/an7583.dtsi new file mode 100644 -index 00000000000..e1fda15ba37 +index 00000000000..9362d2fbedf --- /dev/null +++ b/arch/arm/dts/an7583.dtsi @@ -0,0 +1,387 @@ @@ -556,17 +556,22 @@ index 00000000000..886ab7e4eb9 +obj-y += init.o diff --git a/arch/arm/mach-airoha/an7583/init.c b/arch/arm/mach-airoha/an7583/init.c new file mode 100644 -index 00000000000..77c29290331 +index 00000000000..4cf7f8caf85 --- /dev/null +++ b/arch/arm/mach-airoha/an7583/init.c -@@ -0,0 +1,47 @@ +@@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include ++#include ++#include +#include ++#include +#include + ++DECLARE_GLOBAL_DATA_PTR; ++ +int print_cpuinfo(void) +{ + printf("CPU: Airoha AN7583\n"); @@ -580,30 +585,44 @@ index 00000000000..77c29290331 + +int dram_init_banksize(void) +{ -+ return fdtdec_setup_memory_banksize(); ++ gd->bd->bi_dram[0].start = gd->ram_base; ++ gd->bd->bi_dram[0].size = get_effective_memsize(); ++ ++ if (gd->ram_size > SZ_2G) { ++ gd->bd->bi_dram[1].start = gd->ram_base + SZ_2G; ++ gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; ++ } ++ ++ return 0; +} + -+void reset_cpu(ulong addr) ++void reset_cpu(void) +{ + psci_system_reset(); +} + +static struct mm_region an7583_mem_map[] = { + { -+ /* DDR */ ++ /* DDR, 32-bit area */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, -+ .size = 0x80000000UL, ++ .size = SZ_2G, ++ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, ++ }, { ++ /* DDR, 64-bit area */ ++ .virt = 0x100000000UL, ++ .phys = 0x100000000UL, ++ .size = SZ_4G + SZ_2G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, -+ .size = 0x20000000UL, ++ .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { -+ 0, ++ /* List terminator */ + } +}; +struct mm_region *mem_map = an7583_mem_map; diff --git a/package/boot/uboot-airoha/patches/301-arm-an7583-sync-init-code-with-an7581.patch b/package/boot/uboot-airoha/patches/301-arm-an7583-sync-init-code-with-an7581.patch deleted file mode 100644 index 32142b9988e..00000000000 --- a/package/boot/uboot-airoha/patches/301-arm-an7583-sync-init-code-with-an7581.patch +++ /dev/null @@ -1,83 +0,0 @@ -From c1a853581a4045c0ce9c51d038981c459e02a32d Mon Sep 17 00:00:00 2001 -From: Mikhail Kshevetskiy -Date: Fri, 17 Oct 2025 02:53:28 +0300 -Subject: [PATCH 13/29] arm/an7583: sync init code with an7581 - -Signed-off-by: Mikhail Kshevetskiy ---- - arch/arm/mach-airoha/an7583/init.c | 31 ++++++++++++++++++++++++------ - 1 file changed, 25 insertions(+), 6 deletions(-) - -diff --git a/arch/arm/mach-airoha/an7583/init.c b/arch/arm/mach-airoha/an7583/init.c -index 77c29290331..4cf7f8caf85 100644 ---- a/arch/arm/mach-airoha/an7583/init.c -+++ b/arch/arm/mach-airoha/an7583/init.c -@@ -2,9 +2,14 @@ - - #include - #include -+#include -+#include - #include -+#include - #include - -+DECLARE_GLOBAL_DATA_PTR; -+ - int print_cpuinfo(void) - { - printf("CPU: Airoha AN7583\n"); -@@ -18,30 +23,44 @@ int dram_init(void) - - int dram_init_banksize(void) - { -- return fdtdec_setup_memory_banksize(); -+ gd->bd->bi_dram[0].start = gd->ram_base; -+ gd->bd->bi_dram[0].size = get_effective_memsize(); -+ -+ if (gd->ram_size > SZ_2G) { -+ gd->bd->bi_dram[1].start = gd->ram_base + SZ_2G; -+ gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; -+ } -+ -+ return 0; - } - --void reset_cpu(ulong addr) -+void reset_cpu(void) - { - psci_system_reset(); - } - - static struct mm_region an7583_mem_map[] = { - { -- /* DDR */ -+ /* DDR, 32-bit area */ - .virt = 0x80000000UL, - .phys = 0x80000000UL, -- .size = 0x80000000UL, -+ .size = SZ_2G, -+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, -+ }, { -+ /* DDR, 64-bit area */ -+ .virt = 0x100000000UL, -+ .phys = 0x100000000UL, -+ .size = SZ_4G + SZ_2G, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, -- .size = 0x20000000UL, -+ .size = 0x40000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { -- 0, -+ /* List terminator */ - } - }; - struct mm_region *mem_map = an7583_mem_map; --- -2.53.0 - diff --git a/package/boot/uboot-airoha/patches/307-net-airoha-add-support-for-Airoha-AN7583.patch b/package/boot/uboot-airoha/patches/307-net-airoha-add-support-for-Airoha-AN7583.patch index fcc5618e72e..9df883033ac 100644 --- a/package/boot/uboot-airoha/patches/307-net-airoha-add-support-for-Airoha-AN7583.patch +++ b/package/boot/uboot-airoha/patches/307-net-airoha-add-support-for-Airoha-AN7583.patch @@ -1,7 +1,7 @@ -From 8e7a468d4e3e55d64cbfe5576092f7ecb3eaa0f1 Mon Sep 17 00:00:00 2001 +From 720a8ca371c304149db44467bf38d5daba78c41c Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 19 May 2025 14:29:53 +0200 -Subject: [PATCH 18/29] net: airoha: add support for Airoha AN7583 +Subject: [PATCH 06/16] net: airoha: add support for Airoha AN7583 Add support for Ethernet controller present in Airoha AN7583. This follow the same implementation of Airoha AN7581 with the only difference @@ -16,11 +16,11 @@ enable BMCR_PDOWN by default and tweak to GEPHY_CONN_CFG is also needed. Signed-off-by: Christian Marangi --- - drivers/net/airoha_eth.c | 91 ++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 91 insertions(+) + drivers/net/airoha_eth.c | 94 ++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 94 insertions(+) diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c -index e5d39b95cc5..863c35647b6 100644 +index e5d39b95cc5..d552b9e9de9 100644 --- a/drivers/net/airoha_eth.c +++ b/drivers/net/airoha_eth.c @@ -24,6 +24,7 @@ @@ -89,7 +89,16 @@ index e5d39b95cc5..863c35647b6 100644 static inline dma_addr_t dma_map_unaligned(void *vaddr, size_t len, enum dma_data_direction dir) -@@ -809,6 +838,59 @@ static int airoha_switch_init(struct udevice *dev, struct airoha_eth *eth) +@@ -438,6 +467,8 @@ static int airoha_get_fe_port(struct airoha_gdm_port *port) + case 0x7523: + /* FIXME: GDM1 is the only supported port */ + return FE_PSE_PORT_GDM1; ++ case 0x7583: ++ return port->id == 3 ? FE_PSE_PORT_GDM3 : port->id; + case 0x7581: + default: + return port->id == 4 ? FE_PSE_PORT_GDM4 : port->id; +@@ -809,6 +840,59 @@ static int airoha_switch_init(struct udevice *dev, struct airoha_eth *eth) FIELD_PREP(SWITCH_PHY_END_ADDR, 0xc) | FIELD_PREP(SWITCH_PHY_ST_ADDR, 0x8)); @@ -149,11 +158,12 @@ index e5d39b95cc5..863c35647b6 100644 return 0; } -@@ -1269,6 +1351,12 @@ static const struct airoha_eth_soc_data en7581_data = { +@@ -1269,6 +1353,13 @@ static const struct airoha_eth_soc_data en7581_data = { .switch_compatible = "airoha,en7581-switch", }; +static const struct airoha_eth_soc_data an7583_data = { ++ .version = 0x7583, + .xsi_rsts_names = an7583_xsi_rsts_names, + .num_xsi_rsts = ARRAY_SIZE(an7583_xsi_rsts_names), + .switch_compatible = "airoha,an7583-switch", @@ -162,7 +172,7 @@ index e5d39b95cc5..863c35647b6 100644 static const struct udevice_id airoha_eth_ids[] = { { .compatible = "airoha,en7523-eth", .data = (ulong)&en7523_data, -@@ -1276,6 +1364,9 @@ static const struct udevice_id airoha_eth_ids[] = { +@@ -1276,6 +1367,9 @@ static const struct udevice_id airoha_eth_ids[] = { { .compatible = "airoha,en7581-eth", .data = (ulong)&en7581_data, }, diff --git a/package/boot/uboot-airoha/patches/520-net-airoha-add-support-for-Airoha-AN7583-PCS-driver.patch b/package/boot/uboot-airoha/patches/520-net-airoha-add-support-for-Airoha-AN7583-PCS-driver.patch index 68a6f1c9866..6d8bd0c6a3e 100644 --- a/package/boot/uboot-airoha/patches/520-net-airoha-add-support-for-Airoha-AN7583-PCS-driver.patch +++ b/package/boot/uboot-airoha/patches/520-net-airoha-add-support-for-Airoha-AN7583-PCS-driver.patch @@ -1,7 +1,7 @@ -From 900bbfbb0abbe89abf156dc4b48dc19b929c8a13 Mon Sep 17 00:00:00 2001 +From e6fc9fe766c716511afefbb14f1ae13f6ad702de Mon Sep 17 00:00:00 2001 From: Christian Marangi -Date: Tue, 30 Sep 2025 22:56:29 +0200 -Subject: [PATCH 27/38] net: airoha: add support for Airoha AN7583 PCS driver +Date: Fri, 31 Jul 2026 09:10:40 +0200 +Subject: [PATCH 11/16] net: airoha: add support for Airoha AN7583 PCS driver Add support for the PCS interface on Airoha AN7583 SoC. This is based on the AN7581 SoC with difference in the calibration and Analog PHY @@ -13,8 +13,8 @@ Signed-off-by: Christian Marangi drivers/net/airoha/Makefile | 1 + drivers/net/airoha/pcs-airoha-common.c | 27 + drivers/net/airoha/pcs-airoha.h | 17 + - drivers/net/airoha/pcs-an7583.c | 2200 ++++++++++++++++++++++++ - 5 files changed, 2253 insertions(+) + drivers/net/airoha/pcs-an7583.c | 2202 ++++++++++++++++++++++++ + 5 files changed, 2255 insertions(+) create mode 100644 drivers/net/airoha/pcs-an7583.c diff --git a/drivers/net/airoha/Kconfig b/drivers/net/airoha/Kconfig @@ -126,10 +126,10 @@ index 714d2ebe520..fddeda5ca36 100644 +#endif diff --git a/drivers/net/airoha/pcs-an7583.c b/drivers/net/airoha/pcs-an7583.c new file mode 100644 -index 00000000000..0a5b936cd93 +index 00000000000..4bdda3066ed --- /dev/null +++ b/drivers/net/airoha/pcs-an7583.c -@@ -0,0 +1,2200 @@ +@@ -0,0 +1,2202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 AIROHA Inc @@ -361,21 +361,23 @@ index 00000000000..0a5b936cd93 + FIELD_PREP(AIROHA_PCS_PMA_TX_BEN_EXTEN_FTUNE, tx_ben_exten_ftune)); + + if (data->port_type == AIROHA_PCS_PON) { -+ if (interface == PHY_INTERFACE_MODE_SGMII || interface == PHY_INTERFACE_MODE_1000BASEX || -+ interface == PHY_INTERFACE_MODE_USXGMII || interface == PHY_INTERFACE_MODE_10GBASER) ++ if (interface == PHY_INTERFACE_MODE_SGMII || ++ interface == PHY_INTERFACE_MODE_1000BASEX || ++ interface == PHY_INTERFACE_MODE_USXGMII || ++ interface == PHY_INTERFACE_MODE_10GBASER) + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_TX_DLY_CTRL, -+ AIROHA_PCS_PMA_TX_DLY_BEN_FTUNE | -+ AIROHA_PCS_PMA_TX_DLY_DATA_FTUNE, -+ FIELD_PREP(AIROHA_PCS_PMA_TX_DLY_BEN_FTUNE, tx_dly_ben_ftune) | -+ FIELD_PREP(AIROHA_PCS_PMA_TX_DLY_DATA_FTUNE, tx_dly_data_ftune)); ++ AIROHA_PCS_PMA_TX_DLY_BEN_FTUNE | ++ AIROHA_PCS_PMA_TX_DLY_DATA_FTUNE, ++ FIELD_PREP(AIROHA_PCS_PMA_TX_DLY_BEN_FTUNE, tx_dly_ben_ftune) | ++ FIELD_PREP(AIROHA_PCS_PMA_TX_DLY_DATA_FTUNE, tx_dly_data_ftune)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_MD32_MEM_CLK_CTRL, -+ AIROHA_PCS_PMA_MD32PM_CK_SEL, -+ FIELD_PREP(AIROHA_PCS_PMA_MD32PM_CK_SEL, 0x3)); ++ AIROHA_PCS_PMA_MD32PM_CK_SEL, ++ FIELD_PREP(AIROHA_PCS_PMA_MD32PM_CK_SEL, 0x3)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_TX_DLY_CTRL, -+ AIROHA_PCS_PMA_OUTBEN_DATA_MODE, -+ FIELD_PREP(AIROHA_PCS_PMA_OUTBEN_DATA_MODE, 0x1)); ++ AIROHA_PCS_PMA_OUTBEN_DATA_MODE, ++ FIELD_PREP(AIROHA_PCS_PMA_OUTBEN_DATA_MODE, 0x1)); + } +} + @@ -1979,7 +1981,7 @@ index 00000000000..0a5b936cd93 + feos = eo_buf[FEOS]; + + for (i = 0; i < ARRAY_SIZE(eo_buf); i++) { -+ if ((eo_buf[i] == feos) && (eo_buf[i] >= 32)) ++ if (eo_buf[i] == feos && eo_buf[i] >= 32) + eo_buf[i] = eo_buf[i] - 64; + else if (eo_buf[i] >= 64) + eo_buf[i] = eo_buf[i] - 128; @@ -1997,7 +1999,7 @@ index 00000000000..0a5b936cd93 + udelay(500); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_0, -+ AIROHA_PCS_PMA_FORCE_DA_XPON_CDR_LPF_RSTB); ++ AIROHA_PCS_PMA_FORCE_DA_XPON_CDR_LPF_RSTB); + + udelay(500); + } @@ -2077,7 +2079,6 @@ index 00000000000..0a5b936cd93 +static void an7583_pcs_common_phya_eo_scan(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ -+ + u32 best_heo = 0, best_veo = 0; + u32 leq_gain, best_leq_gain; + u32 best_leq_peacking = 0; @@ -2124,9 +2125,11 @@ index 00000000000..0a5b936cd93 + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, leq_gain)); + -+ for (leq_peaking = 0; leq_peaking <= FIELD_MAX(AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL); leq_peaking++) { ++ for (leq_peaking = 0; ++ leq_peaking <= FIELD_MAX(AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL); ++ leq_peaking++) { + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN, -+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL | ++ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL | + AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, leq_peaking)); @@ -2171,7 +2174,6 @@ index 00000000000..0a5b936cd93 +static void an7583_pcs_common_phya_rxrdy(struct airoha_pcs_priv *priv) +{ + u32 xfi_rx_term_sel = 0x1; -+ // int efuse_valid; + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1, + AIROHA_PCS_PMA_FORCE_RX_RDY); @@ -2328,7 +2330,7 @@ index 00000000000..0a5b936cd93 + AIROHA_PCS_PMA_DISB_RX_RDY); + + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1, -+ AIROHA_PCS_PMA_DISB_RX_RDY); ++ AIROHA_PCS_PMA_DISB_RX_RDY); +} -- 2.53.0