From: Sasha Levin Date: Wed, 5 Aug 2026 16:36:05 +0000 (-0400) Subject: Fixes for all trees X-Git-Url: http://git.ipfire.org/index.cgi?a=commitdiff_plain;ds=sidebyside;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for all trees Signed-off-by: Sasha Levin --- diff --git a/queue-6.12/drm-xe-apply-whitelist-to-engine-save-restore.patch b/queue-6.12/drm-xe-apply-whitelist-to-engine-save-restore.patch new file mode 100644 index 0000000000..f3cc3311ab --- /dev/null +++ b/queue-6.12/drm-xe-apply-whitelist-to-engine-save-restore.patch @@ -0,0 +1,220 @@ +From 18791079c3ab3aec150c56995fc5bc76e4c77a0a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:49:06 -0700 +Subject: drm/xe: Apply whitelist to engine save-restore + +From: Lucas De Marchi + +[ Upstream commit 3fcf68d7393fd622b96cd45124ccb1eddf77684c ] + +Changes in xe_guc_ads.c in the above commit are not needed for linux-6.12.y. + +Instead of handling the whitelist directly in the GuC ADS +initialization, make it follow the same logic as other engine registers +that are save-restored. Main benefit is that then the SW tracking then +shows it in debugfs and there's no risk of an engine workaround to write +to the same nopriv register that is being passed directly to GuC. + +This means that xe_reg_whitelist_process_engine() only has to process +the RTP and convert them to entries for the hwe. With that all the +registers should be covered by xe_reg_sr_apply_mmio() to write to the HW +and there's no special handling in GuC ADS to also add these registers +to the list of registers that is passed to GuC. + +Example for DG2: + + # cat /sys/kernel/debug/dri/0000\:03\:00.0/gt0/register-save-restore + ... + Engine + rcs0 + ... + REG[0x24d0] clr=0xffffffff set=0x1000dafc masked=no mcr=no + REG[0x24d4] clr=0xffffffff set=0x1000db01 masked=no mcr=no + REG[0x24d8] clr=0xffffffff set=0x0000db1c masked=no mcr=no + ... + Whitelist + rcs0 + REG[0xdafc-0xdaff]: allow read access + REG[0xdb00-0xdb1f]: allow read access + REG[0xdb1c-0xdb1f]: allow rw access + +v2: + - Use ~0u for clr bits so it's just a write (Matt Roper) + - Simplify helpers now that unused slots are not written + +Reviewed-by: Matt Roper +Link: https://patchwork.freedesktop.org/patch/msgid/20241209232739.147417-6-lucas.demarchi@intel.com +Signed-off-by: Lucas De Marchi +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_gt.c | 4 +- + drivers/gpu/drm/xe/xe_hw_engine.c | 1 - + drivers/gpu/drm/xe/xe_reg_sr.c | 53 --------------------------- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 37 +++++++++++++++++++ + 4 files changed, 38 insertions(+), 57 deletions(-) + +diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c +index 292947e44a8a8..e2ac1589dfbf6 100644 +--- a/drivers/gpu/drm/xe/xe_gt.c ++++ b/drivers/gpu/drm/xe/xe_gt.c +@@ -722,10 +722,8 @@ static int do_gt_restart(struct xe_gt *gt) + + xe_mocs_init(gt); + +- for_each_hw_engine(hwe, gt, id) { ++ for_each_hw_engine(hwe, gt, id) + xe_reg_sr_apply_mmio(&hwe->reg_sr, gt); +- xe_reg_sr_apply_whitelist(hwe); +- } + + /* Get CCS mode in sync between sw/hw */ + xe_gt_apply_ccs_mode(gt); +diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c +index 45d0ae074e652..ca4c2dee276bc 100644 +--- a/drivers/gpu/drm/xe/xe_hw_engine.c ++++ b/drivers/gpu/drm/xe/xe_hw_engine.c +@@ -546,7 +546,6 @@ static int hw_engine_init(struct xe_gt *gt, struct xe_hw_engine *hwe, + xe_gt_assert(gt, gt->info.engine_mask & BIT(id)); + + xe_reg_sr_apply_mmio(&hwe->reg_sr, gt); +- xe_reg_sr_apply_whitelist(hwe); + + hwe->hwsp = xe_managed_bo_create_pin_map(xe, tile, SZ_4K, + XE_BO_FLAG_VRAM_IF_DGFX(tile) | +diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c +index ae9e6df2f4e12..01ee54d53531b 100644 +--- a/drivers/gpu/drm/xe/xe_reg_sr.c ++++ b/drivers/gpu/drm/xe/xe_reg_sr.c +@@ -24,7 +24,6 @@ + #include "xe_hw_engine_types.h" + #include "xe_macros.h" + #include "xe_mmio.h" +-#include "xe_reg_whitelist.h" + #include "xe_rtp_types.h" + + static void reg_sr_fini(struct drm_device *drm, void *arg) +@@ -194,58 +193,6 @@ void xe_reg_sr_apply_mmio(struct xe_reg_sr *sr, struct xe_gt *gt) + xe_gt_err(gt, "Failed to apply, err=%d\n", err); + } + +-void xe_reg_sr_apply_whitelist(struct xe_hw_engine *hwe) +-{ +- struct xe_reg_sr *sr = &hwe->reg_whitelist; +- struct xe_gt *gt = hwe->gt; +- struct xe_device *xe = gt_to_xe(gt); +- struct xe_reg_sr_entry *entry; +- struct drm_printer p; +- u32 mmio_base = hwe->mmio_base; +- unsigned long reg; +- unsigned int slot = 0; +- int err; +- +- if (xa_empty(&sr->xa)) +- return; +- +- drm_dbg(&xe->drm, "Whitelisting %s registers\n", sr->name); +- +- err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); +- if (err) +- goto err_force_wake; +- +- p = drm_dbg_printer(&xe->drm, DRM_UT_DRIVER, NULL); +- xa_for_each(&sr->xa, reg, entry) { +- if (slot == RING_MAX_NONPRIV_SLOTS) { +- xe_gt_err(gt, +- "hwe %s: maximum register whitelist slots (%d) reached, refusing to add more\n", +- hwe->name, RING_MAX_NONPRIV_SLOTS); +- break; +- } +- +- xe_reg_whitelist_print_entry(&p, 0, reg, entry); +- xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot), +- reg | entry->set_bits); +- slot++; +- } +- +- /* And clear the rest just in case of garbage */ +- for (; slot < RING_MAX_NONPRIV_SLOTS; slot++) { +- u32 addr = RING_NOPID(mmio_base).addr; +- +- xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot), addr); +- } +- +- err = xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); +- XE_WARN_ON(err); +- +- return; +- +-err_force_wake: +- drm_err(&xe->drm, "Failed to apply, err=%d\n", err); +-} +- + /** + * xe_reg_sr_dump - print all save/restore entries + * @sr: Save/restore entries +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index d88261921ae46..ef1bb1b47af09 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -10,7 +10,9 @@ + #include "regs/xe_oa_regs.h" + #include "regs/xe_regs.h" + #include "xe_gt_types.h" ++#include "xe_gt_printk.h" + #include "xe_platform_types.h" ++#include "xe_reg_sr.h" + #include "xe_rtp.h" + #include "xe_step.h" + +@@ -86,6 +88,40 @@ static const struct xe_rtp_entry_sr register_whitelist[] = { + {} + }; + ++static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe) ++{ ++ struct xe_reg_sr *sr = &hwe->reg_whitelist; ++ struct xe_reg_sr_entry *entry; ++ struct drm_printer p; ++ unsigned long reg; ++ unsigned int slot; ++ ++ xe_gt_dbg(hwe->gt, "Add %s whitelist to engine\n", sr->name); ++ p = xe_gt_dbg_printer(hwe->gt); ++ ++ slot = 0; ++ xa_for_each(&sr->xa, reg, entry) { ++ struct xe_reg_sr_entry hwe_entry = { ++ .reg = RING_FORCE_TO_NONPRIV(hwe->mmio_base, slot), ++ .set_bits = entry->reg.addr | entry->set_bits, ++ .clr_bits = ~0u, ++ .read_mask = entry->read_mask, ++ }; ++ ++ if (slot == RING_MAX_NONPRIV_SLOTS) { ++ xe_gt_err(hwe->gt, ++ "hwe %s: maximum register whitelist slots (%d) reached, refusing to add more\n", ++ hwe->name, RING_MAX_NONPRIV_SLOTS); ++ break; ++ } ++ ++ xe_reg_whitelist_print_entry(&p, 0, reg, entry); ++ xe_reg_sr_add(&hwe->reg_sr, &hwe_entry, hwe->gt); ++ ++ slot++; ++ } ++} ++ + /** + * xe_reg_whitelist_process_engine - process table of registers to whitelist + * @hwe: engine instance to process whitelist for +@@ -99,6 +135,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); + + xe_rtp_process_to_sr(&ctx, register_whitelist, &hwe->reg_whitelist); ++ whitelist_apply_to_hwe(hwe); + } + + /** +-- +2.53.0 + diff --git a/queue-6.12/drm-xe-introduce-xe_gt_dbg_printer.patch b/queue-6.12/drm-xe-introduce-xe_gt_dbg_printer.patch new file mode 100644 index 0000000000..354af16365 --- /dev/null +++ b/queue-6.12/drm-xe-introduce-xe_gt_dbg_printer.patch @@ -0,0 +1,72 @@ +From ddfe1b390b3cf858b25aabe1513378f2511b45be Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:49:05 -0700 +Subject: drm/xe: Introduce xe_gt_dbg_printer() + +From: Michal Wajdeczko + +[ Upstream commit 26582fc61a923e81832df8d5a169bbdab095d15e ] + +We didn't have GT-oriented debug level printer as it was hard to +correctly show actual callsite annotation. But this is now doable +from commit c2ef66e9ad88 ("drm/print: Improve drm_dbg_printer"). + +Signed-off-by: Michal Wajdeczko +Reviewed-by: Lucas De Marchi +Link: https://patchwork.freedesktop.org/patch/msgid/20241209232739.147417-3-lucas.demarchi@intel.com +Signed-off-by: Lucas De Marchi +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_gt_printk.h | 31 +++++++++++++++++++++++++++++++ + 1 file changed, 31 insertions(+) + +diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h +index 5dc71394372d6..11da0228cea71 100644 +--- a/drivers/gpu/drm/xe/xe_gt_printk.h ++++ b/drivers/gpu/drm/xe/xe_gt_printk.h +@@ -60,6 +60,21 @@ static inline void __xe_gt_printfn_info(struct drm_printer *p, struct va_format + xe_gt_info(gt, "%pV", vaf); + } + ++static inline void __xe_gt_printfn_dbg(struct drm_printer *p, struct va_format *vaf) ++{ ++ struct xe_gt *gt = p->arg; ++ struct drm_printer dbg; ++ ++ /* ++ * The original xe_gt_dbg() callsite annotations are useless here, ++ * redirect to the tweaked drm_dbg_printer() instead. ++ */ ++ dbg = drm_dbg_printer(>_to_xe(gt)->drm, DRM_UT_DRIVER, NULL); ++ dbg.origin = p->origin; ++ ++ drm_printf(&dbg, "GT%u: %pV", gt->info.id, vaf); ++} ++ + /** + * xe_gt_err_printer - Construct a &drm_printer that outputs to xe_gt_err() + * @gt: the &xe_gt pointer to use in xe_gt_err() +@@ -90,4 +105,20 @@ static inline struct drm_printer xe_gt_info_printer(struct xe_gt *gt) + return p; + } + ++/** ++ * xe_gt_dbg_printer - Construct a &drm_printer that outputs like xe_gt_dbg() ++ * @gt: the &xe_gt pointer to use in xe_gt_dbg() ++ * ++ * Return: The &drm_printer object. ++ */ ++static inline struct drm_printer xe_gt_dbg_printer(struct xe_gt *gt) ++{ ++ struct drm_printer p = { ++ .printfn = __xe_gt_printfn_dbg, ++ .arg = gt, ++ .origin = (const void *)_THIS_IP_, ++ }; ++ return p; ++} ++ + #endif +-- +2.53.0 + diff --git a/queue-6.12/drm-xe-oa-de-whitelist-oa-registers-on-oa-stream-ope.patch b/queue-6.12/drm-xe-oa-de-whitelist-oa-registers-on-oa-stream-ope.patch new file mode 100644 index 0000000000..ae5d83b25e --- /dev/null +++ b/queue-6.12/drm-xe-oa-de-whitelist-oa-registers-on-oa-stream-ope.patch @@ -0,0 +1,60 @@ +From 3cc9d90e3b44f2588eb566f891b0a800b17b3899 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:49:14 -0700 +Subject: drm/xe/oa: (De-)whitelist OA registers on OA stream open/release + +From: Ashutosh Dixit + +[ Upstream commit 63ddb3ad08ff4e89c108499dfec5e9be5ddc25c9 ] + +Whitelist OA registers on stream open and de-whitelist on stream +close/release. Whitelisting is only done when 'stream->sample' is +true. 'stream->sample' is only true when (a) xe_observation_paranoid is set +to false by system admin, or (b) the process is perfmon_capable(). This +therefore enforces the OA register whitelisting security requirements. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-9-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_oa.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c +index 5e38afc46e20e..476d887749a9b 100644 +--- a/drivers/gpu/drm/xe/xe_oa.c ++++ b/drivers/gpu/drm/xe/xe_oa.c +@@ -34,6 +34,7 @@ + #include "xe_oa.h" + #include "xe_observation.h" + #include "xe_pm.h" ++#include "xe_reg_whitelist.h" + #include "xe_sched_job.h" + #include "xe_sriov.h" + #include "xe_sync.h" +@@ -836,6 +837,9 @@ static void xe_oa_stream_destroy(struct xe_oa_stream *stream) + + mutex_destroy(&stream->stream_lock); + ++ if (stream->sample) ++ xe_reg_dewhitelist_oa_regs(stream->gt); ++ + xe_oa_disable_metric_set(stream); + xe_exec_queue_put(stream->k_exec_q); + +@@ -1868,6 +1872,9 @@ static int xe_oa_stream_open_ioctl_locked(struct xe_oa *oa, + goto err_disable; + } + ++ if (stream->sample) ++ xe_reg_whitelist_oa_regs(stream->gt); ++ + /* Hold a reference on the drm device till stream_fd is released */ + drm_dev_get(&stream->oa->xe->drm); + +-- +2.53.0 + diff --git a/queue-6.12/drm-xe-rtp-add-ring_force_to_nonpriv_deny-to-oa-whit.patch b/queue-6.12/drm-xe-rtp-add-ring_force_to_nonpriv_deny-to-oa-whit.patch new file mode 100644 index 0000000000..e28da383a0 --- /dev/null +++ b/queue-6.12/drm-xe-rtp-add-ring_force_to_nonpriv_deny-to-oa-whit.patch @@ -0,0 +1,48 @@ +From 7f74d75788e4d77d31dfd7ee208ac97f6384f5f6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:49:07 -0700 +Subject: drm/xe/rtp: Add RING_FORCE_TO_NONPRIV_DENY to OA whitelists + +From: Ashutosh Dixit + +[ Upstream commit e70086a3a06d276b4a5d9a2c51c9330c6cf72780 ] + +Unconditionally whitelisting OA registers is a security violation. Set +RING_FORCE_TO_NONPRIV_DENY bit in OA nonpriv slots, so that OA registers +don't get whitelisted by default after probe, gt reset, resume and engine +reset. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Suggested-by: Umesh Nerlige Ramappa +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-2-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index ef1bb1b47af09..d75bc87cb3cb1 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -67,10 +67,12 @@ static const struct xe_rtp_entry_sr register_whitelist[] = { + XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0)) + }, + ++#define WHITELIST_DENY(r, f) WHITELIST(r, (f) | RING_FORCE_TO_NONPRIV_DENY) ++ + #define WHITELIST_OA_MMIO_TRG(trg, status, head) \ +- WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \ +- WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD), \ +- WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4) ++ WHITELIST_DENY(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \ ++ WHITELIST_DENY(status, RING_FORCE_TO_NONPRIV_ACCESS_RD), \ ++ WHITELIST_DENY(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4) + + #define WHITELIST_OAG_MMIO_TRG \ + WHITELIST_OA_MMIO_TRG(OAG_MMIOTRIGGER, OAG_OASTATUS, OAG_OAHEADPTR) +-- +2.53.0 + diff --git a/queue-6.12/drm-xe-rtp-de-whitelist-oa-registers-for-all-hwe-s-f.patch b/queue-6.12/drm-xe-rtp-de-whitelist-oa-registers-for-all-hwe-s-f.patch new file mode 100644 index 0000000000..28d18432bc --- /dev/null +++ b/queue-6.12/drm-xe-rtp-de-whitelist-oa-registers-for-all-hwe-s-f.patch @@ -0,0 +1,107 @@ +From 4e2b7cea823c557471345ecd20d0fa61bc63a6a1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:49:13 -0700 +Subject: drm/xe/rtp: (De-)whitelist OA registers for all hwe's for a gt + +From: Ashutosh Dixit + +[ Upstream commit ebba7ce65252a4ab0e3794ff14854df2afca5c08 ] + +Whitelist or de-whitelist OA registers for all hwe's on the gt on which the +OA stream is opened. This simplifies the case where an oa unit has 0 +attached hwe's (but which monitors OA events on the associated GT). + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-8-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 34 +++++++++++++++++++++++++-- + drivers/gpu/drm/xe/xe_reg_whitelist.h | 4 ++++ + 2 files changed, 36 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index 39f577a0cac71..8a1c3f3c82973 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -9,7 +9,7 @@ + #include "regs/xe_gt_regs.h" + #include "regs/xe_oa_regs.h" + #include "regs/xe_regs.h" +-#include "xe_gt_types.h" ++#include "xe_gt.h" + #include "xe_gt_printk.h" + #include "xe_platform_types.h" + #include "xe_reg_sr.h" +@@ -162,7 +162,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, first_oa_slot); + } + +-__maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist) ++static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist) + { + struct xe_reg_sr_entry *entry; + unsigned long reg; +@@ -177,6 +177,36 @@ __maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool wh + xe_reg_sr_apply_mmio(&hwe->oa_sr, hwe->gt); + } + ++/** ++ * xe_reg_whitelist_oa_regs - whitelist oa registers for gt ++ * @gt: gt to whitelist oa registers for ++ * ++ * Whitelist OA registers by resetting RING_FORCE_TO_NONPRIV_DENY ++ */ ++void xe_reg_whitelist_oa_regs(struct xe_gt *gt) ++{ ++ struct xe_hw_engine *hwe; ++ enum xe_hw_engine_id id; ++ ++ for_each_hw_engine(hwe, gt, id) ++ __whitelist_oa_regs(hwe, true); ++} ++ ++/** ++ * xe_reg_dewhitelist_oa_regs - dewhitelist oa registers for gt ++ * @gt: gt to dewhitelist oa registers for ++ * ++ * Dewhitelist OA registers by setting RING_FORCE_TO_NONPRIV_DENY ++ */ ++void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt) ++{ ++ struct xe_hw_engine *hwe; ++ enum xe_hw_engine_id id; ++ ++ for_each_hw_engine(hwe, gt, id) ++ __whitelist_oa_regs(hwe, false); ++} ++ + /** + * xe_reg_whitelist_print_entry - print one whitelist entry + * @p: DRM printer +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.h b/drivers/gpu/drm/xe/xe_reg_whitelist.h +index 69b121d377da0..f243b6ac60b7e 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.h ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.h +@@ -9,12 +9,16 @@ + #include + + struct drm_printer; ++struct xe_gt; + struct xe_hw_engine; + struct xe_reg_sr; + struct xe_reg_sr_entry; + + void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe); + ++void xe_reg_whitelist_oa_regs(struct xe_gt *gt); ++void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt); ++ + void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent, + u32 reg, struct xe_reg_sr_entry *entry); + +-- +2.53.0 + diff --git a/queue-6.12/drm-xe-rtp-ensure-locking-ref-counting-for-oa-whitel.patch b/queue-6.12/drm-xe-rtp-ensure-locking-ref-counting-for-oa-whitel.patch new file mode 100644 index 0000000000..482ae93c78 --- /dev/null +++ b/queue-6.12/drm-xe-rtp-ensure-locking-ref-counting-for-oa-whitel.patch @@ -0,0 +1,77 @@ +From 71f8b5b1801dfdcb6757187fff9afd5650644382 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:49:15 -0700 +Subject: drm/xe/rtp: Ensure locking/ref counting for OA whitelists + +From: Ashutosh Dixit + +[ Upstream commit ef78e2a22f72c892fd6663f0760abd208d49a3e2 ] + +Since multiple OA streams might be open in parallel on a gt, ensure that +proper locking is in place. Also ensure that OA registers are whitelisted +when the first OA stream is open and de-whitelisted after the last OA +stream is closed. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-10-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_oa_types.h | 3 +++ + drivers/gpu/drm/xe/xe_reg_whitelist.c | 10 ++++++++++ + 2 files changed, 13 insertions(+) + +diff --git a/drivers/gpu/drm/xe/xe_oa_types.h b/drivers/gpu/drm/xe/xe_oa_types.h +index fea9d981e414f..0faec73954b70 100644 +--- a/drivers/gpu/drm/xe/xe_oa_types.h ++++ b/drivers/gpu/drm/xe/xe_oa_types.h +@@ -120,6 +120,9 @@ struct xe_oa_gt { + + /** @oa_unit: array of oa_units */ + struct xe_oa_unit *oa_unit; ++ ++ /** @whitelist_count: number of open streams for which oa registers are whitelisted */ ++ u32 whitelist_count; + }; + + /** +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index 8a1c3f3c82973..4b70460d6e002 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -9,6 +9,7 @@ + #include "regs/xe_gt_regs.h" + #include "regs/xe_oa_regs.h" + #include "regs/xe_regs.h" ++#include "xe_assert.h" + #include "xe_gt.h" + #include "xe_gt_printk.h" + #include "xe_platform_types.h" +@@ -188,6 +189,10 @@ void xe_reg_whitelist_oa_regs(struct xe_gt *gt) + struct xe_hw_engine *hwe; + enum xe_hw_engine_id id; + ++ lockdep_assert_held(>->oa.gt_lock); ++ if (gt->oa.whitelist_count++) ++ return; ++ + for_each_hw_engine(hwe, gt, id) + __whitelist_oa_regs(hwe, true); + } +@@ -203,6 +208,11 @@ void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt) + struct xe_hw_engine *hwe; + enum xe_hw_engine_id id; + ++ lockdep_assert_held(>->oa.gt_lock); ++ xe_assert(gt_to_xe(gt), gt->oa.whitelist_count); ++ if (--gt->oa.whitelist_count) ++ return; ++ + for_each_hw_engine(hwe, gt, id) + __whitelist_oa_regs(hwe, false); + } +-- +2.53.0 + diff --git a/queue-6.12/drm-xe-rtp-generalize-whitelist_apply_to_hwe.patch b/queue-6.12/drm-xe-rtp-generalize-whitelist_apply_to_hwe.patch new file mode 100644 index 0000000000..2cbb7ab880 --- /dev/null +++ b/queue-6.12/drm-xe-rtp-generalize-whitelist_apply_to_hwe.patch @@ -0,0 +1,69 @@ +From da8796d04bc15212ad31b0a82683210eb944cef4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:49:10 -0700 +Subject: drm/xe/rtp: Generalize whitelist_apply_to_hwe + +From: Ashutosh Dixit + +[ Upstream commit 4fe2844b0f0c7cdc45ca4c4c62ca56b7f26c514c ] + +Generalize whitelist_apply_to_hwe to construct both non-OA and OA +whitelist nonpriv registers. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-5-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index 12d12d8f0e99c..47beb473f6a29 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -94,9 +94,10 @@ static const struct xe_rtp_entry_sr oa_whitelist[] = { + {} + }; + +-static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe) ++static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe, struct xe_reg_sr *in, ++ struct xe_reg_sr *out, int first_slot) + { +- struct xe_reg_sr *sr = &hwe->reg_whitelist; ++ struct xe_reg_sr *sr = in; + struct xe_reg_sr_entry *entry; + struct drm_printer p; + unsigned long reg; +@@ -105,7 +106,7 @@ static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe) + xe_gt_dbg(hwe->gt, "Add %s whitelist to engine\n", sr->name); + p = xe_gt_dbg_printer(hwe->gt); + +- slot = 0; ++ slot = first_slot; + xa_for_each(&sr->xa, reg, entry) { + struct xe_reg_sr_entry hwe_entry = { + .reg = RING_FORCE_TO_NONPRIV(hwe->mmio_base, slot), +@@ -122,7 +123,7 @@ static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe) + } + + xe_reg_whitelist_print_entry(&p, 0, reg, entry); +- xe_reg_sr_add(&hwe->reg_sr, &hwe_entry, hwe->gt); ++ xe_reg_sr_add(out, &hwe_entry, hwe->gt); + + slot++; + } +@@ -144,7 +145,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + int first_oa_slot; + + xe_rtp_process_to_sr(&ctx, register_whitelist, &hwe->reg_whitelist); +- first_oa_slot = whitelist_apply_to_hwe(hwe); ++ first_oa_slot = whitelist_apply_to_hwe(hwe, &hwe->reg_whitelist, &hwe->reg_sr, 0); + + xe_rtp_process_to_sr(&ctx, oa_whitelist, &hwe->oa_whitelist); + } +-- +2.53.0 + diff --git a/queue-6.12/drm-xe-rtp-keep-track-of-non-oa-nonpriv-slots.patch b/queue-6.12/drm-xe-rtp-keep-track-of-non-oa-nonpriv-slots.patch new file mode 100644 index 0000000000..48e9eae3f8 --- /dev/null +++ b/queue-6.12/drm-xe-rtp-keep-track-of-non-oa-nonpriv-slots.patch @@ -0,0 +1,60 @@ +From c5230087a9c8a2262ac1d4118fdedd73d1b8f6b1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:49:09 -0700 +Subject: drm/xe/rtp: Keep track of non-OA nonpriv slots + +From: Ashutosh Dixit + +[ Upstream commit 60d49ea28bb190a640bd8dc3f4c946e0811a948c ] + +In order to dynamically whitelist/dewhitelist OA registers on OA stream +open/close, we need to keep track of nonpriv slots occupied by non-OA +register whitelists. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-4-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index d82b14f8d0716..12d12d8f0e99c 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -94,7 +94,7 @@ static const struct xe_rtp_entry_sr oa_whitelist[] = { + {} + }; + +-static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe) ++static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe) + { + struct xe_reg_sr *sr = &hwe->reg_whitelist; + struct xe_reg_sr_entry *entry; +@@ -126,6 +126,8 @@ static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe) + + slot++; + } ++ ++ return slot; + } + + /** +@@ -139,9 +141,10 @@ static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe) + void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + { + struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); ++ int first_oa_slot; + + xe_rtp_process_to_sr(&ctx, register_whitelist, &hwe->reg_whitelist); +- whitelist_apply_to_hwe(hwe); ++ first_oa_slot = whitelist_apply_to_hwe(hwe); + + xe_rtp_process_to_sr(&ctx, oa_whitelist, &hwe->oa_whitelist); + } +-- +2.53.0 + diff --git a/queue-6.12/drm-xe-rtp-maintain-oa-whitelists-separately.patch b/queue-6.12/drm-xe-rtp-maintain-oa-whitelists-separately.patch new file mode 100644 index 0000000000..95aac4375f --- /dev/null +++ b/queue-6.12/drm-xe-rtp-maintain-oa-whitelists-separately.patch @@ -0,0 +1,104 @@ +From 5e237a1b6544b0a3823186eb441f1303ad17982b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:49:08 -0700 +Subject: drm/xe/rtp: Maintain OA whitelists separately + +From: Ashutosh Dixit + +[ Upstream commit 31e2437561621b4867c08efc890bf629d017df03 ] + +Contains minor modification of the above commit because of changed API. + +OA registers are dynamically whitelisted (and again dewhitelisted) on OA +stream open/close. Maintaining OA whitelists separately from non-OA +register whitlists simplifies this management of OA register +whitelisting/dewhitelisting. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-3-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_gt_debugfs.c | 4 +++- + drivers/gpu/drm/xe/xe_hw_engine.c | 2 ++ + drivers/gpu/drm/xe/xe_hw_engine_types.h | 8 ++++++++ + drivers/gpu/drm/xe/xe_reg_whitelist.c | 6 ++++++ + 4 files changed, 19 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c +index 8f95d3a5949bc..15ff52dfe461b 100644 +--- a/drivers/gpu/drm/xe/xe_gt_debugfs.c ++++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c +@@ -191,8 +191,10 @@ static int register_save_restore(struct xe_gt *gt, struct drm_printer *p) + drm_printf(p, "\n"); + + drm_printf(p, "Whitelist\n"); +- for_each_hw_engine(hwe, gt, id) ++ for_each_hw_engine(hwe, gt, id) { + xe_reg_whitelist_dump(&hwe->reg_whitelist, p); ++ xe_reg_whitelist_dump(&hwe->oa_whitelist, p); ++ } + + xe_pm_runtime_put(gt_to_xe(gt)); + +diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c +index ca4c2dee276bc..9f560ac9e2b8a 100644 +--- a/drivers/gpu/drm/xe/xe_hw_engine.c ++++ b/drivers/gpu/drm/xe/xe_hw_engine.c +@@ -532,6 +532,8 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe, + hw_engine_setup_default_state(hwe); + + xe_reg_sr_init(&hwe->reg_whitelist, hwe->name, gt_to_xe(gt)); ++ xe_reg_sr_init(&hwe->oa_whitelist, hwe->name, gt_to_xe(gt)); ++ xe_reg_sr_init(&hwe->oa_sr, hwe->name, gt_to_xe(gt)); + xe_reg_whitelist_process_engine(hwe); + } + +diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h +index 8be6d420ece40..ac876a8c3eec3 100644 +--- a/drivers/gpu/drm/xe/xe_hw_engine_types.h ++++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h +@@ -128,6 +128,14 @@ struct xe_hw_engine { + * @reg_whitelist: table with registers to be whitelisted + */ + struct xe_reg_sr reg_whitelist; ++ /** ++ * @oa_whitelist: oa registers to be whitelisted ++ */ ++ struct xe_reg_sr oa_whitelist; ++ /** ++ * @oa_sr: oa nonpriv whitelist registers, changed on oa stream open/close ++ */ ++ struct xe_reg_sr oa_sr; + /** + * @reg_lrc: LRC workaround registers + */ +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index d75bc87cb3cb1..d82b14f8d0716 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -66,6 +66,10 @@ static const struct xe_rtp_entry_sr register_whitelist[] = { + ENGINE_CLASS(RENDER)), + XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0)) + }, ++ {} ++}; ++ ++static const struct xe_rtp_entry_sr oa_whitelist[] = { + + #define WHITELIST_DENY(r, f) WHITELIST(r, (f) | RING_FORCE_TO_NONPRIV_DENY) + +@@ -138,6 +142,8 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + + xe_rtp_process_to_sr(&ctx, register_whitelist, &hwe->reg_whitelist); + whitelist_apply_to_hwe(hwe); ++ ++ xe_rtp_process_to_sr(&ctx, oa_whitelist, &hwe->oa_whitelist); + } + + /** +-- +2.53.0 + diff --git a/queue-6.12/drm-xe-rtp-refactor-oag-mmio-trigger-register-whitel.patch b/queue-6.12/drm-xe-rtp-refactor-oag-mmio-trigger-register-whitel.patch new file mode 100644 index 0000000000..912730981c --- /dev/null +++ b/queue-6.12/drm-xe-rtp-refactor-oag-mmio-trigger-register-whitel.patch @@ -0,0 +1,68 @@ +From 20ea558b10466dcd4649667a75b569726683cccb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:49:04 -0700 +Subject: drm/xe/rtp: Refactor OAG MMIO trigger register whitelisting + +From: Ashutosh Dixit + +[ Upstream commit ed455775c5a68b75e5f6ad6c8e0e3e9c98fd3f64 ] + +Minor refactor of OAG MMIO trigger register whitelisting for code reuse +with OAM MMIO trigger register whitelisting. + +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20251202025115.373546-5-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 29 ++++++++++++--------------- + 1 file changed, 13 insertions(+), 16 deletions(-) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index 3de0a867149da..d88261921ae46 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -64,27 +64,24 @@ static const struct xe_rtp_entry_sr register_whitelist[] = { + ENGINE_CLASS(RENDER)), + XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0)) + }, +- { XE_RTP_NAME("oa_reg_render"), ++ ++#define WHITELIST_OA_MMIO_TRG(trg, status, head) \ ++ WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \ ++ WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD), \ ++ WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4) ++ ++#define WHITELIST_OAG_MMIO_TRG \ ++ WHITELIST_OA_MMIO_TRG(OAG_MMIOTRIGGER, OAG_OASTATUS, OAG_OAHEADPTR) ++ ++ { XE_RTP_NAME("oag_mmio_trg_rcs"), + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED), + ENGINE_CLASS(RENDER)), +- XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER, +- RING_FORCE_TO_NONPRIV_ACCESS_RW), +- WHITELIST(OAG_OASTATUS, +- RING_FORCE_TO_NONPRIV_ACCESS_RD), +- WHITELIST(OAG_OAHEADPTR, +- RING_FORCE_TO_NONPRIV_ACCESS_RD | +- RING_FORCE_TO_NONPRIV_RANGE_4)) ++ XE_RTP_ACTIONS(WHITELIST_OAG_MMIO_TRG) + }, +- { XE_RTP_NAME("oa_reg_compute"), ++ { XE_RTP_NAME("oag_mmio_trg_ccs"), + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED), + ENGINE_CLASS(COMPUTE)), +- XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER, +- RING_FORCE_TO_NONPRIV_ACCESS_RW), +- WHITELIST(OAG_OASTATUS, +- RING_FORCE_TO_NONPRIV_ACCESS_RD), +- WHITELIST(OAG_OAHEADPTR, +- RING_FORCE_TO_NONPRIV_ACCESS_RD | +- RING_FORCE_TO_NONPRIV_RANGE_4)) ++ XE_RTP_ACTIONS(WHITELIST_OAG_MMIO_TRG) + }, + {} + }; +-- +2.53.0 + diff --git a/queue-6.12/drm-xe-rtp-save-oa-nonpriv-registers-to-register-sav.patch b/queue-6.12/drm-xe-rtp-save-oa-nonpriv-registers-to-register-sav.patch new file mode 100644 index 0000000000..d1d1b8d434 --- /dev/null +++ b/queue-6.12/drm-xe-rtp-save-oa-nonpriv-registers-to-register-sav.patch @@ -0,0 +1,57 @@ +From 97603052631f2ba38287e448166f2167b5fea7fa Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:49:11 -0700 +Subject: drm/xe/rtp: Save OA nonpriv registers to register save/restore lists + +From: Ashutosh Dixit + +[ Upstream commit a19a83721a28ccaddace846da70da5c53d7dd052 ] + +Now we can save OA whitelisting nonpriv registers to register save/restore +lists. OA nonpriv registers are saved to both hwe->oa_sr as well as +hwe->reg_sr. + +During probe, resume and gt-reset flows KMD will apply hwe->reg_sr, +ensuring OA registers are de-whitelisted after these events. For +engine-reset, hwe->reg_sr is registered with GuC and GuC will apply these +registers, ensuring OA registers are de-whitelisted after engine resets. + +hwe->oa_sr is used for whitelisting or de-whitelisting OA registers during +OA operation, by toggling the 'deny' bit on oa stream open/close. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-6-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index 47beb473f6a29..a3a45f470faa1 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -148,6 +148,18 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + first_oa_slot = whitelist_apply_to_hwe(hwe, &hwe->reg_whitelist, &hwe->reg_sr, 0); + + xe_rtp_process_to_sr(&ctx, oa_whitelist, &hwe->oa_whitelist); ++ ++ /* ++ * Save oa nonpriv registers to hwe->oa_sr, from which oa registers are whitelisted ++ * or de-whitelisted, by toggling the 'deny' bit on oa stream open/close ++ */ ++ whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->oa_sr, first_oa_slot); ++ ++ /* ++ * Also save oa nonpriv registers to hwe->reg_sr, to ensure oa registers are not ++ * whitelisted by default after probe, gt reset, resume and engine reset ++ */ ++ whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, first_oa_slot); + } + + /** +-- +2.53.0 + diff --git a/queue-6.12/drm-xe-rtp-toggle-deny-bit-to-de-whitelist-oa-regs.patch b/queue-6.12/drm-xe-rtp-toggle-deny-bit-to-de-whitelist-oa-regs.patch new file mode 100644 index 0000000000..c586eb494b --- /dev/null +++ b/queue-6.12/drm-xe-rtp-toggle-deny-bit-to-de-whitelist-oa-regs.patch @@ -0,0 +1,51 @@ +From 57c48e0bb22755c95e9e4c0d183923c8b6a6c891 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:49:12 -0700 +Subject: drm/xe/rtp: Toggle 'deny' bit to (de-)whitelist OA regs + +From: Ashutosh Dixit + +[ Upstream commit b422babd77fac2c96b92db484050e460899bddaf ] + +Whitelist or de-whitelist OA registers by setting or resetting the 'deny' +bit in OA nonpriv registers and writing new register values to HW. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-7-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index a3a45f470faa1..39f577a0cac71 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -162,6 +162,21 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, first_oa_slot); + } + ++__maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist) ++{ ++ struct xe_reg_sr_entry *entry; ++ unsigned long reg; ++ ++ xa_for_each(&hwe->oa_sr.xa, reg, entry) { ++ if (whitelist) ++ entry->set_bits &= ~RING_FORCE_TO_NONPRIV_DENY; ++ else ++ entry->set_bits |= RING_FORCE_TO_NONPRIV_DENY; ++ } ++ ++ xe_reg_sr_apply_mmio(&hwe->oa_sr, hwe->gt); ++} ++ + /** + * xe_reg_whitelist_print_entry - print one whitelist entry + * @p: DRM printer +-- +2.53.0 + diff --git a/queue-6.12/series b/queue-6.12/series index db833ae5d3..84862f6fdb 100644 --- a/queue-6.12/series +++ b/queue-6.12/series @@ -271,3 +271,15 @@ ata-libahci_platform-do-not-set-mask_port_map-when-not-needed.patch ata-ahci-make-ahci_ignore_port-handle-empty-mask_port_map.patch of-reserved_mem-avoid-post-init-uaf-when-alloc_reserved_mem_array-fails.patch bluetooth-iso-fix-connected-closed-transition-on-shutdown-release.patch +drm-xe-rtp-refactor-oag-mmio-trigger-register-whitel.patch +drm-xe-introduce-xe_gt_dbg_printer.patch +drm-xe-apply-whitelist-to-engine-save-restore.patch +drm-xe-rtp-add-ring_force_to_nonpriv_deny-to-oa-whit.patch +drm-xe-rtp-maintain-oa-whitelists-separately.patch +drm-xe-rtp-keep-track-of-non-oa-nonpriv-slots.patch +drm-xe-rtp-generalize-whitelist_apply_to_hwe.patch +drm-xe-rtp-save-oa-nonpriv-registers-to-register-sav.patch +drm-xe-rtp-toggle-deny-bit-to-de-whitelist-oa-regs.patch +drm-xe-rtp-de-whitelist-oa-registers-for-all-hwe-s-f.patch +drm-xe-oa-de-whitelist-oa-registers-on-oa-stream-ope.patch +drm-xe-rtp-ensure-locking-ref-counting-for-oa-whitel.patch diff --git a/queue-6.18/drm-xe-oa-de-whitelist-oa-registers-on-oa-stream-ope.patch b/queue-6.18/drm-xe-oa-de-whitelist-oa-registers-on-oa-stream-ope.patch new file mode 100644 index 0000000000..ca5ae632ee --- /dev/null +++ b/queue-6.18/drm-xe-oa-de-whitelist-oa-registers-on-oa-stream-ope.patch @@ -0,0 +1,60 @@ +From 65b2369946ba4d9fccfa3ccb1f944b6e937feecf Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:46:13 -0700 +Subject: drm/xe/oa: (De-)whitelist OA registers on OA stream open/release + +From: Ashutosh Dixit + +[ Upstream commit 63ddb3ad08ff4e89c108499dfec5e9be5ddc25c9 ] + +Whitelist OA registers on stream open and de-whitelist on stream +close/release. Whitelisting is only done when 'stream->sample' is +true. 'stream->sample' is only true when (a) xe_observation_paranoid is set +to false by system admin, or (b) the process is perfmon_capable(). This +therefore enforces the OA register whitelisting security requirements. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-9-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_oa.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c +index 7d04591e297a8..98df9ee1cac39 100644 +--- a/drivers/gpu/drm/xe/xe_oa.c ++++ b/drivers/gpu/drm/xe/xe_oa.c +@@ -35,6 +35,7 @@ + #include "xe_oa.h" + #include "xe_observation.h" + #include "xe_pm.h" ++#include "xe_reg_whitelist.h" + #include "xe_sched_job.h" + #include "xe_sriov.h" + #include "xe_sync.h" +@@ -863,6 +864,9 @@ static void xe_oa_stream_destroy(struct xe_oa_stream *stream) + + mutex_destroy(&stream->stream_lock); + ++ if (stream->sample) ++ xe_reg_dewhitelist_oa_regs(stream->gt); ++ + xe_oa_disable_metric_set(stream); + xe_exec_queue_put(stream->k_exec_q); + +@@ -1887,6 +1891,9 @@ static int xe_oa_stream_open_ioctl_locked(struct xe_oa *oa, + goto err_disable; + } + ++ if (stream->sample) ++ xe_reg_whitelist_oa_regs(stream->gt); ++ + /* Hold a reference on the drm device till stream_fd is released */ + drm_dev_get(&stream->oa->xe->drm); + +-- +2.53.0 + diff --git a/queue-6.18/drm-xe-rtp-add-ring_force_to_nonpriv_deny-to-oa-whit.patch b/queue-6.18/drm-xe-rtp-add-ring_force_to_nonpriv_deny-to-oa-whit.patch new file mode 100644 index 0000000000..be74856b13 --- /dev/null +++ b/queue-6.18/drm-xe-rtp-add-ring_force_to_nonpriv_deny-to-oa-whit.patch @@ -0,0 +1,48 @@ +From 33fe9576db7023effa010f9ac35fee0c8d8f0f73 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:46:06 -0700 +Subject: drm/xe/rtp: Add RING_FORCE_TO_NONPRIV_DENY to OA whitelists + +From: Ashutosh Dixit + +[ Upstream commit e70086a3a06d276b4a5d9a2c51c9330c6cf72780 ] + +Unconditionally whitelisting OA registers is a security violation. Set +RING_FORCE_TO_NONPRIV_DENY bit in OA nonpriv slots, so that OA registers +don't get whitelisted by default after probe, gt reset, resume and engine +reset. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Suggested-by: Umesh Nerlige Ramappa +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-2-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index 47fb3e74b567c..5cb7e0e3a66bd 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -67,10 +67,12 @@ static const struct xe_rtp_entry_sr register_whitelist[] = { + XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0)) + }, + ++#define WHITELIST_DENY(r, f) WHITELIST(r, (f) | RING_FORCE_TO_NONPRIV_DENY) ++ + #define WHITELIST_OA_MMIO_TRG(trg, status, head) \ +- WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \ +- WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD), \ +- WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4) ++ WHITELIST_DENY(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \ ++ WHITELIST_DENY(status, RING_FORCE_TO_NONPRIV_ACCESS_RD), \ ++ WHITELIST_DENY(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4) + + #define WHITELIST_OAG_MMIO_TRG \ + WHITELIST_OA_MMIO_TRG(OAG_MMIOTRIGGER, OAG_OASTATUS, OAG_OAHEADPTR) +-- +2.53.0 + diff --git a/queue-6.18/drm-xe-rtp-de-whitelist-oa-registers-for-all-hwe-s-f.patch b/queue-6.18/drm-xe-rtp-de-whitelist-oa-registers-for-all-hwe-s-f.patch new file mode 100644 index 0000000000..96bae33190 --- /dev/null +++ b/queue-6.18/drm-xe-rtp-de-whitelist-oa-registers-for-all-hwe-s-f.patch @@ -0,0 +1,107 @@ +From 4dfe21f996ff73b02525a6932e5e1985027c4081 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:46:12 -0700 +Subject: drm/xe/rtp: (De-)whitelist OA registers for all hwe's for a gt + +From: Ashutosh Dixit + +[ Upstream commit ebba7ce65252a4ab0e3794ff14854df2afca5c08 ] + +Whitelist or de-whitelist OA registers for all hwe's on the gt on which the +OA stream is opened. This simplifies the case where an oa unit has 0 +attached hwe's (but which monitors OA events on the associated GT). + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-8-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 34 +++++++++++++++++++++++++-- + drivers/gpu/drm/xe/xe_reg_whitelist.h | 4 ++++ + 2 files changed, 36 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index 4922b3561dbf4..e77f50da4a268 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -9,7 +9,7 @@ + #include "regs/xe_gt_regs.h" + #include "regs/xe_oa_regs.h" + #include "regs/xe_regs.h" +-#include "xe_gt_types.h" ++#include "xe_gt.h" + #include "xe_gt_printk.h" + #include "xe_platform_types.h" + #include "xe_reg_sr.h" +@@ -161,7 +161,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, first_oa_slot); + } + +-__maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist) ++static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist) + { + struct xe_reg_sr_entry *entry; + unsigned long reg; +@@ -176,6 +176,36 @@ __maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool wh + xe_reg_sr_apply_mmio(&hwe->oa_sr, hwe->gt); + } + ++/** ++ * xe_reg_whitelist_oa_regs - whitelist oa registers for gt ++ * @gt: gt to whitelist oa registers for ++ * ++ * Whitelist OA registers by resetting RING_FORCE_TO_NONPRIV_DENY ++ */ ++void xe_reg_whitelist_oa_regs(struct xe_gt *gt) ++{ ++ struct xe_hw_engine *hwe; ++ enum xe_hw_engine_id id; ++ ++ for_each_hw_engine(hwe, gt, id) ++ __whitelist_oa_regs(hwe, true); ++} ++ ++/** ++ * xe_reg_dewhitelist_oa_regs - dewhitelist oa registers for gt ++ * @gt: gt to dewhitelist oa registers for ++ * ++ * Dewhitelist OA registers by setting RING_FORCE_TO_NONPRIV_DENY ++ */ ++void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt) ++{ ++ struct xe_hw_engine *hwe; ++ enum xe_hw_engine_id id; ++ ++ for_each_hw_engine(hwe, gt, id) ++ __whitelist_oa_regs(hwe, false); ++} ++ + /** + * xe_reg_whitelist_print_entry - print one whitelist entry + * @p: DRM printer +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.h b/drivers/gpu/drm/xe/xe_reg_whitelist.h +index 69b121d377da0..f243b6ac60b7e 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.h ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.h +@@ -9,12 +9,16 @@ + #include + + struct drm_printer; ++struct xe_gt; + struct xe_hw_engine; + struct xe_reg_sr; + struct xe_reg_sr_entry; + + void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe); + ++void xe_reg_whitelist_oa_regs(struct xe_gt *gt); ++void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt); ++ + void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent, + u32 reg, struct xe_reg_sr_entry *entry); + +-- +2.53.0 + diff --git a/queue-6.18/drm-xe-rtp-ensure-locking-ref-counting-for-oa-whitel.patch b/queue-6.18/drm-xe-rtp-ensure-locking-ref-counting-for-oa-whitel.patch new file mode 100644 index 0000000000..09b5b4fc55 --- /dev/null +++ b/queue-6.18/drm-xe-rtp-ensure-locking-ref-counting-for-oa-whitel.patch @@ -0,0 +1,77 @@ +From 3383b7b216bb5d0141b8973fbac0c09524db250e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:46:14 -0700 +Subject: drm/xe/rtp: Ensure locking/ref counting for OA whitelists + +From: Ashutosh Dixit + +[ Upstream commit ef78e2a22f72c892fd6663f0760abd208d49a3e2 ] + +Since multiple OA streams might be open in parallel on a gt, ensure that +proper locking is in place. Also ensure that OA registers are whitelisted +when the first OA stream is open and de-whitelisted after the last OA +stream is closed. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-10-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_oa_types.h | 3 +++ + drivers/gpu/drm/xe/xe_reg_whitelist.c | 10 ++++++++++ + 2 files changed, 13 insertions(+) + +diff --git a/drivers/gpu/drm/xe/xe_oa_types.h b/drivers/gpu/drm/xe/xe_oa_types.h +index daf701b5d48b9..48f9520f560c2 100644 +--- a/drivers/gpu/drm/xe/xe_oa_types.h ++++ b/drivers/gpu/drm/xe/xe_oa_types.h +@@ -125,6 +125,9 @@ struct xe_oa_gt { + + /** @oa_unit: array of oa_units */ + struct xe_oa_unit *oa_unit; ++ ++ /** @whitelist_count: number of open streams for which oa registers are whitelisted */ ++ u32 whitelist_count; + }; + + /** +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index e77f50da4a268..eb1d6f52f75fb 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -9,6 +9,7 @@ + #include "regs/xe_gt_regs.h" + #include "regs/xe_oa_regs.h" + #include "regs/xe_regs.h" ++#include "xe_assert.h" + #include "xe_gt.h" + #include "xe_gt_printk.h" + #include "xe_platform_types.h" +@@ -187,6 +188,10 @@ void xe_reg_whitelist_oa_regs(struct xe_gt *gt) + struct xe_hw_engine *hwe; + enum xe_hw_engine_id id; + ++ lockdep_assert_held(>->oa.gt_lock); ++ if (gt->oa.whitelist_count++) ++ return; ++ + for_each_hw_engine(hwe, gt, id) + __whitelist_oa_regs(hwe, true); + } +@@ -202,6 +207,11 @@ void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt) + struct xe_hw_engine *hwe; + enum xe_hw_engine_id id; + ++ lockdep_assert_held(>->oa.gt_lock); ++ xe_assert(gt_to_xe(gt), gt->oa.whitelist_count); ++ if (--gt->oa.whitelist_count) ++ return; ++ + for_each_hw_engine(hwe, gt, id) + __whitelist_oa_regs(hwe, false); + } +-- +2.53.0 + diff --git a/queue-6.18/drm-xe-rtp-generalize-whitelist_apply_to_hwe.patch b/queue-6.18/drm-xe-rtp-generalize-whitelist_apply_to_hwe.patch new file mode 100644 index 0000000000..6db3567e83 --- /dev/null +++ b/queue-6.18/drm-xe-rtp-generalize-whitelist_apply_to_hwe.patch @@ -0,0 +1,69 @@ +From a29f3356ea5e009a021481743d7e1dbc4a59c55f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:46:09 -0700 +Subject: drm/xe/rtp: Generalize whitelist_apply_to_hwe + +From: Ashutosh Dixit + +[ Upstream commit 4fe2844b0f0c7cdc45ca4c4c62ca56b7f26c514c ] + +Generalize whitelist_apply_to_hwe to construct both non-OA and OA +whitelist nonpriv registers. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-5-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index a5658b2df0cc1..cc9f0f598e49c 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -92,9 +92,10 @@ static const struct xe_rtp_entry_sr oa_whitelist[] = { + }, + }; + +-static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe) ++static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe, struct xe_reg_sr *in, ++ struct xe_reg_sr *out, int first_slot) + { +- struct xe_reg_sr *sr = &hwe->reg_whitelist; ++ struct xe_reg_sr *sr = in; + struct xe_reg_sr_entry *entry; + struct drm_printer p; + unsigned long reg; +@@ -103,7 +104,7 @@ static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe) + xe_gt_dbg(hwe->gt, "Add %s whitelist to engine\n", sr->name); + p = xe_gt_dbg_printer(hwe->gt); + +- slot = 0; ++ slot = first_slot; + xa_for_each(&sr->xa, reg, entry) { + struct xe_reg_sr_entry hwe_entry = { + .reg = RING_FORCE_TO_NONPRIV(hwe->mmio_base, slot), +@@ -120,7 +121,7 @@ static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe) + } + + xe_reg_whitelist_print_entry(&p, 0, reg, entry); +- xe_reg_sr_add(&hwe->reg_sr, &hwe_entry, hwe->gt); ++ xe_reg_sr_add(out, &hwe_entry, hwe->gt); + + slot++; + } +@@ -143,7 +144,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + + xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist), + &hwe->reg_whitelist); +- first_oa_slot = whitelist_apply_to_hwe(hwe); ++ first_oa_slot = whitelist_apply_to_hwe(hwe, &hwe->reg_whitelist, &hwe->reg_sr, 0); + + xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist), + &hwe->oa_whitelist); +-- +2.53.0 + diff --git a/queue-6.18/drm-xe-rtp-keep-track-of-non-oa-nonpriv-slots.patch b/queue-6.18/drm-xe-rtp-keep-track-of-non-oa-nonpriv-slots.patch new file mode 100644 index 0000000000..08b0b3c2ed --- /dev/null +++ b/queue-6.18/drm-xe-rtp-keep-track-of-non-oa-nonpriv-slots.patch @@ -0,0 +1,61 @@ +From 9eb916465359569ebbc516ad48466253c57f3c70 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:46:08 -0700 +Subject: drm/xe/rtp: Keep track of non-OA nonpriv slots + +From: Ashutosh Dixit + +[ Upstream commit 60d49ea28bb190a640bd8dc3f4c946e0811a948c ] + +In order to dynamically whitelist/dewhitelist OA registers on OA stream +open/close, we need to keep track of nonpriv slots occupied by non-OA +register whitelists. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-4-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index 6b7c90ba6d10c..a5658b2df0cc1 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -92,7 +92,7 @@ static const struct xe_rtp_entry_sr oa_whitelist[] = { + }, + }; + +-static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe) ++static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe) + { + struct xe_reg_sr *sr = &hwe->reg_whitelist; + struct xe_reg_sr_entry *entry; +@@ -124,6 +124,8 @@ static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe) + + slot++; + } ++ ++ return slot; + } + + /** +@@ -137,10 +139,11 @@ static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe) + void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + { + struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); ++ int first_oa_slot; + + xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist), + &hwe->reg_whitelist); +- whitelist_apply_to_hwe(hwe); ++ first_oa_slot = whitelist_apply_to_hwe(hwe); + + xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist), + &hwe->oa_whitelist); +-- +2.53.0 + diff --git a/queue-6.18/drm-xe-rtp-maintain-oa-whitelists-separately.patch b/queue-6.18/drm-xe-rtp-maintain-oa-whitelists-separately.patch new file mode 100644 index 0000000000..e2f41d5f9b --- /dev/null +++ b/queue-6.18/drm-xe-rtp-maintain-oa-whitelists-separately.patch @@ -0,0 +1,104 @@ +From 07cebe22606880e03def70b37cb3554eda045c64 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:46:07 -0700 +Subject: drm/xe/rtp: Maintain OA whitelists separately + +From: Ashutosh Dixit + +[ Upstream commit 31e2437561621b4867c08efc890bf629d017df03 ] + +Contains minor modification of the above commit because of changed API. + +OA registers are dynamically whitelisted (and again dewhitelisted) on OA +stream open/close. Maintaining OA whitelists separately from non-OA +register whitlists simplifies this management of OA register +whitelisting/dewhitelisting. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-3-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_gt_debugfs.c | 4 +++- + drivers/gpu/drm/xe/xe_hw_engine.c | 2 ++ + drivers/gpu/drm/xe/xe_hw_engine_types.h | 8 ++++++++ + drivers/gpu/drm/xe/xe_reg_whitelist.c | 6 ++++++ + 4 files changed, 19 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c +index f253e2df49077..1a4d8d4f44b4d 100644 +--- a/drivers/gpu/drm/xe/xe_gt_debugfs.c ++++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c +@@ -174,8 +174,10 @@ static int register_save_restore(struct xe_gt *gt, struct drm_printer *p) + drm_printf(p, "\n"); + + drm_printf(p, "Whitelist\n"); +- for_each_hw_engine(hwe, gt, id) ++ for_each_hw_engine(hwe, gt, id) { + xe_reg_whitelist_dump(&hwe->reg_whitelist, p); ++ xe_reg_whitelist_dump(&hwe->oa_whitelist, p); ++ } + + xe_pm_runtime_put(gt_to_xe(gt)); + +diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c +index d88770370eeb0..66a738f17a3ba 100644 +--- a/drivers/gpu/drm/xe/xe_hw_engine.c ++++ b/drivers/gpu/drm/xe/xe_hw_engine.c +@@ -565,6 +565,8 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe, + hw_engine_setup_default_state(hwe); + + xe_reg_sr_init(&hwe->reg_whitelist, hwe->name, gt_to_xe(gt)); ++ xe_reg_sr_init(&hwe->oa_whitelist, hwe->name, gt_to_xe(gt)); ++ xe_reg_sr_init(&hwe->oa_sr, hwe->name, gt_to_xe(gt)); + xe_reg_whitelist_process_engine(hwe); + } + +diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h +index e4191a7a2c318..04ca7545d22c3 100644 +--- a/drivers/gpu/drm/xe/xe_hw_engine_types.h ++++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h +@@ -128,6 +128,14 @@ struct xe_hw_engine { + * @reg_whitelist: table with registers to be whitelisted + */ + struct xe_reg_sr reg_whitelist; ++ /** ++ * @oa_whitelist: oa registers to be whitelisted ++ */ ++ struct xe_reg_sr oa_whitelist; ++ /** ++ * @oa_sr: oa nonpriv whitelist registers, changed on oa stream open/close ++ */ ++ struct xe_reg_sr oa_sr; + /** + * @reg_lrc: LRC workaround registers + */ +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index 5cb7e0e3a66bd..6b7c90ba6d10c 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -66,6 +66,9 @@ static const struct xe_rtp_entry_sr register_whitelist[] = { + ENGINE_CLASS(RENDER)), + XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0)) + }, ++}; ++ ++static const struct xe_rtp_entry_sr oa_whitelist[] = { + + #define WHITELIST_DENY(r, f) WHITELIST(r, (f) | RING_FORCE_TO_NONPRIV_DENY) + +@@ -138,6 +141,9 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist), + &hwe->reg_whitelist); + whitelist_apply_to_hwe(hwe); ++ ++ xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist), ++ &hwe->oa_whitelist); + } + + /** +-- +2.53.0 + diff --git a/queue-6.18/drm-xe-rtp-refactor-oag-mmio-trigger-register-whitel.patch b/queue-6.18/drm-xe-rtp-refactor-oag-mmio-trigger-register-whitel.patch new file mode 100644 index 0000000000..e79e77f226 --- /dev/null +++ b/queue-6.18/drm-xe-rtp-refactor-oag-mmio-trigger-register-whitel.patch @@ -0,0 +1,68 @@ +From 6f15efed6330cc87aafae1e5789e4a65e187990a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:46:05 -0700 +Subject: drm/xe/rtp: Refactor OAG MMIO trigger register whitelisting + +From: Ashutosh Dixit + +[ Upstream commit ed455775c5a68b75e5f6ad6c8e0e3e9c98fd3f64 ] + +Minor refactor of OAG MMIO trigger register whitelisting for code reuse +with OAM MMIO trigger register whitelisting. + +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20251202025115.373546-5-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 29 ++++++++++++--------------- + 1 file changed, 13 insertions(+), 16 deletions(-) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index 21763dc51150b..47fb3e74b567c 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -66,27 +66,24 @@ static const struct xe_rtp_entry_sr register_whitelist[] = { + ENGINE_CLASS(RENDER)), + XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0)) + }, +- { XE_RTP_NAME("oa_reg_render"), ++ ++#define WHITELIST_OA_MMIO_TRG(trg, status, head) \ ++ WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \ ++ WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD), \ ++ WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4) ++ ++#define WHITELIST_OAG_MMIO_TRG \ ++ WHITELIST_OA_MMIO_TRG(OAG_MMIOTRIGGER, OAG_OASTATUS, OAG_OAHEADPTR) ++ ++ { XE_RTP_NAME("oag_mmio_trg_rcs"), + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED), + ENGINE_CLASS(RENDER)), +- XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER, +- RING_FORCE_TO_NONPRIV_ACCESS_RW), +- WHITELIST(OAG_OASTATUS, +- RING_FORCE_TO_NONPRIV_ACCESS_RD), +- WHITELIST(OAG_OAHEADPTR, +- RING_FORCE_TO_NONPRIV_ACCESS_RD | +- RING_FORCE_TO_NONPRIV_RANGE_4)) ++ XE_RTP_ACTIONS(WHITELIST_OAG_MMIO_TRG) + }, +- { XE_RTP_NAME("oa_reg_compute"), ++ { XE_RTP_NAME("oag_mmio_trg_ccs"), + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED), + ENGINE_CLASS(COMPUTE)), +- XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER, +- RING_FORCE_TO_NONPRIV_ACCESS_RW), +- WHITELIST(OAG_OASTATUS, +- RING_FORCE_TO_NONPRIV_ACCESS_RD), +- WHITELIST(OAG_OAHEADPTR, +- RING_FORCE_TO_NONPRIV_ACCESS_RD | +- RING_FORCE_TO_NONPRIV_RANGE_4)) ++ XE_RTP_ACTIONS(WHITELIST_OAG_MMIO_TRG) + }, + }; + +-- +2.53.0 + diff --git a/queue-6.18/drm-xe-rtp-save-oa-nonpriv-registers-to-register-sav.patch b/queue-6.18/drm-xe-rtp-save-oa-nonpriv-registers-to-register-sav.patch new file mode 100644 index 0000000000..34e8eadb0a --- /dev/null +++ b/queue-6.18/drm-xe-rtp-save-oa-nonpriv-registers-to-register-sav.patch @@ -0,0 +1,56 @@ +From 138f53d72270deeac67060b07629912ed01cb0fd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:46:10 -0700 +Subject: drm/xe/rtp: Save OA nonpriv registers to register save/restore lists + +From: Ashutosh Dixit + +[ Upstream commit a19a83721a28ccaddace846da70da5c53d7dd052 ] + +Now we can save OA whitelisting nonpriv registers to register save/restore +lists. OA nonpriv registers are saved to both hwe->oa_sr as well as +hwe->reg_sr. + +During probe, resume and gt-reset flows KMD will apply hwe->reg_sr, +ensuring OA registers are de-whitelisted after these events. For +engine-reset, hwe->reg_sr is registered with GuC and GuC will apply these +registers, ensuring OA registers are de-whitelisted after engine resets. + +hwe->oa_sr is used for whitelisting or de-whitelisting OA registers during +OA operation, by toggling the 'deny' bit on oa stream open/close. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-6-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index cc9f0f598e49c..4f7391d787fb0 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -148,6 +148,17 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + + xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist), + &hwe->oa_whitelist); ++ /* ++ * Save oa nonpriv registers to hwe->oa_sr, from which oa registers are whitelisted ++ * or de-whitelisted, by toggling the 'deny' bit on oa stream open/close ++ */ ++ whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->oa_sr, first_oa_slot); ++ ++ /* ++ * Also save oa nonpriv registers to hwe->reg_sr, to ensure oa registers are not ++ * whitelisted by default after probe, gt reset, resume and engine reset ++ */ ++ whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, first_oa_slot); + } + + /** +-- +2.53.0 + diff --git a/queue-6.18/drm-xe-rtp-toggle-deny-bit-to-de-whitelist-oa-regs.patch b/queue-6.18/drm-xe-rtp-toggle-deny-bit-to-de-whitelist-oa-regs.patch new file mode 100644 index 0000000000..fec9c15c35 --- /dev/null +++ b/queue-6.18/drm-xe-rtp-toggle-deny-bit-to-de-whitelist-oa-regs.patch @@ -0,0 +1,51 @@ +From 70d1cf6af7004ff1ce40e466748db57476487057 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:46:11 -0700 +Subject: drm/xe/rtp: Toggle 'deny' bit to (de-)whitelist OA regs + +From: Ashutosh Dixit + +[ Upstream commit b422babd77fac2c96b92db484050e460899bddaf ] + +Whitelist or de-whitelist OA registers by setting or resetting the 'deny' +bit in OA nonpriv registers and writing new register values to HW. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-7-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index 4f7391d787fb0..4922b3561dbf4 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -161,6 +161,21 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, first_oa_slot); + } + ++__maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist) ++{ ++ struct xe_reg_sr_entry *entry; ++ unsigned long reg; ++ ++ xa_for_each(&hwe->oa_sr.xa, reg, entry) { ++ if (whitelist) ++ entry->set_bits &= ~RING_FORCE_TO_NONPRIV_DENY; ++ else ++ entry->set_bits |= RING_FORCE_TO_NONPRIV_DENY; ++ } ++ ++ xe_reg_sr_apply_mmio(&hwe->oa_sr, hwe->gt); ++} ++ + /** + * xe_reg_whitelist_print_entry - print one whitelist entry + * @p: DRM printer +-- +2.53.0 + diff --git a/queue-6.18/series b/queue-6.18/series index f63a8f241c..c07a0f977b 100644 --- a/queue-6.18/series +++ b/queue-6.18/series @@ -341,3 +341,13 @@ drm-vmwgfx-use-check_add_overflow-for-shader-size-offset-bound.patch drm-vmwgfx-validate-external-bo-copy-bounds-for-both-stride-paths.patch spi-spi-cadence-enable-spi_controller_must_tx.patch hid-logitech-dj-fix-maxfield-check-in-dj-short-report-validation.patch +drm-xe-rtp-refactor-oag-mmio-trigger-register-whitel.patch +drm-xe-rtp-add-ring_force_to_nonpriv_deny-to-oa-whit.patch +drm-xe-rtp-maintain-oa-whitelists-separately.patch +drm-xe-rtp-keep-track-of-non-oa-nonpriv-slots.patch +drm-xe-rtp-generalize-whitelist_apply_to_hwe.patch +drm-xe-rtp-save-oa-nonpriv-registers-to-register-sav.patch +drm-xe-rtp-toggle-deny-bit-to-de-whitelist-oa-regs.patch +drm-xe-rtp-de-whitelist-oa-registers-for-all-hwe-s-f.patch +drm-xe-oa-de-whitelist-oa-registers-on-oa-stream-ope.patch +drm-xe-rtp-ensure-locking-ref-counting-for-oa-whitel.patch diff --git a/queue-6.6/iommu-sva-move-x86-disable-check-before-allocation.patch b/queue-6.6/iommu-sva-move-x86-disable-check-before-allocation.patch new file mode 100644 index 0000000000..2decf4481b --- /dev/null +++ b/queue-6.6/iommu-sva-move-x86-disable-check-before-allocation.patch @@ -0,0 +1,52 @@ +From 672f2f24120890d226a58bc5fb747afc02d9c7b1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 3 Aug 2026 19:40:39 +0800 +Subject: iommu/sva: move x86 disable check before allocation + +From: Wei Yang + +Backport of commit 72f98ef9a4be ("iommu: disable SVA when CONFIG_X86 is +set") placed the IS_ENABLED(CONFIG_X86) early-return in +iommu_sva_bind_device() after iommu_sva_alloc_pasid() and kzalloc(handle), +while upstream puts it at the function start. + +On x86 this leaks the kzalloc'd struct iommu_sva (early return skips +kfree) and a globally allocated PASID (mm->pasid wrongly set, never +unbound). Move the check before any allocation/side effect. + +Fixes: 240cd7f2812c ("iommu: disable SVA when CONFIG_X86 is set") + +Signed-off-by: Wei Yang +Acked-by: Lu Baolu +Signed-off-by: Sasha Levin +--- + drivers/iommu/iommu-sva.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/iommu/iommu-sva.c b/drivers/iommu/iommu-sva.c +index 611733c02b7c0..a340b805b82b7 100644 +--- a/drivers/iommu/iommu-sva.c ++++ b/drivers/iommu/iommu-sva.c +@@ -62,6 +62,9 @@ struct iommu_sva *iommu_sva_bind_device(struct device *dev, struct mm_struct *mm + struct iommu_sva *handle; + int ret; + ++ if (IS_ENABLED(CONFIG_X86)) ++ return ERR_PTR(-EOPNOTSUPP); ++ + /* Allocate mm->pasid if necessary. */ + ret = iommu_sva_alloc_pasid(mm, dev); + if (ret) +@@ -71,9 +74,6 @@ struct iommu_sva *iommu_sva_bind_device(struct device *dev, struct mm_struct *mm + if (!handle) + return ERR_PTR(-ENOMEM); + +- if (IS_ENABLED(CONFIG_X86)) +- return ERR_PTR(-EOPNOTSUPP); +- + mutex_lock(&iommu_sva_lock); + /* Search for an existing domain. */ + domain = iommu_get_domain_for_dev_pasid(dev, mm->pasid, +-- +2.53.0 + diff --git a/queue-6.6/series b/queue-6.6/series index a8cba4169d..7d45e9410b 100644 --- a/queue-6.6/series +++ b/queue-6.6/series @@ -205,3 +205,4 @@ spi-spi-cadence-enable-spi_controller_must_tx.patch hid-logitech-dj-fix-maxfield-check-in-dj-short-report-validation.patch ata-libahci_platform-do-not-set-mask_port_map-when-not-needed.patch ata-ahci-make-ahci_ignore_port-handle-empty-mask_port_map.patch +iommu-sva-move-x86-disable-check-before-allocation.patch diff --git a/queue-7.1/drm-xe-oa-de-whitelist-oa-registers-on-oa-stream-ope.patch b/queue-7.1/drm-xe-oa-de-whitelist-oa-registers-on-oa-stream-ope.patch new file mode 100644 index 0000000000..c7bcf89868 --- /dev/null +++ b/queue-7.1/drm-xe-oa-de-whitelist-oa-registers-on-oa-stream-ope.patch @@ -0,0 +1,60 @@ +From d4b7ed15842e8b7b027e28080652a06472e1324c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:42:59 -0700 +Subject: drm/xe/oa: (De-)whitelist OA registers on OA stream open/release + +From: Ashutosh Dixit + +[ Upstream commit 63ddb3ad08ff4e89c108499dfec5e9be5ddc25c9 ] + +Whitelist OA registers on stream open and de-whitelist on stream +close/release. Whitelisting is only done when 'stream->sample' is +true. 'stream->sample' is only true when (a) xe_observation_paranoid is set +to false by system admin, or (b) the process is perfmon_capable(). This +therefore enforces the OA register whitelisting security requirements. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-9-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_oa.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c +index d908f4e039063..5111c6519c6db 100644 +--- a/drivers/gpu/drm/xe/xe_oa.c ++++ b/drivers/gpu/drm/xe/xe_oa.c +@@ -35,6 +35,7 @@ + #include "xe_oa.h" + #include "xe_observation.h" + #include "xe_pm.h" ++#include "xe_reg_whitelist.h" + #include "xe_sched_job.h" + #include "xe_sriov.h" + #include "xe_sync.h" +@@ -866,6 +867,9 @@ static void xe_oa_stream_destroy(struct xe_oa_stream *stream) + + mutex_destroy(&stream->stream_lock); + ++ if (stream->sample) ++ xe_reg_dewhitelist_oa_regs(stream->gt); ++ + xe_oa_disable_metric_set(stream); + xe_exec_queue_put(stream->k_exec_q); + +@@ -1871,6 +1875,9 @@ static int xe_oa_stream_open_ioctl_locked(struct xe_oa *oa, + goto err_disable; + } + ++ if (stream->sample) ++ xe_reg_whitelist_oa_regs(stream->gt); ++ + /* Hold a reference on the drm device till stream_fd is released */ + drm_dev_get(&stream->oa->xe->drm); + +-- +2.53.0 + diff --git a/queue-7.1/drm-xe-rtp-de-whitelist-oa-registers-for-all-hwe-s-f.patch b/queue-7.1/drm-xe-rtp-de-whitelist-oa-registers-for-all-hwe-s-f.patch new file mode 100644 index 0000000000..4b5ed33f20 --- /dev/null +++ b/queue-7.1/drm-xe-rtp-de-whitelist-oa-registers-for-all-hwe-s-f.patch @@ -0,0 +1,107 @@ +From 887ee65f804b1fbb2048d5df85010d58d840abd7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:42:58 -0700 +Subject: drm/xe/rtp: (De-)whitelist OA registers for all hwe's for a gt + +From: Ashutosh Dixit + +[ Upstream commit ebba7ce65252a4ab0e3794ff14854df2afca5c08 ] + +Whitelist or de-whitelist OA registers for all hwe's on the gt on which the +OA stream is opened. This simplifies the case where an oa unit has 0 +attached hwe's (but which monitors OA events on the associated GT). + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-8-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 34 +++++++++++++++++++++++++-- + drivers/gpu/drm/xe/xe_reg_whitelist.h | 4 ++++ + 2 files changed, 36 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index 1a53abbd9a74f..2ecf273c5f401 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -9,7 +9,7 @@ + #include "regs/xe_gt_regs.h" + #include "regs/xe_oa_regs.h" + #include "xe_device.h" +-#include "xe_gt_types.h" ++#include "xe_gt.h" + #include "xe_gt_printk.h" + #include "xe_platform_types.h" + #include "xe_reg_sr.h" +@@ -216,7 +216,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, first_oa_slot); + } + +-__maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist) ++static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist) + { + struct xe_reg_sr_entry *entry; + unsigned long reg; +@@ -231,6 +231,36 @@ __maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool wh + xe_reg_sr_apply_mmio(&hwe->oa_sr, hwe->gt); + } + ++/** ++ * xe_reg_whitelist_oa_regs - whitelist oa registers for gt ++ * @gt: gt to whitelist oa registers for ++ * ++ * Whitelist OA registers by resetting RING_FORCE_TO_NONPRIV_DENY ++ */ ++void xe_reg_whitelist_oa_regs(struct xe_gt *gt) ++{ ++ struct xe_hw_engine *hwe; ++ enum xe_hw_engine_id id; ++ ++ for_each_hw_engine(hwe, gt, id) ++ __whitelist_oa_regs(hwe, true); ++} ++ ++/** ++ * xe_reg_dewhitelist_oa_regs - dewhitelist oa registers for gt ++ * @gt: gt to dewhitelist oa registers for ++ * ++ * Dewhitelist OA registers by setting RING_FORCE_TO_NONPRIV_DENY ++ */ ++void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt) ++{ ++ struct xe_hw_engine *hwe; ++ enum xe_hw_engine_id id; ++ ++ for_each_hw_engine(hwe, gt, id) ++ __whitelist_oa_regs(hwe, false); ++} ++ + /** + * xe_reg_whitelist_print_entry - print one whitelist entry + * @p: DRM printer +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.h b/drivers/gpu/drm/xe/xe_reg_whitelist.h +index 69b121d377da0..f243b6ac60b7e 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.h ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.h +@@ -9,12 +9,16 @@ + #include + + struct drm_printer; ++struct xe_gt; + struct xe_hw_engine; + struct xe_reg_sr; + struct xe_reg_sr_entry; + + void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe); + ++void xe_reg_whitelist_oa_regs(struct xe_gt *gt); ++void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt); ++ + void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent, + u32 reg, struct xe_reg_sr_entry *entry); + +-- +2.53.0 + diff --git a/queue-7.1/drm-xe-rtp-ensure-locking-ref-counting-for-oa-whitel.patch b/queue-7.1/drm-xe-rtp-ensure-locking-ref-counting-for-oa-whitel.patch new file mode 100644 index 0000000000..69246c1924 --- /dev/null +++ b/queue-7.1/drm-xe-rtp-ensure-locking-ref-counting-for-oa-whitel.patch @@ -0,0 +1,69 @@ +From 7ee7deca7df0e57c4be0ce97d8ee6ff29d352239 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:43:00 -0700 +Subject: drm/xe/rtp: Ensure locking/ref counting for OA whitelists + +From: Ashutosh Dixit + +[ Upstream commit ef78e2a22f72c892fd6663f0760abd208d49a3e2 ] + +Since multiple OA streams might be open in parallel on a gt, ensure that +proper locking is in place. Also ensure that OA registers are whitelisted +when the first OA stream is open and de-whitelisted after the last OA +stream is closed. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-10-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_oa_types.h | 3 +++ + drivers/gpu/drm/xe/xe_reg_whitelist.c | 9 +++++++++ + 2 files changed, 12 insertions(+) + +diff --git a/drivers/gpu/drm/xe/xe_oa_types.h b/drivers/gpu/drm/xe/xe_oa_types.h +index b03ffd5134834..c0ddfae755b6a 100644 +--- a/drivers/gpu/drm/xe/xe_oa_types.h ++++ b/drivers/gpu/drm/xe/xe_oa_types.h +@@ -126,6 +126,9 @@ struct xe_oa_gt { + + /** @oa_unit: array of oa_units */ + struct xe_oa_unit *oa_unit; ++ ++ /** @whitelist_count: number of open streams for which oa registers are whitelisted */ ++ u32 whitelist_count; + }; + + /** +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index 2ecf273c5f401..dad47988bdf6d 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -242,6 +242,10 @@ void xe_reg_whitelist_oa_regs(struct xe_gt *gt) + struct xe_hw_engine *hwe; + enum xe_hw_engine_id id; + ++ lockdep_assert_held(>->oa.gt_lock); ++ if (gt->oa.whitelist_count++) ++ return; ++ + for_each_hw_engine(hwe, gt, id) + __whitelist_oa_regs(hwe, true); + } +@@ -257,6 +261,11 @@ void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt) + struct xe_hw_engine *hwe; + enum xe_hw_engine_id id; + ++ lockdep_assert_held(>->oa.gt_lock); ++ xe_assert(gt_to_xe(gt), gt->oa.whitelist_count); ++ if (--gt->oa.whitelist_count) ++ return; ++ + for_each_hw_engine(hwe, gt, id) + __whitelist_oa_regs(hwe, false); + } +-- +2.53.0 + diff --git a/queue-7.1/drm-xe-rtp-generalize-whitelist_apply_to_hwe.patch b/queue-7.1/drm-xe-rtp-generalize-whitelist_apply_to_hwe.patch new file mode 100644 index 0000000000..21b0c96f72 --- /dev/null +++ b/queue-7.1/drm-xe-rtp-generalize-whitelist_apply_to_hwe.patch @@ -0,0 +1,69 @@ +From dcaf930a10a8aca9dda0e382390e4a7adf7f179c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:42:55 -0700 +Subject: drm/xe/rtp: Generalize whitelist_apply_to_hwe + +From: Ashutosh Dixit + +[ Upstream commit 4fe2844b0f0c7cdc45ca4c4c62ca56b7f26c514c ] + +Generalize whitelist_apply_to_hwe to construct both non-OA and OA +whitelist nonpriv registers. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-5-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index 00f00002afcef..1a7d69ef4fe82 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -147,9 +147,10 @@ static const struct xe_rtp_entry_sr oa_whitelist[] = { + }, + }; + +-static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe) ++static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe, struct xe_reg_sr *in, ++ struct xe_reg_sr *out, int first_slot) + { +- struct xe_reg_sr *sr = &hwe->reg_whitelist; ++ struct xe_reg_sr *sr = in; + struct xe_reg_sr_entry *entry; + struct drm_printer p; + unsigned long reg; +@@ -158,7 +159,7 @@ static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe) + xe_gt_dbg(hwe->gt, "Add %s whitelist to engine\n", sr->name); + p = xe_gt_dbg_printer(hwe->gt); + +- slot = 0; ++ slot = first_slot; + xa_for_each(&sr->xa, reg, entry) { + struct xe_reg_sr_entry hwe_entry = { + .reg = RING_FORCE_TO_NONPRIV(hwe->mmio_base, slot), +@@ -175,7 +176,7 @@ static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe) + } + + xe_reg_whitelist_print_entry(&p, 0, reg, entry); +- xe_reg_sr_add(&hwe->reg_sr, &hwe_entry, hwe->gt); ++ xe_reg_sr_add(out, &hwe_entry, hwe->gt); + + slot++; + } +@@ -198,7 +199,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + + xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist), + &hwe->reg_whitelist, false); +- first_oa_slot = whitelist_apply_to_hwe(hwe); ++ first_oa_slot = whitelist_apply_to_hwe(hwe, &hwe->reg_whitelist, &hwe->reg_sr, 0); + + xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist), + &hwe->oa_whitelist, false); +-- +2.53.0 + diff --git a/queue-7.1/drm-xe-rtp-keep-track-of-non-oa-nonpriv-slots.patch b/queue-7.1/drm-xe-rtp-keep-track-of-non-oa-nonpriv-slots.patch new file mode 100644 index 0000000000..443f3f1a4a --- /dev/null +++ b/queue-7.1/drm-xe-rtp-keep-track-of-non-oa-nonpriv-slots.patch @@ -0,0 +1,61 @@ +From df09ac06f7c6fb99473f44e489c4046b69d1b07c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:42:54 -0700 +Subject: drm/xe/rtp: Keep track of non-OA nonpriv slots + +From: Ashutosh Dixit + +[ Upstream commit 60d49ea28bb190a640bd8dc3f4c946e0811a948c ] + +In order to dynamically whitelist/dewhitelist OA registers on OA stream +open/close, we need to keep track of nonpriv slots occupied by non-OA +register whitelists. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-4-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index a0bbf4b745a1f..00f00002afcef 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -147,7 +147,7 @@ static const struct xe_rtp_entry_sr oa_whitelist[] = { + }, + }; + +-static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe) ++static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe) + { + struct xe_reg_sr *sr = &hwe->reg_whitelist; + struct xe_reg_sr_entry *entry; +@@ -179,6 +179,8 @@ static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe) + + slot++; + } ++ ++ return slot; + } + + /** +@@ -192,10 +194,11 @@ static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe) + void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + { + struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); ++ int first_oa_slot; + + xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist), + &hwe->reg_whitelist, false); +- whitelist_apply_to_hwe(hwe); ++ first_oa_slot = whitelist_apply_to_hwe(hwe); + + xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist), + &hwe->oa_whitelist, false); +-- +2.53.0 + diff --git a/queue-7.1/drm-xe-rtp-maintain-oa-whitelists-separately.patch b/queue-7.1/drm-xe-rtp-maintain-oa-whitelists-separately.patch new file mode 100644 index 0000000000..3f58c010ea --- /dev/null +++ b/queue-7.1/drm-xe-rtp-maintain-oa-whitelists-separately.patch @@ -0,0 +1,110 @@ +From 51f5a8c6cf8dcbca4ac5ad71ef0a2bc18e4653d2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:42:53 -0700 +Subject: drm/xe/rtp: Maintain OA whitelists separately +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ashutosh Dixit + +[ Upstream commit 31e2437561621b4867c08efc890bf629d017df03 ] + +OA registers are dynamically whitelisted (and again dewhitelisted) on OA +stream open/close. Maintaining OA whitelists separately from non-OA +register whitlists simplifies this management of OA register +whitelisting/dewhitelisting. + +(cherry picked from commit c478244a9e2d14b3f1f92e8bd293919e554622a5) +[ adapted RTP table from struct wrapper macro `XE_RTP_TABLE_SR()` back to plain `struct xe_rtp_entry_sr[]` array and restored the 5-arg `xe_rtp_process_to_sr()` call with `ARRAY_SIZE()` ] + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-3-ashutosh.dixit@intel.com +Signed-off-by: Thomas Hellström +Signed-off-by: Sasha Levin +Signed-off-by: Ashutosh Dixit +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_gt_debugfs.c | 4 +++- + drivers/gpu/drm/xe/xe_hw_engine.c | 2 ++ + drivers/gpu/drm/xe/xe_hw_engine_types.h | 8 ++++++++ + drivers/gpu/drm/xe/xe_reg_whitelist.c | 6 ++++++ + 4 files changed, 19 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c +index f45306308cd66..c38bcacb27e4a 100644 +--- a/drivers/gpu/drm/xe/xe_gt_debugfs.c ++++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c +@@ -149,8 +149,10 @@ static int register_save_restore(struct xe_gt *gt, struct drm_printer *p) + drm_printf(p, "\n"); + + drm_printf(p, "Whitelist\n"); +- for_each_hw_engine(hwe, gt, id) ++ for_each_hw_engine(hwe, gt, id) { + xe_reg_whitelist_dump(&hwe->reg_whitelist, p); ++ xe_reg_whitelist_dump(&hwe->oa_whitelist, p); ++ } + + return 0; + } +diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c +index a7441a66e94c2..b5a869c720af7 100644 +--- a/drivers/gpu/drm/xe/xe_hw_engine.c ++++ b/drivers/gpu/drm/xe/xe_hw_engine.c +@@ -575,6 +575,8 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe, + hw_engine_setup_default_state(hwe); + + xe_reg_sr_init(&hwe->reg_whitelist, hwe->name, gt_to_xe(gt)); ++ xe_reg_sr_init(&hwe->oa_whitelist, hwe->name, gt_to_xe(gt)); ++ xe_reg_sr_init(&hwe->oa_sr, hwe->name, gt_to_xe(gt)); + xe_reg_whitelist_process_engine(hwe); + } + +diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h +index e4191a7a2c318..04ca7545d22c3 100644 +--- a/drivers/gpu/drm/xe/xe_hw_engine_types.h ++++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h +@@ -128,6 +128,14 @@ struct xe_hw_engine { + * @reg_whitelist: table with registers to be whitelisted + */ + struct xe_reg_sr reg_whitelist; ++ /** ++ * @oa_whitelist: oa registers to be whitelisted ++ */ ++ struct xe_reg_sr oa_whitelist; ++ /** ++ * @oa_sr: oa nonpriv whitelist registers, changed on oa stream open/close ++ */ ++ struct xe_reg_sr oa_sr; + /** + * @reg_lrc: LRC workaround registers + */ +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index 506501d77f389..a0bbf4b745a1f 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -89,6 +89,9 @@ static const struct xe_rtp_entry_sr register_whitelist[] = { + WHITELIST(VFLSKPD, + RING_FORCE_TO_NONPRIV_ACCESS_RW)) + }, ++}; ++ ++static const struct xe_rtp_entry_sr oa_whitelist[] = { + + #define WHITELIST_DENY(r, f) WHITELIST(r, (f) | RING_FORCE_TO_NONPRIV_DENY) + +@@ -193,6 +196,9 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist), + &hwe->reg_whitelist, false); + whitelist_apply_to_hwe(hwe); ++ ++ xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist), ++ &hwe->oa_whitelist, false); + } + + /** +-- +2.53.0 + diff --git a/queue-7.1/drm-xe-rtp-save-oa-nonpriv-registers-to-register-sav.patch b/queue-7.1/drm-xe-rtp-save-oa-nonpriv-registers-to-register-sav.patch new file mode 100644 index 0000000000..b4ba798d8b --- /dev/null +++ b/queue-7.1/drm-xe-rtp-save-oa-nonpriv-registers-to-register-sav.patch @@ -0,0 +1,56 @@ +From e13bfc4a86a1381e563b69044fc21bf51eaf3995 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:42:56 -0700 +Subject: drm/xe/rtp: Save OA nonpriv registers to register save/restore lists + +From: Ashutosh Dixit + +[ Upstream commit a19a83721a28ccaddace846da70da5c53d7dd052 ] + +Now we can save OA whitelisting nonpriv registers to register save/restore +lists. OA nonpriv registers are saved to both hwe->oa_sr as well as +hwe->reg_sr. + +During probe, resume and gt-reset flows KMD will apply hwe->reg_sr, +ensuring OA registers are de-whitelisted after these events. For +engine-reset, hwe->reg_sr is registered with GuC and GuC will apply these +registers, ensuring OA registers are de-whitelisted after engine resets. + +hwe->oa_sr is used for whitelisting or de-whitelisting OA registers during +OA operation, by toggling the 'deny' bit on oa stream open/close. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-6-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index 1a7d69ef4fe82..dbaa387a35613 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -203,6 +203,17 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + + xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist), + &hwe->oa_whitelist, false); ++ /* ++ * Save oa nonpriv registers to hwe->oa_sr, from which oa registers are whitelisted ++ * or de-whitelisted, by toggling the 'deny' bit on oa stream open/close ++ */ ++ whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->oa_sr, first_oa_slot); ++ ++ /* ++ * Also save oa nonpriv registers to hwe->reg_sr, to ensure oa registers are not ++ * whitelisted by default after probe, gt reset, resume and engine reset ++ */ ++ whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, first_oa_slot); + } + + /** +-- +2.53.0 + diff --git a/queue-7.1/drm-xe-rtp-toggle-deny-bit-to-de-whitelist-oa-regs.patch b/queue-7.1/drm-xe-rtp-toggle-deny-bit-to-de-whitelist-oa-regs.patch new file mode 100644 index 0000000000..5475a24542 --- /dev/null +++ b/queue-7.1/drm-xe-rtp-toggle-deny-bit-to-de-whitelist-oa-regs.patch @@ -0,0 +1,51 @@ +From 940684e9d4232351e2fa09fdae603cd56a8ce9d7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Aug 2026 19:42:57 -0700 +Subject: drm/xe/rtp: Toggle 'deny' bit to (de-)whitelist OA regs + +From: Ashutosh Dixit + +[ Upstream commit b422babd77fac2c96b92db484050e460899bddaf ] + +Whitelist or de-whitelist OA registers by setting or resetting the 'deny' +bit in OA nonpriv registers and writing new register values to HW. + +Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Ashutosh Dixit +Reviewed-by: Umesh Nerlige Ramappa +Link: https://patch.msgid.link/20260615224227.34880-7-ashutosh.dixit@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/xe/xe_reg_whitelist.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c +index dbaa387a35613..1a53abbd9a74f 100644 +--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c ++++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c +@@ -216,6 +216,21 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) + whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, first_oa_slot); + } + ++__maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist) ++{ ++ struct xe_reg_sr_entry *entry; ++ unsigned long reg; ++ ++ xa_for_each(&hwe->oa_sr.xa, reg, entry) { ++ if (whitelist) ++ entry->set_bits &= ~RING_FORCE_TO_NONPRIV_DENY; ++ else ++ entry->set_bits |= RING_FORCE_TO_NONPRIV_DENY; ++ } ++ ++ xe_reg_sr_apply_mmio(&hwe->oa_sr, hwe->gt); ++} ++ + /** + * xe_reg_whitelist_print_entry - print one whitelist entry + * @p: DRM printer +-- +2.53.0 + diff --git a/queue-7.1/series b/queue-7.1/series index ea5e132221..dfe6efdcbd 100644 --- a/queue-7.1/series +++ b/queue-7.1/series @@ -416,3 +416,11 @@ drm-vmwgfx-avoid-destroy_workqueue-null-on-vkms-init-failure.patch drm-vmwgfx-enforce-cursor-size-limits-for-mob-cursors.patch drm-vmwgfx-use-check_add_overflow-for-shader-size-offset-bound.patch drm-vmwgfx-validate-external-bo-copy-bounds-for-both-stride-paths.patch +drm-xe-rtp-maintain-oa-whitelists-separately.patch +drm-xe-rtp-keep-track-of-non-oa-nonpriv-slots.patch +drm-xe-rtp-generalize-whitelist_apply_to_hwe.patch +drm-xe-rtp-save-oa-nonpriv-registers-to-register-sav.patch +drm-xe-rtp-toggle-deny-bit-to-de-whitelist-oa-regs.patch +drm-xe-rtp-de-whitelist-oa-registers-for-all-hwe-s-f.patch +drm-xe-oa-de-whitelist-oa-registers-on-oa-stream-ope.patch +drm-xe-rtp-ensure-locking-ref-counting-for-oa-whitel.patch