From: Vivian Wang Date: Sun, 5 Apr 2026 00:42:40 +0000 (-0600) Subject: riscv: smp: Clarify comment "cache" -> "instruction cache" X-Git-Tag: v7.1-rc1~27^2~28 X-Git-Url: http://git.ipfire.org/index.cgi?a=commitdiff_plain;h=31454cb5f1a37eefe2465601418a978b7668424e;p=thirdparty%2Fkernel%2Flinux.git riscv: smp: Clarify comment "cache" -> "instruction cache" local_flush_icache_all() only flushes and synchronizes the *instruction* cache, not the data cache. Since RISC-V does have a cbo.flush instruction for data cache flush, clarify the comment to avoid confusion. Fixes: 58661a30f1bc ("riscv: Flush the instruction cache during SMP bringup") Signed-off-by: Vivian Wang Link: https://patch.msgid.link/20260204-riscv-smp-comment-update-2026-01-v1-2-8b77aa181530@iscas.ac.cn Signed-off-by: Paul Walmsley --- diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 0e6fe20c69a2..8b628580fe11 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -251,8 +251,8 @@ asmlinkage __visible void smp_callin(void) set_cpu_online(curr_cpuid, true); /* - * Remote cache and TLB flushes are ignored while the CPU is offline, - * so flush them both right now just in case. + * Remote instruction cache and TLB flushes are ignored while the CPU + * is offline, so flush them both right now just in case. */ local_flush_icache_all(); local_flush_tlb_all();