In preparation for support for Airoha AN7583, convert the driver to
regmap API. This is needed as Airoha AN7583 will use syscon to access
reset registers.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
arm: airoha: introduce EN7523 helpers to get SCU and CHIP_SCU regmaps
We need access SCU and CHIP_SCU regmaps in several places (clk-airoha,
reset-airoha, airoha_eth). Unfortunately these regmaps can't be easily
retrieved with a common code, because of different Airoha SoCs uses
a different dts structure.
To make life easy we can write a commonly named SoC specific helpers
for these tasks. This patch implements helpers for Airoha EN7523 SoC.
arm: airoha: introduce AN7581 helpers to get SCU and CHIP_SCU regmaps
We need access SCU and CHIP_SCU regmaps in several places (clk-airoha,
reset-airoha, airoha_eth). Unfortunately these regmaps can't be easily
retrieved with a common code, because of different Airoha SoCs uses
a different dts structure.
To make life easy we can write a commonly named SoC specific helpers
for these tasks. This patch implements helpers for Airoha AN7581 SoC.
airoha/an7581: add CONFIG_TARGET_AN7581=y to the defconfig
This is required because airoha/en7523 will be added with the following
patches. Without this line config for en7523 will be created instead of
an7581.
Vitor Soares [Tue, 28 Oct 2025 15:10:11 +0000 (15:10 +0000)]
toradex: verdin-am62: sync rm-cfg with SDK 11.01.05.03 baseline
Update the resource management configuration (rm-cfg.yaml) to align
with the default configuration provided in TI's AM62xx Processor SDK
Linux version 11.01.05.03, generated using the K3 Resource Partitioning
Tool.
This matches the configuration from board/ti/am62x/rm-cfg.yaml and the
notable change is the sharing of MCU GPIO interrupts between DM R5 and
A53 cores, and reservation of an additional virtual interrupt and event
for TIFS usage.
Quentin Schulz [Tue, 28 Oct 2025 14:02:19 +0000 (15:02 +0100)]
ext4: include missing blk.h
If missing, lbaint_t typedef will not be found in some cases.
[The proper fix for the commit above at the time would have been to
include ide.h as only since commit 1a73661bc7a7 ("dm: Add a new header
for block devices") is the typedef in blk.h]
Tom Rini [Fri, 24 Oct 2025 17:26:42 +0000 (11:26 -0600)]
test/py: multiplexed_log.py: Clean up and correct RunAndLog()
The general python documentation for the subprocess class recommends
that run() be used in all cases that it can handle. What we do in
RunAndLog is simple enough that run() is easy to switch to. In fact,
looking at this exposed a problem we have today, which is that we had
combined stdout and stderr but then looked at both stdout and stderr as
if they were separate. Stop combining them.
Tom Rini [Fri, 7 Nov 2025 19:02:07 +0000 (13:02 -0600)]
Merge patch series "pwm: put symbols into a menu + use if DM_PWM block instead of depends on"
Quentin Schulz <foss+uboot@0leil.net> says:
This improves readability in menuconfig by putting PWM symbols under a
Kconfig menu.
It also groups PWM symbols that depend on DM_PWM together under an if
DM_PWM block so that we don't need to always list the dependency in the
depends on of the symbol.
No intended change in behavior except how it shows in menuconfig.
Quentin Schulz [Thu, 30 Oct 2025 10:03:57 +0000 (11:03 +0100)]
pwm: put all PWM DM drivers under an if condition on DM_PWM
This simplifies the "depends on" since we don't need DM_PWM listed
explicitly there as it already is made explicit via the surrounding
"if". No intended change in behavior.
Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Marek Vasut [Mon, 27 Oct 2025 16:38:38 +0000 (17:38 +0100)]
mailbox: Allow operation without .recv callback
Some shared memory mailboxes may have empty receive operation,
because the data are polled by upper layers directly from the
shared memory region, and there is no completion interrupt or
bit of any sort. Allow empty .recv callback, and if the .recv
callback is empty, exit from mbox_recv() right away, because
any polling for completion here would be meaningless.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Alice Guo <alice.guo@nxp.com>
Marek Vasut [Mon, 27 Oct 2025 16:33:29 +0000 (17:33 +0100)]
clk: renesas: Isolate R-Car Gen3 driver to Gen3, Gen4 and RZ/G2L
Isolate Renesas R-Car Gen3 clock driver to R-Car Gen3 and Gen4 and RZ/G2L.
The Renesas R-Car Gen5 uses SCMI clock protocol driver instead. This is
a preparatory change for R-Car Gen5. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
* bootstd: Describe environment variable extension_overlay_addr
environment and remove extension support from TODO list
EFI:
* Correct the detection of the video mode in the EFI payload app:
- Use struct efi_gop_mode_info in the definition of struct
efi_entry_gopmode.
- In function get_mode_from_entry() use the correct type for the video
mode structure.
* Use a valid error code as return value in efi_store_memory_map().
* Avoid a memory leak for the variable name in efi_bl_create_block_device().
* Correct the code indentation in efi_uc_stop().
* Correct the description of struct efi_priv.
* Fix typos in code comments.
Other:
* qfw: Add more fields and a heading to qfw list
* Fix the support for ACPI pass-through on ARM and RISC-V:
Avoid zeroing out the XSDT address
* test: provide unit test for 'acpi list' command
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# 3PMrjKAxpxocT0hglsMVnptnfvDEigMsjwH/TWrau83mY+juxFQLjm+U4vye+qCa
# 4zXjjLas18+eRcrv2KxU7teakyi1Jp+WbqHq37L26YcQMaLq/RkBc0bTrsreKKLu
# jprYFpvc7EJpH2Fd1XWaZ2EnxXcVSJSvrY/iwRQqb6wbwQ6XGtMvSh3IFY8IzAoh
# N2Pj78oaYqyL1q/TftuZWhEHo3a0M/HfM4D+oMSHzJtWCb0wZHE=
# =OGcS
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 07 Nov 2025 12:21:45 AM CST
# gpg: using RSA key 6DC4F9C71F29A6FA06B76D33C481DBBC2C051AC4
# gpg: Good signature from "Heinrich Schuchardt <xypron.glpk@gmx.de>" [unknown]
# gpg: aka "[jpeg image of size 1389]" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6DC4 F9C7 1F29 A6FA 06B7 6D33 C481 DBBC 2C05 1AC4
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sam Protsenko [Sun, 26 Oct 2025 01:06:58 +0000 (20:06 -0500)]
mmc: exynos_dw_mmc: Disable FMP for Exynos850 chip
Add DWMCI_QUIRK_DISABLE_FMP flag to Exynos850 driver data to make the
driver disable FMP in case of Exynos850 chip. That makes eMMC on
Exynos850 functional when U-Boot is executed during USB boot.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sam Protsenko [Sun, 26 Oct 2025 01:06:57 +0000 (20:06 -0500)]
mmc: exynos_dw_mmc: Add exynos850 compatible
Up until now "samsung,exynos7-dw-mshc-smu" compatible was used for
Exynos850 SoC, as it's present in its device tree. But Exynos850 device
tree also supports "samsung,exynos850-dw-mshc-smu" compatible string.
Add it in compatible ID list in the driver so that it can be matched
against this string for Exynos850 device tree.
No functional change, as the driver data is just a copy of
"samsung,exynos7-dw-mshc-smu" data for now.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sam Protsenko [Sun, 26 Oct 2025 01:06:56 +0000 (20:06 -0500)]
mmc: exynos_dw_mmc: Add quirk for disabling FMP
Add DWMCI_QUIRK_DISABLE_FMP which disables Flash Memory Protector (FMP)
during driver's init. It's usually done by early bootloaders, but in
some cases (like USB boot) the FMP may be left unconfigured. The issue
was observed on Exynos850 SoC (the E850-96 board). Enabling this quirk
makes eMMC functional even in such cases.
No functional change, as this feature is only added here but not enabled
for any chips yet.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sam Protsenko [Sun, 26 Oct 2025 01:06:54 +0000 (20:06 -0500)]
mmc: dw_mmc: Do not export dwmci_send_cmd() and dwmci_set_ios()
Do not over-expose the private dw_mmc API. The glue layer drivers at
this point shouldn't be aware and shouldn't use the generic
dwmci_send_cmd() and dwmci_set_ios() functions. Making those functions
public causes a "leaky abstraction" issue. It clutters the public
interface of generic dw_mmc driver and possibly leads to improper usage
of those functions, so it's a bad design.
If struct dm_dwmci_ops has to be extended, do so by copying it first
(like it's done for example in snps_dw_mmc driver). That also makes sure
the future changes to struct dm_dwmci_ops in dw_mmc driver will be
automatically reflected in all extended copies, and avoid code
duplication.
This effectively reverts commit ef3b16bb8e73 ("mmc: dw_mmc: export
dwmci_send_cmd() and dwmci_set_ios()").
No functional change.
Fixes: ef3b16bb8e73 ("mmc: dw_mmc: export dwmci_send_cmd() and dwmci_set_ios()") Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sam Protsenko [Sun, 26 Oct 2025 01:06:53 +0000 (20:06 -0500)]
mmc: exynos_dw_mmc: Extend dm_dwmci_ops without code duplication
Instead of extending dm_dwmci_ops by copy-pasting the structure code
first, copy the actual structure data with memcpy() and then set the
.execute_tuning field. Now if struct dm_dwmci_ops gets modified in
future, these changes will be automatically reflected in struct
exynos_dwmmc_ops, which prevents possible issues in future. It also
avoids code duplication.
No functional change, but it can prevent possible isssues in future.
Fixes: eda4bd29929c ("mmc: exynos_dw_mmc: add support for MMC HS200 and HS400 modes") Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Anshul Dalal [Fri, 31 Oct 2025 07:46:26 +0000 (13:16 +0530)]
spl: remove redundant prints in boot_from_devices
The null check for loader in boot_from_devices was moved earlier in the
code path by the commit ae409a84e7bff ("spl: NULL check variable before
dereference"), therefore the subsequent null checks for loader are not
necessary.
This patch removes those checks and refactors the prints to be more
useful in case of errors.
U-Boot's falcon mode expects the jump from SPL to kernel to happen on the same
core which is not directly applicable for our heterogeneous platforms since
ATF, OPTEE and other non SPL binaries from tispl.bin should be loaded before the
kernel by the R5 SPL.
So we have to use a different flow to bypass A53 SPL and U-Boot, we first load
the newly added tispl_falcon.bin instead of tispl.bin which lacks u-boot-spl.bin
(A53's SPL) and the corresponding fdt. This sets up dm, tifs, optee and
atf. Once loaded, we load the kernel and the dtb (with fixups) at ATF's
PRELOADED_BL33_BASE and K3_HW_CONFIG_BASE.
NOTE:
Since we're now using the SPL to load the kernel and kernel expects a 2MiB
aligned load address, the existing PRELOADED_BL33_BASE has to be changed for ATF
to 0x82000000 with K3_HW_CONFIG_BASE set to 0x88000000 for the DTB.
Anshul Dalal [Fri, 31 Oct 2025 07:37:57 +0000 (13:07 +0530)]
doc: ti: document R5 falcon mode for AM62 platforms
This patch adds user documentation for R5 falcon mode for AM62
platforms. The main section is added to am62x_sk.rst and other documents
just include the relevant sections. Steps to build falcon support, usage
and the modified R5 memory map have been documented.
Two svg images have also been added for reference, one for the modified
tifalcon.bin and other for the fitImage format specific to R5 falcon
mode.
Anshul Dalal [Fri, 31 Oct 2025 07:37:56 +0000 (13:07 +0530)]
mach-k3: r5: common: add bootargs to kernel's dtb
The bootargs are passed to the kernel in the chosen node, this patch
adds support for populating bootargs in the dtb if missing.
The values for kernel boot params is taken from the env, with 'boot' and
'bootpart' specifying the rootfs for the kernel similar to the
non-falcon boot flow.
Anshul Dalal [Fri, 31 Oct 2025 07:37:54 +0000 (13:07 +0530)]
mach-k3: common: support only MMC in R5 falcon mode
To simplify the boot process and prevent the R5 SPL size from growing,
this patch restricts the boot media to load the next stage payload
(tifalcon.bin and kernel FIT) to MMC only.
We select between eMMC/SD by checking "mmcdev" in env to conform with
how U-Boot proper handles loading binaries from MMC1 or MMC2.
Note that tiboot3.bin (the initial bootloader) can be loaded from any
boot mode supported by the ROM since the restriction only applies to
tifalcon.bin and fitImage.
Anshul Dalal [Fri, 31 Oct 2025 07:37:53 +0000 (13:07 +0530)]
mach-k3: common: enable falcon mode from R5 SPL
We use the spl_board_prepare_for_boot hook to call k3_r5_falcon_prep
which is ran after tispl is loaded but before jump_to_image.
In k3_r5_falcon_prep, we find the boot media and load the kernel FIT
just as standard secure falcon mode (since spl_start_uboot returns 0
now). Once the kernel and args are loaded.
Now when the flow goes to jump_to_image, we do the regular pre-jump
procedure and jump to TFA which jumps to the kernel directly since we
have already loaded the kernel and dtb at their respective addresses
(PRELOADED_BL33_BASE and K3_HW_CONFIG_BASE).
Overall execution for the R5 SPL after this patch:
board_init_r
|-> boot_from_devices
| +-> load_image (we load tifalcon.bin here since spl_start_uboot
| returns 1)
|
+-> spl_prepare_for_boot
| +-> k3_falcon_prep
| +-> load_image (we load fitImage here since spl_start_uboot
| returns 0 now)
|
+-> jump_to_image
Anshul Dalal [Fri, 31 Oct 2025 07:37:52 +0000 (13:07 +0530)]
configs: add falcon mode fragment for k3 devices
This fragment enables falcon mode for K3 platforms and modifies the
memory map.
To have enough stack and heap space for loading kernel image as
FIT the memory map was modified by expanding stack + heap size, the
PRELOADED_BL33_BASE in TFA has to also be updated to 0x82000000 since
the kernel needs to be loaded at 2MiB aligned address along with
updating K3_HW_CONFIG_BASE to 0x88000000 for the DT passed to kernel.
Modified memory map for R5 SPL (modified addresses marked with *):
Quentin Schulz [Wed, 29 Oct 2025 11:17:43 +0000 (12:17 +0100)]
serial: make VPL_DM_SERIAL depend on VPL_DM
I have a hunch VPL_DM_SERIAL should not be selectable if VPL isn't set
as implied by the prefix. Additionally, still based on the prefix, I'm
assuming VPL_DM should be a dependency. Since VPL_DM can only be
selectable when VPL is enabled, only depend on VPL_DM.
This mirrors SPL_DM_SERIAL and TPL_DM_SERIAL so seems right to me.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Quentin Schulz [Wed, 29 Oct 2025 11:08:58 +0000 (12:08 +0100)]
boot: specify SPL_FIT_FULL_CHECK applies to SPL
SPL_FIT_FULL_CHECK currently shares its description and help text with
FIT_FULL_CHECK which is quite confusing, so let's specify this applies
to SPL.
Fixes: 6f3c2d8aa5e6 ("image: Add an option to do a full check of the FIT") Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Tom Rini [Thu, 6 Nov 2025 23:21:46 +0000 (17:21 -0600)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
This is mostly R-Car Gen5 drivers for GPIO, pin control, RSwitch3 and
matching PHYs. There is also a few trivial clean ups for arch headers
and configs. Board code, DT and clock are coming in follow up PR.
Ben Wolsieffer [Mon, 27 Oct 2025 20:56:27 +0000 (16:56 -0400)]
efi: video: fix mode info in payload mode
Currently, the EFI framebuffer is non-functional in payload mode. It
always reports: "No video mode configured in EFI!"
This is caused by a copy-paste error that replaced
"struct efi_entry_gopmode" with "struct efi_gop_mode".
Fixes: 88753816cf54 ("efi: video: Move payload code into a function") Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
On RISC-V QEMU provides an XSDT table. The RSDP table points to it.
We must not zero out this pointer because otherwise no ACPI table can be
found.
Fixes: 15ca25e31ed5 ("x86: emulation: Support BLOBLIST_TABLES properly") Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Simon Glass [Wed, 29 Oct 2025 14:14:32 +0000 (15:14 +0100)]
qfw: Add more fields and a heading to qfw list
Update the command to show the size and selected file, since this is
useful information at times. Add a heading so it is clear what each
field refers to.
Add a simple test as well.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tom Rini [Thu, 30 Oct 2025 04:35:58 +0000 (22:35 -0600)]
Gitlab CI: Rework our tag usage again
Now that we've had jobs running on both amd64 and arm64 hosts for a
while, we have enough data to look at usage and findings. For the world
build job, make use of the new DEFAULT_FAST_TAG and only build it once,
on either amd64 or arm64 as we don't run in to host specific results
there. For sandbox, continue to build on both arm64 and amd64 hosts as
we can find host specific breakage that way. Remove the mistaken
restriction on sandbox64_lwip.
Tom Rini [Thu, 6 Nov 2025 17:32:57 +0000 (11:32 -0600)]
Merge patch series "ARM: bootm: Add support for starting Linux through OPTEE-OS on ARMv7a"
This series from Marek Vasut <marek.vasut@mailbox.org> brings some
enhancements to use cases using OPTEE-OS on ARMv7a platforms, some of
which already existed on ARMv8.
Marek Vasut [Wed, 22 Oct 2025 13:17:16 +0000 (15:17 +0200)]
arm64: renesas: Clean up default boot command
The current default boot command does not respect the Linux kernel 2 MiB
alignment requirement, present on aarch64 [1]:
"
The Image must be placed text_offset bytes from a 2MB aligned base
address anywhere in usable system RAM and called there.
"
Adjust the boot command such, that it always places both Image and DT at
the nearest highest 2 MiB aligned offset. The DT is placed at lower 2 MiB
aligned address, the aarch64 Image is placed at the next higher 2 MiB
aligned address. Is is unlikely that a DT would be larger than 2 MiB on
these systems.
Replace use of hard-coded load addresses with generic ${loadaddr} aligned
using setexpr. This way, if user picks valid ${loadaddr}, their kernel and
DT address will be correctly set as well.
Fix up boot commands to use && instead of ; to exit the boot command early
in case of failure.
Hai Pham [Mon, 27 Oct 2025 17:09:24 +0000 (18:09 +0100)]
arm64: renesas: Make CONFIG_SYS_LOAD_ADDR family-specific
Make CONFIG_SYS_LOAD_ADDR family-specific to prepare for R-Car Gen5
support. R-Car Gen5 uses different memory map compared to the current
R-Car Gen3 and Gen4 and also different CONFIG_SYS_LOAD_ADDR. This is
a preparatory change for R-Car Gen5. No functional change.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Upport
Marek Vasut [Mon, 27 Oct 2025 17:08:33 +0000 (18:08 +0100)]
arm64: renesas: Drop encoded file name from R-Car Gen3/Gen4 header
Checkpatch warns that it's generally not useful to have
the filename in the file. The warning is valid, drop the
encoded file name. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add initial pin control tables for the Renesas R-Car X5H R8A78000 SoC.
This SoC is the first one which includes custom DRV register handling,
different from previous generations due to change in DRV register bit
layout.
Signed-off-by: Huy Bui <huy.bui.wm@renesas.com> Signed-off-by: Khanh Le <khanh.le.xr@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Hai Pham [Mon, 27 Oct 2025 16:53:53 +0000 (17:53 +0100)]
pinctrl: renesas: Move drive strength configuration into sh_pfc_soc_operations
The upcoming Renesas R-Car Gen5 uses different mapping of bits in DRV
control register, which is incompatible with existing DRV register bit
mapping. Add .set_drive_strength callback into sh_pfc_soc_operations
and call it from sh_pfc_pinconf_set(), to allow each SoC specific PFC
driver to implement replacement .set_drive_strength. Make the current
sh_pfc_pinconf_set_drive_strength() non-static, rename it with rcar_
prefix, and pass it as .set_drive_strength for existing PFC drivers.
This is a preparatory patch for R-Car Gen5, no functional change.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Consistently use .set_drive_strength() and pass exisiting
sh_pfc_pinconf_set_drive_strength() as its parameter for
all PFC drivers. Rewrite commit message.]
Huy Bui [Mon, 27 Oct 2025 16:35:38 +0000 (17:35 +0100)]
gpio: renesas: Add R-Car Gen5 support
Add support for the GPIO controller block in the R-Car Gen5 SoC family.
The GPIO controller has a General Input Enable Register (INEN), whose
reset state is to have all input disabled. The GPIO controller also has
updated offsets for its control registers. U-Boot uses three registers,
INDT, POSNEG, INEN, which have updated offsets, those are handled by the
driver.
Signed-off-by: Huy Bui <huy.bui.wm@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: - Access Gen5 specific registers via driver data offsets,
- Update commit message]
Marek Vasut [Mon, 27 Oct 2025 16:35:37 +0000 (17:35 +0100)]
gpio: renesas: Access INDT, POSNEG, INEN registers via match data offsets
The Renesas R-Car Gen5 GPIO controller has INDT, POSNEG, INEN registers
at different offsets compared to previous generations. Introduce three
new entries in struct rcar_gpio_data {} match data to describe these
register offsets for each GPIO controller. Update the driver to access
these three registers through the match data offsets. No functional
change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Mon, 27 Oct 2025 16:35:36 +0000 (17:35 +0100)]
gpio: renesas: Wrap quirks in struct rcar_gpio_data
Wrap the RCAR_GPIO_HAS_INEN quirk in more flexible struct rcar_gpio_data {}
in preparation for addition of Renesas R-Car Gen5 GPIO controller support.
The Renesas R-Car Gen5 GPIO controller requires more than a single quirk
to properly describe it, therefore increase the flexibility and introduce
full match data structure, and use it throughout the driver. No functional
change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Mon, 27 Oct 2025 16:35:35 +0000 (17:35 +0100)]
gpio: renesas: Drop unused register macros
Remove register macros for registers which are not used by this driver.
This makes it easier to get an overview of which registers are really
used by the driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Mon, 27 Oct 2025 16:35:34 +0000 (17:35 +0100)]
gpio: renesas: Drop pfc_offset parsing
The PFC offset is no longer used directly in the driver since commit fbf26bea3964 ("gpio: renesas: Migrate to pinctrl GPIO accessors")
Drop the pfc_offset parsing.
Fixes: fbf26bea3964 ("gpio: renesas: Migrate to pinctrl GPIO accessors") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Thanh Quan [Mon, 27 Oct 2025 16:52:21 +0000 (17:52 +0100)]
phy: renesas: Add Multi-Protocol PHY driver for R-Car X5H
Add PHY driver for Multi-Protocol PHY present on Renesas R-Car X5H
R8A78000 SoC. Currently, the PHY driver only supports configuring
the MPPHY for ethernet operation.
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> #Fix License-Identifier Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Clean up macros, indent, clock and reset handling in probe,
rename the driver and add r8a78000- into compatible string,
update commit message.]
Tam Nguyen [Mon, 27 Oct 2025 16:50:24 +0000 (17:50 +0100)]
phy: renesas: Add PCS driver for Renesas R-Car X5H R8A78000
Add support for the Ethernet Physical Coding Sublayer (PCS) controller
on R-Car Gen5 SoCs, specifically the Renesas R-Car X5H R8A78000.
The controller is based on the SERDES infrastructure used in previous
R-Car generations, with updates for Gen5 register layout and features.
Because majority of this driver is SoC-specific register programming,
the majority of this driver is different enough from R8A779F0 SerDes
driver to justify its own driver. Deduplication of the remaining bits
of code does not yield any improvement.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Add missing clk_bulk_disable() in fail path.
Drop always-true aneg_on setting.
Reduce poll delay from 100s to 100ms.
Use bulk reset operations to finalize reset handling.]
Marek Vasut [Mon, 27 Oct 2025 16:45:42 +0000 (17:45 +0100)]
net: rswitch: Add Renesas R-Car X5H Ethernet Switch3 support
Add support for the Renesas Ethernet Switch3 (RSW3) controller,
present in R-Car Gen5 SoCs such as R-Car X5H (R8A78000). The
hardware offset differences are handled via driver match data.
The driver newly detects whether the switch prot is connected
to xPCS or not, and if so, turns on MIOC bit 3. This is new on
R-Car X5H. GWCKSC register is also programmed only on X5H. The
rest of the operation is identical to RSwitch2.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com> Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
The MPIC_MDC_CLK clock setting value differs between R-Car S4
and R-Car X5H. Parametrize the value in preparation for R-Car
X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The GWDCBAC0, GWDCBAC1, FWPBFCSDC, CABPIRM register offsets changed
between R-Car S4 and R-Car X5H. Parametrize their offsets in preparation
for R-Car X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Inline FWRO, CARO, GWRO, TARO, RMRO macros directly into the
follow up register macros. FWRO, CARO, GWRO, TARO are already
zero, drop them. RMRO is 0x1000, increment all registers which
add RMRO by 0x1000 directly. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The forwarding engine CSD register offset changed between the
R-Car S4 and R-Car X5H. Parametrize this offset in preparation
for R-Car X5H addition into this driver. Clean up the macro
parameter names and make them more obvious. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Mon, 27 Oct 2025 16:45:37 +0000 (17:45 +0100)]
net: rswitch: Parametrize port count
The total port counts differ across variants of this IP in
R-Car S4 and R-Car X5H. Parametrize port count in preparation
for R-Car X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Mon, 27 Oct 2025 16:45:36 +0000 (17:45 +0100)]
net: rswitch: Parametize COMA, ETHA, GWCA offsets
The COMA, ETHA, GWCA offsets differ across variants of this IP in
R-Car S4 and R-Car X5H. Parametrize these offsets in preparation
for R-Car X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Mon, 27 Oct 2025 16:45:35 +0000 (17:45 +0100)]
net: rswitch: Add support for split MII and SerDes
This IP does support operating MII and SerDes via different ports.
Currently, the driver assumes that MII and SerDes are always bound
together on the same port, but this may not be the case. Implement
support for controlling MII and SerDes separately.
While the change is extensive, the gist of the change is to pass
pointer to the selected port registers to MII or SerDes functions,
depending on which port and operations should be done on that port.
Each combined ETHA instance contains both MII and SerDes register
pointers, which may not point to the same port, and passes those
registers to MII and SerDes functions respectively to control the
MII or SerDes of each port.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Mon, 27 Oct 2025 16:45:34 +0000 (17:45 +0100)]
net: rswitch: Use bulk clock operations
The new version of RSwitch3 in Renesas R-Car Gen5 uses multiple
clock to supply the IP. Convert the driver to bulk clock API to
cater for both single clock of R-Car S4 and multiple clock of
R-Car Gen5. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Mon, 27 Oct 2025 16:45:33 +0000 (17:45 +0100)]
net: rswitch: Initialize RX DMA descriptor .die_dt field to DT_FEMPTY
Empty RX DMA descriptor must contain .die_dt field set to DT_FEMPTY,
because hardware DMA overwrites this field to non-DT_FEMPTY when data
are received, and the .recv callback tests the content of RX descriptor
.die_dt field to determine whether hardware did receive any data and
updated the .die_dt field, and based on that information, receives a
packet or not. Fix the incorrect RX DMA descriptor initialization to
assure the .recv callback always works correctly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Thu, 30 Oct 2025 21:23:50 +0000 (22:23 +0100)]
spl: fit: Add ability to jump to Linux via OPTEE-OS on ARMv7a
Add support for jumping to Linux kernel through OPTEE-OS on ARMv7a to SPL.
This is already supported on ARMv8a, this patch adds the ARMv7a support.
Extend the SPL fitImage loader to record OPTEE-OS load address and in case
the load address is non-zero, use the same bootm-optee.S code used by the
U-Boot fitImage jump code to start OPTEE-OS first and jump to Linux next.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Marek Vasut [Thu, 30 Oct 2025 21:23:49 +0000 (22:23 +0100)]
ARM: bootm: Add support for starting Linux through OPTEE-OS on ARMv7a
Add support for jumping to Linux kernel through OPTEE-OS on ARMv7a.
This is only supported if U-Boot runs in PL1 secure. This change adds
two components, one is fitImage OPTEE-OS loadable handler, which makes
a note of OPTEE-OS being loaded and stores the load address for later
jump to it. The second part is the actual jump to Linux through OPTEE-OS.
The jump through OPTEE-OS requires set up of multiple CPU registers, r1
and r2 are passed through, r0 and r3 have to be set to 0, lr is set to
Linux kernel entry point. This setup is done by new assembler function
boot_jump_linux_via_optee().
The boot_jump_linux_via_optee() also includes STM32MP13xx late TZC
configuration write, this cannot be moved easily, hence the ifdef.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
projects / thirdparty / u-boot.git / log
