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Commit | Line | Data |
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18a00dfd | 1 | /* |
f905432c | 2 | * Voipac PXA270 Support |
18a00dfd | 3 | * |
f905432c | 4 | * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> |
18a00dfd MV |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of | |
9 | * the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
19 | * MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include <common.h> | |
23 | #include <asm/arch/hardware.h> | |
5d877f42 | 24 | #include <asm/arch/regs-mmc.h> |
c7e61334 | 25 | #include <netdev.h> |
3ba8bf7c MV |
26 | #include <serial.h> |
27 | #include <asm/io.h> | |
18a00dfd MV |
28 | |
29 | DECLARE_GLOBAL_DATA_PTR; | |
30 | ||
18a00dfd MV |
31 | /* |
32 | * Miscelaneous platform dependent initialisations | |
33 | */ | |
f905432c | 34 | int board_init(void) |
18a00dfd | 35 | { |
720a650c MV |
36 | /* We have RAM, disable cache */ |
37 | dcache_disable(); | |
38 | icache_disable(); | |
39 | ||
18a00dfd MV |
40 | /* memory and cpu-speed are setup before relocation */ |
41 | /* so we do _nothing_ here */ | |
42 | ||
f905432c | 43 | /* Arch number of vpac270 */ |
18a00dfd MV |
44 | gd->bd->bi_arch_number = MACH_TYPE_VPAC270; |
45 | ||
46 | /* adress of boot parameters */ | |
47 | gd->bd->bi_boot_params = 0xa0000100; | |
48 | ||
49 | return 0; | |
50 | } | |
51 | ||
f905432c | 52 | struct serial_device *default_serial_console(void) |
18a00dfd | 53 | { |
f905432c MV |
54 | return &serial_ffuart_device; |
55 | } | |
18a00dfd | 56 | |
720a650c | 57 | extern void pxa_dram_init(void); |
f905432c | 58 | int dram_init(void) |
6ef6eb91 | 59 | { |
411b9eaf | 60 | #ifndef CONFIG_ONENAND |
720a650c | 61 | pxa_dram_init(); |
411b9eaf | 62 | #endif |
6ef6eb91 | 63 | gd->ram_size = PHYS_SDRAM_1_SIZE; |
6ef6eb91 MV |
64 | return 0; |
65 | } | |
66 | ||
67 | void dram_init_banksize(void) | |
f905432c MV |
68 | { |
69 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
18a00dfd | 70 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
18a00dfd | 71 | |
f97e9c65 | 72 | #ifdef CONFIG_RAM_256M |
f905432c MV |
73 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
74 | gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; | |
75 | #endif | |
18a00dfd MV |
76 | } |
77 | ||
5d877f42 MV |
78 | #ifdef CONFIG_CMD_MMC |
79 | int board_mmc_init(bd_t *bis) | |
80 | { | |
81 | pxa_mmc_register(0); | |
82 | return 0; | |
83 | } | |
84 | #endif | |
85 | ||
f905432c | 86 | #ifdef CONFIG_CMD_USB |
18a00dfd MV |
87 | int usb_board_init(void) |
88 | { | |
3ba8bf7c MV |
89 | writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) & |
90 | ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), | |
91 | UHCHR); | |
18a00dfd | 92 | |
3ba8bf7c | 93 | writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); |
18a00dfd | 94 | |
3ba8bf7c MV |
95 | while (readl(UHCHR) & UHCHR_FSBIR) |
96 | ; | |
18a00dfd | 97 | |
3ba8bf7c MV |
98 | writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); |
99 | writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); | |
18a00dfd MV |
100 | |
101 | /* Clear any OTG Pin Hold */ | |
3ba8bf7c MV |
102 | if (readl(PSSR) & PSSR_OTGPH) |
103 | writel(readl(PSSR) | PSSR_OTGPH, PSSR); | |
18a00dfd | 104 | |
3ba8bf7c MV |
105 | writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); |
106 | writel(readl(UHCRHDA) | 0x100, UHCRHDA); | |
18a00dfd MV |
107 | |
108 | /* Set port power control mask bits, only 3 ports. */ | |
3ba8bf7c | 109 | writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); |
18a00dfd MV |
110 | |
111 | /* enable port 2 */ | |
3ba8bf7c MV |
112 | writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | |
113 | UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); | |
18a00dfd MV |
114 | |
115 | return 0; | |
116 | } | |
117 | ||
118 | void usb_board_init_fail(void) | |
119 | { | |
120 | return; | |
121 | } | |
122 | ||
123 | void usb_board_stop(void) | |
124 | { | |
3ba8bf7c | 125 | writel(readl(UHCHR) | UHCHR_FHR, UHCHR); |
18a00dfd | 126 | udelay(11); |
3ba8bf7c | 127 | writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); |
18a00dfd | 128 | |
3ba8bf7c | 129 | writel(readl(UHCCOMS) | 1, UHCCOMS); |
18a00dfd MV |
130 | udelay(10); |
131 | ||
3ba8bf7c | 132 | writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); |
18a00dfd MV |
133 | |
134 | return; | |
135 | } | |
f905432c | 136 | #endif |
18a00dfd MV |
137 | |
138 | #ifdef CONFIG_DRIVER_DM9000 | |
139 | int board_eth_init(bd_t *bis) | |
140 | { | |
141 | return dm9000_initialize(bis); | |
142 | } | |
143 | #endif |