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AArch64: Add MTE CPU feature check support
[thirdparty/binutils-gdb.git] / gdb / aarch64-tdep.c
CommitLineData
07b287a0
MS		 1/* Common target dependent code for GDB on AArch64 systems.
2
3666a048 3 Copyright (C) 2009-2021 Free Software Foundation, Inc.
07b287a0
MS		 4 Contributed by ARM Ltd.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "defs.h"
22
23#include "frame.h"
07b287a0
MS		 24#include "gdbcmd.h"
25#include "gdbcore.h"
4de283e4 26#include "dis-asm.h"
d55e5aa6
TT		 27#include "regcache.h"
28#include "reggroups.h"
4de283e4
TT		 29#include "value.h"
30#include "arch-utils.h"
31#include "osabi.h"
32#include "frame-unwind.h"
33#include "frame-base.h"
d55e5aa6 34#include "trad-frame.h"
4de283e4
TT		 35#include "objfiles.h"
36#include "dwarf2.h"
82ca8957 37#include "dwarf2/frame.h"
4de283e4
TT		 38#include "gdbtypes.h"
39#include "prologue-value.h"
40#include "target-descriptions.h"
07b287a0 41#include "user-regs.h"
4de283e4 42#include "ax-gdb.h"
268a13a5 43#include "gdbsupport/selftest.h"
4de283e4
TT		 44
45#include "aarch64-tdep.h"
46#include "aarch64-ravenscar-thread.h"
47
4de283e4
TT		 48#include "record.h"
49#include "record-full.h"
50#include "arch/aarch64-insn.h"
0d12e84c 51#include "gdbarch.h"
4de283e4
TT		 52
53#include "opcode/aarch64.h"
54#include <algorithm>
f77ee802 55
ea92689a
AH		 56/* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
57 four members. */
58#define HA_MAX_NUM_FLDS 4
59
95228a0d 60/* All possible aarch64 target descriptors. */
6bd434d6 61static target_desc *tdesc_aarch64_list[AARCH64_MAX_SVE_VQ + 1][2/*pauth*/];
95228a0d 62
07b287a0
MS		 63/* The standard register names, and all the valid aliases for them. */
64static const struct
65{
66 const char *const name;
67 int regnum;
68} aarch64_register_aliases[] =
69{
70 /* 64-bit register names. */
71 {"fp", AARCH64_FP_REGNUM},
72 {"lr", AARCH64_LR_REGNUM},
73 {"sp", AARCH64_SP_REGNUM},
74
75 /* 32-bit register names. */
76 {"w0", AARCH64_X0_REGNUM + 0},
77 {"w1", AARCH64_X0_REGNUM + 1},
78 {"w2", AARCH64_X0_REGNUM + 2},
79 {"w3", AARCH64_X0_REGNUM + 3},
80 {"w4", AARCH64_X0_REGNUM + 4},
81 {"w5", AARCH64_X0_REGNUM + 5},
82 {"w6", AARCH64_X0_REGNUM + 6},
83 {"w7", AARCH64_X0_REGNUM + 7},
84 {"w8", AARCH64_X0_REGNUM + 8},
85 {"w9", AARCH64_X0_REGNUM + 9},
86 {"w10", AARCH64_X0_REGNUM + 10},
87 {"w11", AARCH64_X0_REGNUM + 11},
88 {"w12", AARCH64_X0_REGNUM + 12},
89 {"w13", AARCH64_X0_REGNUM + 13},
90 {"w14", AARCH64_X0_REGNUM + 14},
91 {"w15", AARCH64_X0_REGNUM + 15},
92 {"w16", AARCH64_X0_REGNUM + 16},
93 {"w17", AARCH64_X0_REGNUM + 17},
94 {"w18", AARCH64_X0_REGNUM + 18},
95 {"w19", AARCH64_X0_REGNUM + 19},
96 {"w20", AARCH64_X0_REGNUM + 20},
97 {"w21", AARCH64_X0_REGNUM + 21},
98 {"w22", AARCH64_X0_REGNUM + 22},
99 {"w23", AARCH64_X0_REGNUM + 23},
100 {"w24", AARCH64_X0_REGNUM + 24},
101 {"w25", AARCH64_X0_REGNUM + 25},
102 {"w26", AARCH64_X0_REGNUM + 26},
103 {"w27", AARCH64_X0_REGNUM + 27},
104 {"w28", AARCH64_X0_REGNUM + 28},
105 {"w29", AARCH64_X0_REGNUM + 29},
106 {"w30", AARCH64_X0_REGNUM + 30},
107
108 /* specials */
109 {"ip0", AARCH64_X0_REGNUM + 16},
110 {"ip1", AARCH64_X0_REGNUM + 17}
111};
112
113/* The required core 'R' registers. */
114static const char *const aarch64_r_register_names[] =
115{
116 /* These registers must appear in consecutive RAW register number
117 order and they must begin with AARCH64_X0_REGNUM! */
118 "x0", "x1", "x2", "x3",
119 "x4", "x5", "x6", "x7",
120 "x8", "x9", "x10", "x11",
121 "x12", "x13", "x14", "x15",
122 "x16", "x17", "x18", "x19",
123 "x20", "x21", "x22", "x23",
124 "x24", "x25", "x26", "x27",
125 "x28", "x29", "x30", "sp",
126 "pc", "cpsr"
127};
128
129/* The FP/SIMD 'V' registers. */
130static const char *const aarch64_v_register_names[] =
131{
132 /* These registers must appear in consecutive RAW register number
133 order and they must begin with AARCH64_V0_REGNUM! */
134 "v0", "v1", "v2", "v3",
135 "v4", "v5", "v6", "v7",
136 "v8", "v9", "v10", "v11",
137 "v12", "v13", "v14", "v15",
138 "v16", "v17", "v18", "v19",
139 "v20", "v21", "v22", "v23",
140 "v24", "v25", "v26", "v27",
141 "v28", "v29", "v30", "v31",
142 "fpsr",
143 "fpcr"
144};
145
739e8682
AH		 146/* The SVE 'Z' and 'P' registers. */
147static const char *const aarch64_sve_register_names[] =
148{
149 /* These registers must appear in consecutive RAW register number
150 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
151 "z0", "z1", "z2", "z3",
152 "z4", "z5", "z6", "z7",
153 "z8", "z9", "z10", "z11",
154 "z12", "z13", "z14", "z15",
155 "z16", "z17", "z18", "z19",
156 "z20", "z21", "z22", "z23",
157 "z24", "z25", "z26", "z27",
158 "z28", "z29", "z30", "z31",
159 "fpsr", "fpcr",
160 "p0", "p1", "p2", "p3",
161 "p4", "p5", "p6", "p7",
162 "p8", "p9", "p10", "p11",
163 "p12", "p13", "p14", "p15",
164 "ffr", "vg"
165};
166
76bed0fd
AH		 167static const char *const aarch64_pauth_register_names[] =
168{
169 /* Authentication mask for data pointer. */
170 "pauth_dmask",
171 /* Authentication mask for code pointer. */
172 "pauth_cmask"
173};
174
07b287a0
MS		 175/* AArch64 prologue cache structure. */
176struct aarch64_prologue_cache
177{
db634143
PL		 178 /* The program counter at the start of the function. It is used to
179 identify this frame as a prologue frame. */
180 CORE_ADDR func;
181
182 /* The program counter at the time this frame was created; i.e. where
183 this function was called from. It is used to identify this frame as a
184 stub frame. */
185 CORE_ADDR prev_pc;
186
07b287a0
MS		 187 /* The stack pointer at the time this frame was created; i.e. the
188 caller's stack pointer when this function was called. It is used
189 to identify this frame. */
190 CORE_ADDR prev_sp;
191
7dfa3edc
PL		 192 /* Is the target available to read from? */
193 int available_p;
194
07b287a0
MS		 195 /* The frame base for this frame is just prev_sp - frame size.
196 FRAMESIZE is the distance from the frame pointer to the
197 initial stack pointer. */
198 int framesize;
199
200 /* The register used to hold the frame pointer for this frame. */
201 int framereg;
202
203 /* Saved register offsets. */
098caef4 204 trad_frame_saved_reg *saved_regs;
07b287a0
MS		 205};
206
07b287a0
MS		 207static void
208show_aarch64_debug (struct ui_file *file, int from_tty,
dda83cd7 209 struct cmd_list_element *c, const char *value)
07b287a0
MS		 210{
211 fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
212}
213
ffdbe864
YQ		 214namespace {
215
4d9a9006
YQ		 216/* Abstract instruction reader. */
217
218class abstract_instruction_reader
219{
220public:
221 /* Read in one instruction. */
222 virtual ULONGEST read (CORE_ADDR memaddr, int len,
223 enum bfd_endian byte_order) = 0;
224};
225
226/* Instruction reader from real target. */
227
228class instruction_reader : public abstract_instruction_reader
229{
230 public:
231 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 232 override
4d9a9006 233 {
fc2f703e 234 return read_code_unsigned_integer (memaddr, len, byte_order);
4d9a9006
YQ		 235 }
236};
237
ffdbe864
YQ		 238} // namespace
239
3d31bc39
AH		 240/* If address signing is enabled, mask off the signature bits from the link
241 register, which is passed by value in ADDR, using the register values in
242 THIS_FRAME. */
11e1b75f
AH		 243
244static CORE_ADDR
3d31bc39
AH		 245aarch64_frame_unmask_lr (struct gdbarch_tdep *tdep,
246 struct frame_info *this_frame, CORE_ADDR addr)
11e1b75f
AH		 247{
248 if (tdep->has_pauth ()
249 && frame_unwind_register_unsigned (this_frame,
250 tdep->pauth_ra_state_regnum))
251 {
252 int cmask_num = AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base);
253 CORE_ADDR cmask = frame_unwind_register_unsigned (this_frame, cmask_num);
254 addr = addr & ~cmask;
3d31bc39
AH		 255
256 /* Record in the frame that the link register required unmasking. */
257 set_frame_previous_pc_masked (this_frame);
11e1b75f
AH		 258 }
259
260 return addr;
261}
262
aa7ca1bb
AH		 263/* Implement the "get_pc_address_flags" gdbarch method. */
264
265static std::string
266aarch64_get_pc_address_flags (frame_info *frame, CORE_ADDR pc)
267{
268 if (pc != 0 && get_frame_pc_masked (frame))
269 return "PAC";
270
271 return "";
272}
273
07b287a0
MS		 274/* Analyze a prologue, looking for a recognizable stack frame
275 and frame pointer. Scan until we encounter a store that could
276 clobber the stack frame unexpectedly, or an unknown instruction. */
277
278static CORE_ADDR
279aarch64_analyze_prologue (struct gdbarch *gdbarch,
280 CORE_ADDR start, CORE_ADDR limit,
4d9a9006
YQ		 281 struct aarch64_prologue_cache *cache,
282 abstract_instruction_reader& reader)
07b287a0
MS		 283{
284 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
285 int i;
f8e3fe0d
LM		 286
287 /* Whether the stack has been set. This should be true when we notice a SP
288 to FP move or if we are using the SP as the base register for storing
289 data, in case the FP is ommitted. */
290 bool seen_stack_set = false;
291
187f5d00
YQ		 292 /* Track X registers and D registers in prologue. */
293 pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
07b287a0 294
187f5d00 295 for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
07b287a0 296 regs[i] = pv_register (i, 0);
f7b7ed97 297 pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
07b287a0
MS		 298
299 for (; start < limit; start += 4)
300 {
301 uint32_t insn;
d9ebcbce 302 aarch64_inst inst;
07b287a0 303
4d9a9006 304 insn = reader.read (start, 4, byte_order_for_code);
07b287a0 305
561a72d4 306 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
d9ebcbce
YQ		 307 break;
308
309 if (inst.opcode->iclass == addsub_imm
310 && (inst.opcode->op == OP_ADD
311 || strcmp ("sub", inst.opcode->name) == 0))
07b287a0 312 {
d9ebcbce
YQ		 313 unsigned rd = inst.operands[0].reg.regno;
314 unsigned rn = inst.operands[1].reg.regno;
315
316 gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
317 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
318 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
319 gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
320
321 if (inst.opcode->op == OP_ADD)
322 {
323 regs[rd] = pv_add_constant (regs[rn],
324 inst.operands[2].imm.value);
325 }
326 else
327 {
328 regs[rd] = pv_add_constant (regs[rn],
329 -inst.operands[2].imm.value);
330 }
f8e3fe0d
LM		 331
332 /* Did we move SP to FP? */
333 if (rn == AARCH64_SP_REGNUM && rd == AARCH64_FP_REGNUM)
334 seen_stack_set = true;
d9ebcbce
YQ		 335 }
336 else if (inst.opcode->iclass == pcreladdr
337 && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
338 {
339 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
340 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
341
342 regs[inst.operands[0].reg.regno] = pv_unknown ();
07b287a0 343 }
d9ebcbce 344 else if (inst.opcode->iclass == branch_imm)
07b287a0
MS		 345 {
346 /* Stop analysis on branch. */
347 break;
348 }
d9ebcbce 349 else if (inst.opcode->iclass == condbranch)
07b287a0
MS		 350 {
351 /* Stop analysis on branch. */
352 break;
353 }
d9ebcbce 354 else if (inst.opcode->iclass == branch_reg)
07b287a0
MS		 355 {
356 /* Stop analysis on branch. */
357 break;
358 }
d9ebcbce 359 else if (inst.opcode->iclass == compbranch)
07b287a0
MS		 360 {
361 /* Stop analysis on branch. */
362 break;
363 }
d9ebcbce
YQ		 364 else if (inst.opcode->op == OP_MOVZ)
365 {
366 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
f8e3fe0d
LM		 367
368 /* If this shows up before we set the stack, keep going. Otherwise
369 stop the analysis. */
370 if (seen_stack_set)
371 break;
372
d9ebcbce
YQ		 373 regs[inst.operands[0].reg.regno] = pv_unknown ();
374 }
375 else if (inst.opcode->iclass == log_shift
376 && strcmp (inst.opcode->name, "orr") == 0)
07b287a0 377 {
d9ebcbce
YQ		 378 unsigned rd = inst.operands[0].reg.regno;
379 unsigned rn = inst.operands[1].reg.regno;
380 unsigned rm = inst.operands[2].reg.regno;
381
382 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
383 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
384 gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
385
386 if (inst.operands[2].shifter.amount == 0
387 && rn == AARCH64_SP_REGNUM)
07b287a0
MS		 388 regs[rd] = regs[rm];
389 else
390 {
c6185dce
SM		 391 aarch64_debug_printf ("prologue analysis gave up "
392 "addr=%s opcode=0x%x (orr x register)",
393 core_addr_to_string_nz (start), insn);
394
07b287a0
MS		 395 break;
396 }
397 }
d9ebcbce 398 else if (inst.opcode->op == OP_STUR)
07b287a0 399 {
d9ebcbce
YQ		 400 unsigned rt = inst.operands[0].reg.regno;
401 unsigned rn = inst.operands[1].addr.base_regno;
75faf5c4 402 int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
d9ebcbce
YQ		 403
404 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
405 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
406 gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
407 gdb_assert (!inst.operands[1].addr.offset.is_reg);
408
75faf5c4
AH		 409 stack.store
410 (pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm),
411 size, regs[rt]);
f8e3fe0d
LM		 412
413 /* Are we storing with SP as a base? */
414 if (rn == AARCH64_SP_REGNUM)
415 seen_stack_set = true;
07b287a0 416 }
d9ebcbce 417 else if ((inst.opcode->iclass == ldstpair_off
03bcd739
YQ		 418 || (inst.opcode->iclass == ldstpair_indexed
419 && inst.operands[2].addr.preind))
d9ebcbce 420 && strcmp ("stp", inst.opcode->name) == 0)
07b287a0 421 {
03bcd739 422 /* STP with addressing mode Pre-indexed and Base register. */
187f5d00
YQ		 423 unsigned rt1;
424 unsigned rt2;
d9ebcbce
YQ		 425 unsigned rn = inst.operands[2].addr.base_regno;
426 int32_t imm = inst.operands[2].addr.offset.imm;
75faf5c4 427 int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
d9ebcbce 428
187f5d00
YQ		 429 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
430 || inst.operands[0].type == AARCH64_OPND_Ft);
431 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
432 || inst.operands[1].type == AARCH64_OPND_Ft2);
d9ebcbce
YQ		 433 gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
434 gdb_assert (!inst.operands[2].addr.offset.is_reg);
435
07b287a0
MS		 436 /* If recording this store would invalidate the store area
437 (perhaps because rn is not known) then we should abandon
438 further prologue analysis. */
f7b7ed97 439 if (stack.store_would_trash (pv_add_constant (regs[rn], imm)))
07b287a0
MS		 440 break;
441
f7b7ed97 442 if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8)))
07b287a0
MS		 443 break;
444
187f5d00
YQ		 445 rt1 = inst.operands[0].reg.regno;
446 rt2 = inst.operands[1].reg.regno;
447 if (inst.operands[0].type == AARCH64_OPND_Ft)
448 {
187f5d00
YQ		 449 rt1 += AARCH64_X_REGISTER_COUNT;
450 rt2 += AARCH64_X_REGISTER_COUNT;
451 }
452
75faf5c4
AH		 453 stack.store (pv_add_constant (regs[rn], imm), size, regs[rt1]);
454 stack.store (pv_add_constant (regs[rn], imm + size), size, regs[rt2]);
14ac654f 455
d9ebcbce 456 if (inst.operands[2].addr.writeback)
93d96012 457 regs[rn] = pv_add_constant (regs[rn], imm);
07b287a0 458
f8e3fe0d
LM		 459 /* Ignore the instruction that allocates stack space and sets
460 the SP. */
461 if (rn == AARCH64_SP_REGNUM && !inst.operands[2].addr.writeback)
462 seen_stack_set = true;
07b287a0 463 }
432ec081
YQ		 464 else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
465 || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
466 && (inst.opcode->op == OP_STR_POS
467 || inst.opcode->op == OP_STRF_POS)))
468 && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
469 && strcmp ("str", inst.opcode->name) == 0)
470 {
471 /* STR (immediate) */
472 unsigned int rt = inst.operands[0].reg.regno;
473 int32_t imm = inst.operands[1].addr.offset.imm;
474 unsigned int rn = inst.operands[1].addr.base_regno;
75faf5c4 475 int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
432ec081
YQ		 476 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
477 || inst.operands[0].type == AARCH64_OPND_Ft);
478
479 if (inst.operands[0].type == AARCH64_OPND_Ft)
75faf5c4 480 rt += AARCH64_X_REGISTER_COUNT;
432ec081 481
75faf5c4 482 stack.store (pv_add_constant (regs[rn], imm), size, regs[rt]);
432ec081
YQ		 483 if (inst.operands[1].addr.writeback)
484 regs[rn] = pv_add_constant (regs[rn], imm);
f8e3fe0d
LM		 485
486 /* Are we storing with SP as a base? */
487 if (rn == AARCH64_SP_REGNUM)
488 seen_stack_set = true;
432ec081 489 }
d9ebcbce 490 else if (inst.opcode->iclass == testbranch)
07b287a0
MS		 491 {
492 /* Stop analysis on branch. */
493 break;
494 }
17e116a7
AH		 495 else if (inst.opcode->iclass == ic_system)
496 {
497 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
498 int ra_state_val = 0;
499
500 if (insn == 0xd503233f /* paciasp. */
501 || insn == 0xd503237f /* pacibsp. */)
502 {
503 /* Return addresses are mangled. */
504 ra_state_val = 1;
505 }
506 else if (insn == 0xd50323bf /* autiasp. */
507 || insn == 0xd50323ff /* autibsp. */)
508 {
509 /* Return addresses are not mangled. */
510 ra_state_val = 0;
511 }
512 else
513 {
c6185dce
SM		 514 aarch64_debug_printf ("prologue analysis gave up addr=%s"
515 " opcode=0x%x (iclass)",
516 core_addr_to_string_nz (start), insn);
17e116a7
AH		 517 break;
518 }
519
520 if (tdep->has_pauth () && cache != nullptr)
a9a87d35
LM		 521 {
522 int regnum = tdep->pauth_ra_state_regnum;
523 cache->saved_regs[regnum].set_value (ra_state_val);
524 }
17e116a7 525 }
07b287a0
MS		 526 else
527 {
c6185dce
SM		 528 aarch64_debug_printf ("prologue analysis gave up addr=%s"
529 " opcode=0x%x",
530 core_addr_to_string_nz (start), insn);
531
07b287a0
MS		 532 break;
533 }
534 }
535
536 if (cache == NULL)
f7b7ed97 537 return start;
07b287a0
MS		 538
539 if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
540 {
541 /* Frame pointer is fp. Frame size is constant. */
542 cache->framereg = AARCH64_FP_REGNUM;
543 cache->framesize = -regs[AARCH64_FP_REGNUM].k;
544 }
545 else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
546 {
547 /* Try the stack pointer. */
548 cache->framesize = -regs[AARCH64_SP_REGNUM].k;
549 cache->framereg = AARCH64_SP_REGNUM;
550 }
551 else
552 {
553 /* We're just out of luck. We don't know where the frame is. */
554 cache->framereg = -1;
555 cache->framesize = 0;
556 }
557
558 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
559 {
560 CORE_ADDR offset;
561
f7b7ed97 562 if (stack.find_reg (gdbarch, i, &offset))
098caef4 563 cache->saved_regs[i].set_addr (offset);
07b287a0
MS		 564 }
565
187f5d00
YQ		 566 for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
567 {
568 int regnum = gdbarch_num_regs (gdbarch);
569 CORE_ADDR offset;
570
f7b7ed97
TT		 571 if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT,
572 &offset))
098caef4 573 cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].set_addr (offset);
187f5d00
YQ		 574 }
575
07b287a0
MS		 576 return start;
577}
578
4d9a9006
YQ		 579static CORE_ADDR
580aarch64_analyze_prologue (struct gdbarch *gdbarch,
581 CORE_ADDR start, CORE_ADDR limit,
582 struct aarch64_prologue_cache *cache)
583{
584 instruction_reader reader;
585
586 return aarch64_analyze_prologue (gdbarch, start, limit, cache,
587 reader);
588}
589
590#if GDB_SELF_TEST
591
592namespace selftests {
593
594/* Instruction reader from manually cooked instruction sequences. */
595
596class instruction_reader_test : public abstract_instruction_reader
597{
598public:
599 template<size_t SIZE>
600 explicit instruction_reader_test (const uint32_t (&insns)[SIZE])
601 : m_insns (insns), m_insns_size (SIZE)
602 {}
603
604 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 605 override
4d9a9006
YQ		 606 {
607 SELF_CHECK (len == 4);
608 SELF_CHECK (memaddr % 4 == 0);
609 SELF_CHECK (memaddr / 4 < m_insns_size);
610
611 return m_insns[memaddr / 4];
612 }
613
614private:
615 const uint32_t *m_insns;
616 size_t m_insns_size;
617};
618
619static void
620aarch64_analyze_prologue_test (void)
621{
622 struct gdbarch_info info;
623
624 gdbarch_info_init (&info);
625 info.bfd_arch_info = bfd_scan_arch ("aarch64");
626
627 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
628 SELF_CHECK (gdbarch != NULL);
629
17e116a7
AH		 630 struct aarch64_prologue_cache cache;
631 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
632
633 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
634
4d9a9006
YQ		 635 /* Test the simple prologue in which frame pointer is used. */
636 {
4d9a9006
YQ		 637 static const uint32_t insns[] = {
638 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
639 0x910003fd, /* mov x29, sp */
640 0x97ffffe6, /* bl 0x400580 */
641 };
642 instruction_reader_test reader (insns);
643
644 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
645 SELF_CHECK (end == 4 * 2);
646
647 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
648 SELF_CHECK (cache.framesize == 272);
649
650 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
651 {
652 if (i == AARCH64_FP_REGNUM)
098caef4 653 SELF_CHECK (cache.saved_regs[i].addr () == -272);
4d9a9006 654 else if (i == AARCH64_LR_REGNUM)
098caef4 655 SELF_CHECK (cache.saved_regs[i].addr () == -264);
4d9a9006 656 else
a9a87d35
LM		 657 SELF_CHECK (cache.saved_regs[i].is_realreg ()
658 && cache.saved_regs[i].realreg () == i);
4d9a9006
YQ		 659 }
660
661 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
662 {
a9a87d35
LM		 663 int num_regs = gdbarch_num_regs (gdbarch);
664 int regnum = i + num_regs + AARCH64_D0_REGNUM;
4d9a9006 665
a9a87d35
LM		 666 SELF_CHECK (cache.saved_regs[regnum].is_realreg ()
667 && cache.saved_regs[regnum].realreg () == regnum);
4d9a9006
YQ		 668 }
669 }
432ec081
YQ		 670
671 /* Test a prologue in which STR is used and frame pointer is not
672 used. */
673 {
432ec081
YQ		 674 static const uint32_t insns[] = {
675 0xf81d0ff3, /* str x19, [sp, #-48]! */
676 0xb9002fe0, /* str w0, [sp, #44] */
677 0xf90013e1, /* str x1, [sp, #32]*/
678 0xfd000fe0, /* str d0, [sp, #24] */
679 0xaa0203f3, /* mov x19, x2 */
680 0xf94013e0, /* ldr x0, [sp, #32] */
681 };
682 instruction_reader_test reader (insns);
683
68811f8f 684 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
432ec081
YQ		 685 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
686
687 SELF_CHECK (end == 4 * 5);
688
689 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
690 SELF_CHECK (cache.framesize == 48);
691
692 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
693 {
694 if (i == 1)
098caef4 695 SELF_CHECK (cache.saved_regs[i].addr () == -16);
432ec081 696 else if (i == 19)
098caef4 697 SELF_CHECK (cache.saved_regs[i].addr () == -48);
432ec081 698 else
a9a87d35
LM		 699 SELF_CHECK (cache.saved_regs[i].is_realreg ()
700 && cache.saved_regs[i].realreg () == i);
432ec081
YQ		 701 }
702
703 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
704 {
a9a87d35
LM		 705 int num_regs = gdbarch_num_regs (gdbarch);
706 int regnum = i + num_regs + AARCH64_D0_REGNUM;
707
432ec081
YQ		 708
709 if (i == 0)
a9a87d35 710 SELF_CHECK (cache.saved_regs[regnum].addr () == -24);
432ec081 711 else
a9a87d35
LM		 712 SELF_CHECK (cache.saved_regs[regnum].is_realreg ()
713 && cache.saved_regs[regnum].realreg () == regnum);
432ec081
YQ		 714 }
715 }
17e116a7 716
f8e3fe0d
LM		 717 /* Test handling of movz before setting the frame pointer. */
718 {
719 static const uint32_t insns[] = {
720 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
721 0x52800020, /* mov w0, #0x1 */
722 0x910003fd, /* mov x29, sp */
723 0x528000a2, /* mov w2, #0x5 */
724 0x97fffff8, /* bl 6e4 */
725 };
726
727 instruction_reader_test reader (insns);
728
729 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
730 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
731
732 /* We should stop at the 4th instruction. */
733 SELF_CHECK (end == (4 - 1) * 4);
734 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
735 SELF_CHECK (cache.framesize == 16);
736 }
737
738 /* Test handling of movz/stp when using the stack pointer as frame
739 pointer. */
740 {
741 static const uint32_t insns[] = {
742 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
743 0x52800020, /* mov w0, #0x1 */
744 0x290207e0, /* stp w0, w1, [sp, #16] */
745 0xa9018fe2, /* stp x2, x3, [sp, #24] */
746 0x528000a2, /* mov w2, #0x5 */
747 0x97fffff8, /* bl 6e4 */
748 };
749
750 instruction_reader_test reader (insns);
751
752 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
753 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
754
755 /* We should stop at the 5th instruction. */
756 SELF_CHECK (end == (5 - 1) * 4);
757 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
758 SELF_CHECK (cache.framesize == 64);
759 }
760
761 /* Test handling of movz/str when using the stack pointer as frame
762 pointer */
763 {
764 static const uint32_t insns[] = {
765 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
766 0x52800020, /* mov w0, #0x1 */
767 0xb9002be4, /* str w4, [sp, #40] */
768 0xf9001be5, /* str x5, [sp, #48] */
769 0x528000a2, /* mov w2, #0x5 */
770 0x97fffff8, /* bl 6e4 */
771 };
772
773 instruction_reader_test reader (insns);
774
775 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
776 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
777
778 /* We should stop at the 5th instruction. */
779 SELF_CHECK (end == (5 - 1) * 4);
780 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
781 SELF_CHECK (cache.framesize == 64);
782 }
783
784 /* Test handling of movz/stur when using the stack pointer as frame
785 pointer. */
786 {
787 static const uint32_t insns[] = {
788 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
789 0x52800020, /* mov w0, #0x1 */
790 0xb80343e6, /* stur w6, [sp, #52] */
791 0xf80383e7, /* stur x7, [sp, #56] */
792 0x528000a2, /* mov w2, #0x5 */
793 0x97fffff8, /* bl 6e4 */
794 };
795
796 instruction_reader_test reader (insns);
797
798 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
799 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
800
801 /* We should stop at the 5th instruction. */
802 SELF_CHECK (end == (5 - 1) * 4);
803 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
804 SELF_CHECK (cache.framesize == 64);
805 }
806
807 /* Test handling of movz when there is no frame pointer set or no stack
808 pointer used. */
809 {
810 static const uint32_t insns[] = {
811 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
812 0x52800020, /* mov w0, #0x1 */
813 0x528000a2, /* mov w2, #0x5 */
814 0x97fffff8, /* bl 6e4 */
815 };
816
817 instruction_reader_test reader (insns);
818
819 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
820 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
821
822 /* We should stop at the 4th instruction. */
823 SELF_CHECK (end == (4 - 1) * 4);
824 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
825 SELF_CHECK (cache.framesize == 16);
826 }
827
17e116a7
AH		 828 /* Test a prologue in which there is a return address signing instruction. */
829 if (tdep->has_pauth ())
830 {
831 static const uint32_t insns[] = {
832 0xd503233f, /* paciasp */
833 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
834 0x910003fd, /* mov x29, sp */
835 0xf801c3f3, /* str x19, [sp, #28] */
836 0xb9401fa0, /* ldr x19, [x29, #28] */
837 };
838 instruction_reader_test reader (insns);
839
68811f8f 840 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
17e116a7
AH		 841 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache,
842 reader);
843
844 SELF_CHECK (end == 4 * 4);
845 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
846 SELF_CHECK (cache.framesize == 48);
847
848 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
849 {
850 if (i == 19)
098caef4 851 SELF_CHECK (cache.saved_regs[i].addr () == -20);
17e116a7 852 else if (i == AARCH64_FP_REGNUM)
098caef4 853 SELF_CHECK (cache.saved_regs[i].addr () == -48);
17e116a7 854 else if (i == AARCH64_LR_REGNUM)
098caef4 855 SELF_CHECK (cache.saved_regs[i].addr () == -40);
17e116a7 856 else
a9a87d35
LM		 857 SELF_CHECK (cache.saved_regs[i].is_realreg ()
858 && cache.saved_regs[i].realreg () == i);
17e116a7
AH		 859 }
860
861 if (tdep->has_pauth ())
862 {
a9a87d35
LM		 863 int regnum = tdep->pauth_ra_state_regnum;
864 SELF_CHECK (cache.saved_regs[regnum].is_value ());
17e116a7
AH		 865 }
866 }
4d9a9006
YQ		 867}
868} // namespace selftests
869#endif /* GDB_SELF_TEST */
870
07b287a0
MS		 871/* Implement the "skip_prologue" gdbarch method. */
872
873static CORE_ADDR
874aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
875{
07b287a0 876 CORE_ADDR func_addr, limit_pc;
07b287a0
MS		 877
878 /* See if we can determine the end of the prologue via the symbol
879 table. If so, then return either PC, or the PC after the
880 prologue, whichever is greater. */
881 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
882 {
883 CORE_ADDR post_prologue_pc
884 = skip_prologue_using_sal (gdbarch, func_addr);
885
886 if (post_prologue_pc != 0)
325fac50 887 return std::max (pc, post_prologue_pc);
07b287a0
MS		 888 }
889
890 /* Can't determine prologue from the symbol table, need to examine
891 instructions. */
892
893 /* Find an upper limit on the function prologue using the debug
894 information. If the debug information could not be used to
895 provide that bound, then use an arbitrary large number as the
896 upper bound. */
897 limit_pc = skip_prologue_using_sal (gdbarch, pc);
898 if (limit_pc == 0)
899 limit_pc = pc + 128; /* Magic. */
900
901 /* Try disassembling prologue. */
902 return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
903}
904
905/* Scan the function prologue for THIS_FRAME and populate the prologue
906 cache CACHE. */
907
908static void
909aarch64_scan_prologue (struct frame_info *this_frame,
910 struct aarch64_prologue_cache *cache)
911{
912 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
913 CORE_ADDR prologue_start;
914 CORE_ADDR prologue_end;
915 CORE_ADDR prev_pc = get_frame_pc (this_frame);
916 struct gdbarch *gdbarch = get_frame_arch (this_frame);
917
db634143
PL		 918 cache->prev_pc = prev_pc;
919
07b287a0
MS		 920 /* Assume we do not find a frame. */
921 cache->framereg = -1;
922 cache->framesize = 0;
923
924 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
925 &prologue_end))
926 {
927 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
928
929 if (sal.line == 0)
930 {
931 /* No line info so use the current PC. */
932 prologue_end = prev_pc;
933 }
934 else if (sal.end < prologue_end)
935 {
936 /* The next line begins after the function end. */
937 prologue_end = sal.end;
938 }
939
325fac50 940 prologue_end = std::min (prologue_end, prev_pc);
07b287a0
MS		 941 aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
942 }
943 else
944 {
945 CORE_ADDR frame_loc;
07b287a0
MS		 946
947 frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
948 if (frame_loc == 0)
949 return;
950
951 cache->framereg = AARCH64_FP_REGNUM;
952 cache->framesize = 16;
098caef4
LM		 953 cache->saved_regs[29].set_addr (0);
954 cache->saved_regs[30].set_addr (8);
07b287a0
MS		 955 }
956}
957
7dfa3edc
PL		 958/* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
959 function may throw an exception if the inferior's registers or memory is
960 not available. */
07b287a0 961
7dfa3edc
PL		 962static void
963aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
964 struct aarch64_prologue_cache *cache)
07b287a0 965{
07b287a0
MS		 966 CORE_ADDR unwound_fp;
967 int reg;
968
07b287a0
MS		 969 aarch64_scan_prologue (this_frame, cache);
970
971 if (cache->framereg == -1)
7dfa3edc 972 return;
07b287a0
MS		 973
974 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
975 if (unwound_fp == 0)
7dfa3edc 976 return;
07b287a0
MS		 977
978 cache->prev_sp = unwound_fp + cache->framesize;
979
980 /* Calculate actual addresses of saved registers using offsets
981 determined by aarch64_analyze_prologue. */
982 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
a9a87d35 983 if (cache->saved_regs[reg].is_addr ())
098caef4
LM		 984 cache->saved_regs[reg].set_addr (cache->saved_regs[reg].addr ()
985 + cache->prev_sp);
07b287a0 986
db634143
PL		 987 cache->func = get_frame_func (this_frame);
988
7dfa3edc
PL		 989 cache->available_p = 1;
990}
991
992/* Allocate and fill in *THIS_CACHE with information about the prologue of
993 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
994 Return a pointer to the current aarch64_prologue_cache in
995 *THIS_CACHE. */
996
997static struct aarch64_prologue_cache *
998aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
999{
1000 struct aarch64_prologue_cache *cache;
1001
1002 if (*this_cache != NULL)
9a3c8263 1003 return (struct aarch64_prologue_cache *) *this_cache;
7dfa3edc
PL		 1004
1005 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
1006 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1007 *this_cache = cache;
1008
a70b8144 1009 try
7dfa3edc
PL		 1010 {
1011 aarch64_make_prologue_cache_1 (this_frame, cache);
1012 }
230d2906 1013 catch (const gdb_exception_error &ex)
7dfa3edc
PL		 1014 {
1015 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 1016 throw;
7dfa3edc 1017 }
7dfa3edc 1018
07b287a0
MS		 1019 return cache;
1020}
1021
7dfa3edc
PL		 1022/* Implement the "stop_reason" frame_unwind method. */
1023
1024static enum unwind_stop_reason
1025aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame,
1026 void **this_cache)
1027{
1028 struct aarch64_prologue_cache *cache
1029 = aarch64_make_prologue_cache (this_frame, this_cache);
1030
1031 if (!cache->available_p)
1032 return UNWIND_UNAVAILABLE;
1033
1034 /* Halt the backtrace at "_start". */
1035 if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
1036 return UNWIND_OUTERMOST;
1037
1038 /* We've hit a wall, stop. */
1039 if (cache->prev_sp == 0)
1040 return UNWIND_OUTERMOST;
1041
1042 return UNWIND_NO_REASON;
1043}
1044
07b287a0
MS		 1045/* Our frame ID for a normal frame is the current function's starting
1046 PC and the caller's SP when we were called. */
1047
1048static void
1049aarch64_prologue_this_id (struct frame_info *this_frame,
1050 void **this_cache, struct frame_id *this_id)
1051{
7c8edfae
PL		 1052 struct aarch64_prologue_cache *cache
1053 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0 1054
7dfa3edc
PL		 1055 if (!cache->available_p)
1056 *this_id = frame_id_build_unavailable_stack (cache->func);
1057 else
1058 *this_id = frame_id_build (cache->prev_sp, cache->func);
07b287a0
MS		 1059}
1060
1061/* Implement the "prev_register" frame_unwind method. */
1062
1063static struct value *
1064aarch64_prologue_prev_register (struct frame_info *this_frame,
1065 void **this_cache, int prev_regnum)
1066{
7c8edfae
PL		 1067 struct aarch64_prologue_cache *cache
1068 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 1069
1070 /* If we are asked to unwind the PC, then we need to return the LR
1071 instead. The prologue may save PC, but it will point into this
1072 frame's prologue, not the next frame's resume location. */
1073 if (prev_regnum == AARCH64_PC_REGNUM)
1074 {
1075 CORE_ADDR lr;
17e116a7
AH		 1076 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1077 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
07b287a0
MS		 1078
1079 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
17e116a7
AH		 1080
1081 if (tdep->has_pauth ()
a9a87d35 1082 && cache->saved_regs[tdep->pauth_ra_state_regnum].is_value ())
3d31bc39 1083 lr = aarch64_frame_unmask_lr (tdep, this_frame, lr);
17e116a7 1084
07b287a0
MS		 1085 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
1086 }
1087
1088 /* SP is generally not saved to the stack, but this frame is
1089 identified by the next frame's stack pointer at the time of the
1090 call. The value was already reconstructed into PREV_SP. */
1091 /*
dda83cd7
SM		 1092 +----------+ ^
1093 | saved lr | |
07b287a0
MS		 1094 +->| saved fp |--+
1095 | | |
1096 | | | <- Previous SP
1097 | +----------+
1098 | | saved lr |
1099 +--| saved fp |<- FP
dda83cd7
SM		 1100 | |
1101 | |<- SP
1102 +----------+ */
07b287a0
MS		 1103 if (prev_regnum == AARCH64_SP_REGNUM)
1104 return frame_unwind_got_constant (this_frame, prev_regnum,
1105 cache->prev_sp);
1106
1107 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
1108 prev_regnum);
1109}
1110
1111/* AArch64 prologue unwinder. */
6bd434d6 1112static frame_unwind aarch64_prologue_unwind =
07b287a0
MS		 1113{
1114 NORMAL_FRAME,
7dfa3edc 1115 aarch64_prologue_frame_unwind_stop_reason,
07b287a0
MS		 1116 aarch64_prologue_this_id,
1117 aarch64_prologue_prev_register,
1118 NULL,
1119 default_frame_sniffer
1120};
1121
8b61f75d
PL		 1122/* Allocate and fill in *THIS_CACHE with information about the prologue of
1123 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
1124 Return a pointer to the current aarch64_prologue_cache in
1125 *THIS_CACHE. */
07b287a0
MS		 1126
1127static struct aarch64_prologue_cache *
8b61f75d 1128aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache)
07b287a0 1129{
07b287a0 1130 struct aarch64_prologue_cache *cache;
8b61f75d
PL		 1131
1132 if (*this_cache != NULL)
9a3c8263 1133 return (struct aarch64_prologue_cache *) *this_cache;
07b287a0
MS		 1134
1135 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
1136 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
8b61f75d 1137 *this_cache = cache;
07b287a0 1138
a70b8144 1139 try
02a2a705
PL		 1140 {
1141 cache->prev_sp = get_frame_register_unsigned (this_frame,
1142 AARCH64_SP_REGNUM);
1143 cache->prev_pc = get_frame_pc (this_frame);
1144 cache->available_p = 1;
1145 }
230d2906 1146 catch (const gdb_exception_error &ex)
02a2a705
PL		 1147 {
1148 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 1149 throw;
02a2a705 1150 }
07b287a0
MS		 1151
1152 return cache;
1153}
1154
02a2a705
PL		 1155/* Implement the "stop_reason" frame_unwind method. */
1156
1157static enum unwind_stop_reason
1158aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame,
1159 void **this_cache)
1160{
1161 struct aarch64_prologue_cache *cache
1162 = aarch64_make_stub_cache (this_frame, this_cache);
1163
1164 if (!cache->available_p)
1165 return UNWIND_UNAVAILABLE;
1166
1167 return UNWIND_NO_REASON;
1168}
1169
07b287a0
MS		 1170/* Our frame ID for a stub frame is the current SP and LR. */
1171
1172static void
1173aarch64_stub_this_id (struct frame_info *this_frame,
1174 void **this_cache, struct frame_id *this_id)
1175{
8b61f75d
PL		 1176 struct aarch64_prologue_cache *cache
1177 = aarch64_make_stub_cache (this_frame, this_cache);
07b287a0 1178
02a2a705
PL		 1179 if (cache->available_p)
1180 *this_id = frame_id_build (cache->prev_sp, cache->prev_pc);
1181 else
1182 *this_id = frame_id_build_unavailable_stack (cache->prev_pc);
07b287a0
MS		 1183}
1184
1185/* Implement the "sniffer" frame_unwind method. */
1186
1187static int
1188aarch64_stub_unwind_sniffer (const struct frame_unwind *self,
1189 struct frame_info *this_frame,
1190 void **this_prologue_cache)
1191{
1192 CORE_ADDR addr_in_block;
1193 gdb_byte dummy[4];
1194
1195 addr_in_block = get_frame_address_in_block (this_frame);
3e5d3a5a 1196 if (in_plt_section (addr_in_block)
07b287a0
MS		 1197 /* We also use the stub winder if the target memory is unreadable
1198 to avoid having the prologue unwinder trying to read it. */
1199 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
1200 return 1;
1201
1202 return 0;
1203}
1204
1205/* AArch64 stub unwinder. */
6bd434d6 1206static frame_unwind aarch64_stub_unwind =
07b287a0
MS		 1207{
1208 NORMAL_FRAME,
02a2a705 1209 aarch64_stub_frame_unwind_stop_reason,
07b287a0
MS		 1210 aarch64_stub_this_id,
1211 aarch64_prologue_prev_register,
1212 NULL,
1213 aarch64_stub_unwind_sniffer
1214};
1215
1216/* Return the frame base address of *THIS_FRAME. */
1217
1218static CORE_ADDR
1219aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache)
1220{
7c8edfae
PL		 1221 struct aarch64_prologue_cache *cache
1222 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 1223
1224 return cache->prev_sp - cache->framesize;
1225}
1226
1227/* AArch64 default frame base information. */
6bd434d6 1228static frame_base aarch64_normal_base =
07b287a0
MS		 1229{
1230 &aarch64_prologue_unwind,
1231 aarch64_normal_frame_base,
1232 aarch64_normal_frame_base,
1233 aarch64_normal_frame_base
1234};
1235
07b287a0
MS		 1236/* Return the value of the REGNUM register in the previous frame of
1237 *THIS_FRAME. */
1238
1239static struct value *
1240aarch64_dwarf2_prev_register (struct frame_info *this_frame,
1241 void **this_cache, int regnum)
1242{
11e1b75f 1243 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
07b287a0
MS		 1244 CORE_ADDR lr;
1245
1246 switch (regnum)
1247 {
1248 case AARCH64_PC_REGNUM:
1249 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
3d31bc39 1250 lr = aarch64_frame_unmask_lr (tdep, this_frame, lr);
07b287a0
MS		 1251 return frame_unwind_got_constant (this_frame, regnum, lr);
1252
1253 default:
1254 internal_error (__FILE__, __LINE__,
1255 _("Unexpected register %d"), regnum);
1256 }
1257}
1258
11e1b75f
AH		 1259static const unsigned char op_lit0 = DW_OP_lit0;
1260static const unsigned char op_lit1 = DW_OP_lit1;
1261
07b287a0
MS		 1262/* Implement the "init_reg" dwarf2_frame_ops method. */
1263
1264static void
1265aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1266 struct dwarf2_frame_state_reg *reg,
1267 struct frame_info *this_frame)
1268{
11e1b75f
AH		 1269 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1270
07b287a0
MS		 1271 switch (regnum)
1272 {
1273 case AARCH64_PC_REGNUM:
1274 reg->how = DWARF2_FRAME_REG_FN;
1275 reg->loc.fn = aarch64_dwarf2_prev_register;
11e1b75f
AH		 1276 return;
1277
07b287a0
MS		 1278 case AARCH64_SP_REGNUM:
1279 reg->how = DWARF2_FRAME_REG_CFA;
11e1b75f
AH		 1280 return;
1281 }
1282
1283 /* Init pauth registers. */
1284 if (tdep->has_pauth ())
1285 {
1286 if (regnum == tdep->pauth_ra_state_regnum)
1287 {
1288 /* Initialize RA_STATE to zero. */
1289 reg->how = DWARF2_FRAME_REG_SAVED_VAL_EXP;
1290 reg->loc.exp.start = &op_lit0;
1291 reg->loc.exp.len = 1;
1292 return;
1293 }
1294 else if (regnum == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
1295 || regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base))
1296 {
1297 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1298 return;
1299 }
07b287a0
MS		 1300 }
1301}
1302
11e1b75f
AH		 1303/* Implement the execute_dwarf_cfa_vendor_op method. */
1304
1305static bool
1306aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op,
1307 struct dwarf2_frame_state *fs)
1308{
1309 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1310 struct dwarf2_frame_state_reg *ra_state;
1311
8fca4da0 1312 if (op == DW_CFA_AARCH64_negate_ra_state)
11e1b75f 1313 {
8fca4da0
AH		 1314 /* On systems without pauth, treat as a nop. */
1315 if (!tdep->has_pauth ())
1316 return true;
1317
11e1b75f
AH		 1318 /* Allocate RA_STATE column if it's not allocated yet. */
1319 fs->regs.alloc_regs (AARCH64_DWARF_PAUTH_RA_STATE + 1);
1320
1321 /* Toggle the status of RA_STATE between 0 and 1. */
1322 ra_state = &(fs->regs.reg[AARCH64_DWARF_PAUTH_RA_STATE]);
1323 ra_state->how = DWARF2_FRAME_REG_SAVED_VAL_EXP;
1324
1325 if (ra_state->loc.exp.start == nullptr
1326 || ra_state->loc.exp.start == &op_lit0)
1327 ra_state->loc.exp.start = &op_lit1;
1328 else
1329 ra_state->loc.exp.start = &op_lit0;
1330
1331 ra_state->loc.exp.len = 1;
1332
1333 return true;
1334 }
1335
1336 return false;
1337}
1338
5133a315
LM		 1339/* Used for matching BRK instructions for AArch64. */
1340static constexpr uint32_t BRK_INSN_MASK = 0xffe0001f;
1341static constexpr uint32_t BRK_INSN_BASE = 0xd4200000;
1342
1343/* Implementation of gdbarch_program_breakpoint_here_p for aarch64. */
1344
1345static bool
1346aarch64_program_breakpoint_here_p (gdbarch *gdbarch, CORE_ADDR address)
1347{
1348 const uint32_t insn_len = 4;
1349 gdb_byte target_mem[4];
1350
1351 /* Enable the automatic memory restoration from breakpoints while
1352 we read the memory. Otherwise we may find temporary breakpoints, ones
1353 inserted by GDB, and flag them as permanent breakpoints. */
1354 scoped_restore restore_memory
1355 = make_scoped_restore_show_memory_breakpoints (0);
1356
1357 if (target_read_memory (address, target_mem, insn_len) == 0)
1358 {
1359 uint32_t insn =
1360 (uint32_t) extract_unsigned_integer (target_mem, insn_len,
1361 gdbarch_byte_order_for_code (gdbarch));
1362
1363 /* Check if INSN is a BRK instruction pattern. There are multiple choices
1364 of such instructions with different immediate values. Different OS'
1365 may use a different variation, but they have the same outcome. */
1366 return ((insn & BRK_INSN_MASK) == BRK_INSN_BASE);
1367 }
1368
1369 return false;
1370}
1371
07b287a0
MS		 1372/* When arguments must be pushed onto the stack, they go on in reverse
1373 order. The code below implements a FILO (stack) to do this. */
1374
89055eaa 1375struct stack_item_t
07b287a0 1376{
c3c87445
YQ		 1377 /* Value to pass on stack. It can be NULL if this item is for stack
1378 padding. */
7c543f7b 1379 const gdb_byte *data;
07b287a0
MS		 1380
1381 /* Size in bytes of value to pass on stack. */
1382 int len;
89055eaa 1383};
07b287a0 1384
b907456c
AB		 1385/* Implement the gdbarch type alignment method, overrides the generic
1386 alignment algorithm for anything that is aarch64 specific. */
07b287a0 1387
b907456c
AB		 1388static ULONGEST
1389aarch64_type_align (gdbarch *gdbarch, struct type *t)
07b287a0 1390{
07b287a0 1391 t = check_typedef (t);
bd63c870 1392 if (t->code () == TYPE_CODE_ARRAY && t->is_vector ())
07b287a0 1393 {
b907456c
AB		 1394 /* Use the natural alignment for vector types (the same for
1395 scalar type), but the maximum alignment is 128-bit. */
1396 if (TYPE_LENGTH (t) > 16)
1397 return 16;
238f2452 1398 else
b907456c 1399 return TYPE_LENGTH (t);
07b287a0 1400 }
b907456c
AB		 1401
1402 /* Allow the common code to calculate the alignment. */
1403 return 0;
07b287a0
MS		 1404}
1405
ea92689a
AH		 1406/* Worker function for aapcs_is_vfp_call_or_return_candidate.
1407
1408 Return the number of register required, or -1 on failure.
1409
1410 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1411 to the element, else fail if the type of this element does not match the
1412 existing value. */
1413
1414static int
1415aapcs_is_vfp_call_or_return_candidate_1 (struct type *type,
1416 struct type **fundamental_type)
1417{
1418 if (type == nullptr)
1419 return -1;
1420
78134374 1421 switch (type->code ())
ea92689a
AH		 1422 {
1423 case TYPE_CODE_FLT:
1424 if (TYPE_LENGTH (type) > 16)
1425 return -1;
1426
1427 if (*fundamental_type == nullptr)
1428 *fundamental_type = type;
1429 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
78134374 1430 || type->code () != (*fundamental_type)->code ())
ea92689a
AH		 1431 return -1;
1432
1433 return 1;
1434
1435 case TYPE_CODE_COMPLEX:
1436 {
1437 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
1438 if (TYPE_LENGTH (target_type) > 16)
1439 return -1;
1440
1441 if (*fundamental_type == nullptr)
1442 *fundamental_type = target_type;
1443 else if (TYPE_LENGTH (target_type) != TYPE_LENGTH (*fundamental_type)
78134374 1444 || target_type->code () != (*fundamental_type)->code ())
ea92689a
AH		 1445 return -1;
1446
1447 return 2;
1448 }
1449
1450 case TYPE_CODE_ARRAY:
1451 {
bd63c870 1452 if (type->is_vector ())
ea92689a
AH		 1453 {
1454 if (TYPE_LENGTH (type) != 8 && TYPE_LENGTH (type) != 16)
1455 return -1;
1456
1457 if (*fundamental_type == nullptr)
1458 *fundamental_type = type;
1459 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
78134374 1460 || type->code () != (*fundamental_type)->code ())
ea92689a
AH		 1461 return -1;
1462
1463 return 1;
1464 }
1465 else
1466 {
1467 struct type *target_type = TYPE_TARGET_TYPE (type);
1468 int count = aapcs_is_vfp_call_or_return_candidate_1
1469 (target_type, fundamental_type);
1470
1471 if (count == -1)
1472 return count;
1473
d4718d5c 1474 count *= (TYPE_LENGTH (type) / TYPE_LENGTH (target_type));
ea92689a
AH		 1475 return count;
1476 }
1477 }
1478
1479 case TYPE_CODE_STRUCT:
1480 case TYPE_CODE_UNION:
1481 {
1482 int count = 0;
1483
1f704f76 1484 for (int i = 0; i < type->num_fields (); i++)
ea92689a 1485 {
353229bf 1486 /* Ignore any static fields. */
ceacbf6e 1487 if (field_is_static (&type->field (i)))
353229bf
AH		 1488 continue;
1489
940da03e 1490 struct type *member = check_typedef (type->field (i).type ());
ea92689a
AH		 1491
1492 int sub_count = aapcs_is_vfp_call_or_return_candidate_1
1493 (member, fundamental_type);
1494 if (sub_count == -1)
1495 return -1;
1496 count += sub_count;
1497 }
73021deb
AH		 1498
1499 /* Ensure there is no padding between the fields (allowing for empty
1500 zero length structs) */
1501 int ftype_length = (*fundamental_type == nullptr)
1502 ? 0 : TYPE_LENGTH (*fundamental_type);
1503 if (count * ftype_length != TYPE_LENGTH (type))
1504 return -1;
1505
ea92689a
AH		 1506 return count;
1507 }
1508
1509 default:
1510 break;
1511 }
1512
1513 return -1;
1514}
1515
1516/* Return true if an argument, whose type is described by TYPE, can be passed or
1517 returned in simd/fp registers, providing enough parameter passing registers
1518 are available. This is as described in the AAPCS64.
1519
1520 Upon successful return, *COUNT returns the number of needed registers,
1521 *FUNDAMENTAL_TYPE contains the type of those registers.
1522
1523 Candidate as per the AAPCS64 5.4.2.C is either a:
1524 - float.
1525 - short-vector.
1526 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1527 all the members are floats and has at most 4 members.
1528 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1529 all the members are short vectors and has at most 4 members.
1530 - Complex (7.1.1)
1531
1532 Note that HFAs and HVAs can include nested structures and arrays. */
1533
0e745c60 1534static bool
ea92689a
AH		 1535aapcs_is_vfp_call_or_return_candidate (struct type *type, int *count,
1536 struct type **fundamental_type)
1537{
1538 if (type == nullptr)
1539 return false;
1540
1541 *fundamental_type = nullptr;
1542
1543 int ag_count = aapcs_is_vfp_call_or_return_candidate_1 (type,
1544 fundamental_type);
1545
1546 if (ag_count > 0 && ag_count <= HA_MAX_NUM_FLDS)
1547 {
1548 *count = ag_count;
1549 return true;
1550 }
1551 else
1552 return false;
1553}
1554
07b287a0
MS		 1555/* AArch64 function call information structure. */
1556struct aarch64_call_info
1557{
1558 /* the current argument number. */
89055eaa 1559 unsigned argnum = 0;
07b287a0
MS		 1560
1561 /* The next general purpose register number, equivalent to NGRN as
1562 described in the AArch64 Procedure Call Standard. */
89055eaa 1563 unsigned ngrn = 0;
07b287a0
MS		 1564
1565 /* The next SIMD and floating point register number, equivalent to
1566 NSRN as described in the AArch64 Procedure Call Standard. */
89055eaa 1567 unsigned nsrn = 0;
07b287a0
MS		 1568
1569 /* The next stacked argument address, equivalent to NSAA as
1570 described in the AArch64 Procedure Call Standard. */
89055eaa 1571 unsigned nsaa = 0;
07b287a0
MS		 1572
1573 /* Stack item vector. */
89055eaa 1574 std::vector<stack_item_t> si;
07b287a0
MS		 1575};
1576
1577/* Pass a value in a sequence of consecutive X registers. The caller
30baf67b 1578 is responsible for ensuring sufficient registers are available. */
07b287a0
MS		 1579
1580static void
1581pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
1582 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1583 struct value *arg)
07b287a0
MS		 1584{
1585 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1586 int len = TYPE_LENGTH (type);
78134374 1587 enum type_code typecode = type->code ();
07b287a0 1588 int regnum = AARCH64_X0_REGNUM + info->ngrn;
8e80f9d1 1589 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1590
1591 info->argnum++;
1592
1593 while (len > 0)
1594 {
1595 int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE;
1596 CORE_ADDR regval = extract_unsigned_integer (buf, partial_len,
1597 byte_order);
1598
1599
1600 /* Adjust sub-word struct/union args when big-endian. */
1601 if (byte_order == BFD_ENDIAN_BIG
1602 && partial_len < X_REGISTER_SIZE
1603 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
1604 regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
1605
c6185dce
SM		 1606 aarch64_debug_printf ("arg %d in %s = 0x%s", info->argnum,
1607 gdbarch_register_name (gdbarch, regnum),
1608 phex (regval, X_REGISTER_SIZE));
1609
07b287a0
MS		 1610 regcache_cooked_write_unsigned (regcache, regnum, regval);
1611 len -= partial_len;
1612 buf += partial_len;
1613 regnum++;
1614 }
1615}
1616
1617/* Attempt to marshall a value in a V register. Return 1 if
1618 successful, or 0 if insufficient registers are available. This
1619 function, unlike the equivalent pass_in_x() function does not
1620 handle arguments spread across multiple registers. */
1621
1622static int
1623pass_in_v (struct gdbarch *gdbarch,
1624 struct regcache *regcache,
1625 struct aarch64_call_info *info,
0735fddd 1626 int len, const bfd_byte *buf)
07b287a0
MS		 1627{
1628 if (info->nsrn < 8)
1629 {
07b287a0 1630 int regnum = AARCH64_V0_REGNUM + info->nsrn;
3ff2c72e
AH		 1631 /* Enough space for a full vector register. */
1632 gdb_byte reg[register_size (gdbarch, regnum)];
1633 gdb_assert (len <= sizeof (reg));
07b287a0
MS		 1634
1635 info->argnum++;
1636 info->nsrn++;
1637
0735fddd
YQ		 1638 memset (reg, 0, sizeof (reg));
1639 /* PCS C.1, the argument is allocated to the least significant
1640 bits of V register. */
1641 memcpy (reg, buf, len);
b66f5587 1642 regcache->cooked_write (regnum, reg);
0735fddd 1643
c6185dce
SM		 1644 aarch64_debug_printf ("arg %d in %s", info->argnum,
1645 gdbarch_register_name (gdbarch, regnum));
1646
07b287a0
MS		 1647 return 1;
1648 }
1649 info->nsrn = 8;
1650 return 0;
1651}
1652
1653/* Marshall an argument onto the stack. */
1654
1655static void
1656pass_on_stack (struct aarch64_call_info *info, struct type *type,
8e80f9d1 1657 struct value *arg)
07b287a0 1658{
8e80f9d1 1659 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1660 int len = TYPE_LENGTH (type);
1661 int align;
1662 stack_item_t item;
1663
1664 info->argnum++;
1665
b907456c 1666 align = type_align (type);
07b287a0
MS		 1667
1668 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1669 Natural alignment of the argument's type. */
1670 align = align_up (align, 8);
1671
1672 /* The AArch64 PCS requires at most doubleword alignment. */
1673 if (align > 16)
1674 align = 16;
1675
c6185dce
SM		 1676 aarch64_debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
1677 info->nsaa);
07b287a0
MS		 1678
1679 item.len = len;
1680 item.data = buf;
89055eaa 1681 info->si.push_back (item);
07b287a0
MS		 1682
1683 info->nsaa += len;
1684 if (info->nsaa & (align - 1))
1685 {
1686 /* Push stack alignment padding. */
1687 int pad = align - (info->nsaa & (align - 1));
1688
1689 item.len = pad;
c3c87445 1690 item.data = NULL;
07b287a0 1691
89055eaa 1692 info->si.push_back (item);
07b287a0
MS		 1693 info->nsaa += pad;
1694 }
1695}
1696
1697/* Marshall an argument into a sequence of one or more consecutive X
1698 registers or, if insufficient X registers are available then onto
1699 the stack. */
1700
1701static void
1702pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache,
1703 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1704 struct value *arg)
07b287a0
MS		 1705{
1706 int len = TYPE_LENGTH (type);
1707 int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE;
1708
1709 /* PCS C.13 - Pass in registers if we have enough spare */
1710 if (info->ngrn + nregs <= 8)
1711 {
8e80f9d1 1712 pass_in_x (gdbarch, regcache, info, type, arg);
07b287a0
MS		 1713 info->ngrn += nregs;
1714 }
1715 else
1716 {
1717 info->ngrn = 8;
8e80f9d1 1718 pass_on_stack (info, type, arg);
07b287a0
MS		 1719 }
1720}
1721
0e745c60
AH		 1722/* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1723 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1724 registers. A return value of false is an error state as the value will have
1725 been partially passed to the stack. */
1726static bool
1727pass_in_v_vfp_candidate (struct gdbarch *gdbarch, struct regcache *regcache,
1728 struct aarch64_call_info *info, struct type *arg_type,
1729 struct value *arg)
07b287a0 1730{
78134374 1731 switch (arg_type->code ())
0e745c60
AH		 1732 {
1733 case TYPE_CODE_FLT:
1734 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1735 value_contents (arg));
1736 break;
1737
1738 case TYPE_CODE_COMPLEX:
1739 {
1740 const bfd_byte *buf = value_contents (arg);
1741 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (arg_type));
1742
1743 if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1744 buf))
1745 return false;
1746
1747 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1748 buf + TYPE_LENGTH (target_type));
1749 }
1750
1751 case TYPE_CODE_ARRAY:
bd63c870 1752 if (arg_type->is_vector ())
0e745c60
AH		 1753 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1754 value_contents (arg));
1755 /* fall through. */
1756
1757 case TYPE_CODE_STRUCT:
1758 case TYPE_CODE_UNION:
1f704f76 1759 for (int i = 0; i < arg_type->num_fields (); i++)
0e745c60 1760 {
353229bf 1761 /* Don't include static fields. */
ceacbf6e 1762 if (field_is_static (&arg_type->field (i)))
353229bf
AH		 1763 continue;
1764
0e745c60
AH		 1765 struct value *field = value_primitive_field (arg, 0, i, arg_type);
1766 struct type *field_type = check_typedef (value_type (field));
1767
1768 if (!pass_in_v_vfp_candidate (gdbarch, regcache, info, field_type,
1769 field))
1770 return false;
1771 }
1772 return true;
1773
1774 default:
1775 return false;
1776 }
07b287a0
MS		 1777}
1778
1779/* Implement the "push_dummy_call" gdbarch method. */
1780
1781static CORE_ADDR
1782aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1783 struct regcache *regcache, CORE_ADDR bp_addr,
1784 int nargs,
cf84fa6b
AH		 1785 struct value **args, CORE_ADDR sp,
1786 function_call_return_method return_method,
07b287a0
MS		 1787 CORE_ADDR struct_addr)
1788{
07b287a0 1789 int argnum;
07b287a0 1790 struct aarch64_call_info info;
07b287a0 1791
07b287a0
MS		 1792 /* We need to know what the type of the called function is in order
1793 to determine the number of named/anonymous arguments for the
1794 actual argument placement, and the return type in order to handle
1795 return value correctly.
1796
1797 The generic code above us views the decision of return in memory
1798 or return in registers as a two stage processes. The language
1799 handler is consulted first and may decide to return in memory (eg
1800 class with copy constructor returned by value), this will cause
1801 the generic code to allocate space AND insert an initial leading
1802 argument.
1803
1804 If the language code does not decide to pass in memory then the
1805 target code is consulted.
1806
1807 If the language code decides to pass in memory we want to move
1808 the pointer inserted as the initial argument from the argument
1809 list and into X8, the conventional AArch64 struct return pointer
38a72da0 1810 register. */
07b287a0
MS		 1811
1812 /* Set the return address. For the AArch64, the return breakpoint
1813 is always at BP_ADDR. */
1814 regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr);
1815
38a72da0
AH		 1816 /* If we were given an initial argument for the return slot, lose it. */
1817 if (return_method == return_method_hidden_param)
07b287a0
MS		 1818 {
1819 args++;
1820 nargs--;
1821 }
1822
1823 /* The struct_return pointer occupies X8. */
38a72da0 1824 if (return_method != return_method_normal)
07b287a0 1825 {
c6185dce
SM		 1826 aarch64_debug_printf ("struct return in %s = 0x%s",
1827 gdbarch_register_name
1828 (gdbarch, AARCH64_STRUCT_RETURN_REGNUM),
1829 paddress (gdbarch, struct_addr));
1830
07b287a0
MS		 1831 regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
1832 struct_addr);
1833 }
1834
1835 for (argnum = 0; argnum < nargs; argnum++)
1836 {
1837 struct value *arg = args[argnum];
0e745c60
AH		 1838 struct type *arg_type, *fundamental_type;
1839 int len, elements;
07b287a0
MS		 1840
1841 arg_type = check_typedef (value_type (arg));
1842 len = TYPE_LENGTH (arg_type);
1843
0e745c60
AH		 1844 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1845 if there are enough spare registers. */
1846 if (aapcs_is_vfp_call_or_return_candidate (arg_type, &elements,
1847 &fundamental_type))
1848 {
1849 if (info.nsrn + elements <= 8)
1850 {
1851 /* We know that we have sufficient registers available therefore
1852 this will never need to fallback to the stack. */
1853 if (!pass_in_v_vfp_candidate (gdbarch, regcache, &info, arg_type,
1854 arg))
1855 gdb_assert_not_reached ("Failed to push args");
1856 }
1857 else
1858 {
1859 info.nsrn = 8;
1860 pass_on_stack (&info, arg_type, arg);
1861 }
1862 continue;
1863 }
1864
78134374 1865 switch (arg_type->code ())
07b287a0
MS		 1866 {
1867 case TYPE_CODE_INT:
1868 case TYPE_CODE_BOOL:
1869 case TYPE_CODE_CHAR:
1870 case TYPE_CODE_RANGE:
1871 case TYPE_CODE_ENUM:
1872 if (len < 4)
1873 {
1874 /* Promote to 32 bit integer. */
c6d940a9 1875 if (arg_type->is_unsigned ())
07b287a0
MS		 1876 arg_type = builtin_type (gdbarch)->builtin_uint32;
1877 else
1878 arg_type = builtin_type (gdbarch)->builtin_int32;
1879 arg = value_cast (arg_type, arg);
1880 }
8e80f9d1 1881 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1882 break;
1883
07b287a0
MS		 1884 case TYPE_CODE_STRUCT:
1885 case TYPE_CODE_ARRAY:
1886 case TYPE_CODE_UNION:
0e745c60 1887 if (len > 16)
07b287a0
MS		 1888 {
1889 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1890 invisible reference. */
1891
1892 /* Allocate aligned storage. */
1893 sp = align_down (sp - len, 16);
1894
1895 /* Write the real data into the stack. */
1896 write_memory (sp, value_contents (arg), len);
1897
1898 /* Construct the indirection. */
1899 arg_type = lookup_pointer_type (arg_type);
1900 arg = value_from_pointer (arg_type, sp);
8e80f9d1 1901 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1902 }
1903 else
1904 /* PCS C.15 / C.18 multiple values pass. */
8e80f9d1 1905 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1906 break;
1907
1908 default:
8e80f9d1 1909 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1910 break;
1911 }
1912 }
1913
1914 /* Make sure stack retains 16 byte alignment. */
1915 if (info.nsaa & 15)
1916 sp -= 16 - (info.nsaa & 15);
1917
89055eaa 1918 while (!info.si.empty ())
07b287a0 1919 {
89055eaa 1920 const stack_item_t &si = info.si.back ();
07b287a0 1921
89055eaa
TT		 1922 sp -= si.len;
1923 if (si.data != NULL)
1924 write_memory (sp, si.data, si.len);
1925 info.si.pop_back ();
07b287a0
MS		 1926 }
1927
07b287a0
MS		 1928 /* Finally, update the SP register. */
1929 regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp);
1930
1931 return sp;
1932}
1933
1934/* Implement the "frame_align" gdbarch method. */
1935
1936static CORE_ADDR
1937aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1938{
1939 /* Align the stack to sixteen bytes. */
1940 return sp & ~(CORE_ADDR) 15;
1941}
1942
1943/* Return the type for an AdvSISD Q register. */
1944
1945static struct type *
1946aarch64_vnq_type (struct gdbarch *gdbarch)
1947{
1948 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1949
1950 if (tdep->vnq_type == NULL)
1951 {
1952 struct type *t;
1953 struct type *elem;
1954
1955 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1956 TYPE_CODE_UNION);
1957
1958 elem = builtin_type (gdbarch)->builtin_uint128;
1959 append_composite_type_field (t, "u", elem);
1960
1961 elem = builtin_type (gdbarch)->builtin_int128;
1962 append_composite_type_field (t, "s", elem);
1963
1964 tdep->vnq_type = t;
1965 }
1966
1967 return tdep->vnq_type;
1968}
1969
1970/* Return the type for an AdvSISD D register. */
1971
1972static struct type *
1973aarch64_vnd_type (struct gdbarch *gdbarch)
1974{
1975 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1976
1977 if (tdep->vnd_type == NULL)
1978 {
1979 struct type *t;
1980 struct type *elem;
1981
1982 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1983 TYPE_CODE_UNION);
1984
1985 elem = builtin_type (gdbarch)->builtin_double;
1986 append_composite_type_field (t, "f", elem);
1987
1988 elem = builtin_type (gdbarch)->builtin_uint64;
1989 append_composite_type_field (t, "u", elem);
1990
1991 elem = builtin_type (gdbarch)->builtin_int64;
1992 append_composite_type_field (t, "s", elem);
1993
1994 tdep->vnd_type = t;
1995 }
1996
1997 return tdep->vnd_type;
1998}
1999
2000/* Return the type for an AdvSISD S register. */
2001
2002static struct type *
2003aarch64_vns_type (struct gdbarch *gdbarch)
2004{
2005 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2006
2007 if (tdep->vns_type == NULL)
2008 {
2009 struct type *t;
2010 struct type *elem;
2011
2012 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
2013 TYPE_CODE_UNION);
2014
2015 elem = builtin_type (gdbarch)->builtin_float;
2016 append_composite_type_field (t, "f", elem);
2017
2018 elem = builtin_type (gdbarch)->builtin_uint32;
2019 append_composite_type_field (t, "u", elem);
2020
2021 elem = builtin_type (gdbarch)->builtin_int32;
2022 append_composite_type_field (t, "s", elem);
2023
2024 tdep->vns_type = t;
2025 }
2026
2027 return tdep->vns_type;
2028}
2029
2030/* Return the type for an AdvSISD H register. */
2031
2032static struct type *
2033aarch64_vnh_type (struct gdbarch *gdbarch)
2034{
2035 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2036
2037 if (tdep->vnh_type == NULL)
2038 {
2039 struct type *t;
2040 struct type *elem;
2041
2042 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
2043 TYPE_CODE_UNION);
2044
5291fe3c
SP		 2045 elem = builtin_type (gdbarch)->builtin_bfloat16;
2046 append_composite_type_field (t, "bf", elem);
2047
a6d0f249
AH		 2048 elem = builtin_type (gdbarch)->builtin_half;
2049 append_composite_type_field (t, "f", elem);
2050
07b287a0
MS		 2051 elem = builtin_type (gdbarch)->builtin_uint16;
2052 append_composite_type_field (t, "u", elem);
2053
2054 elem = builtin_type (gdbarch)->builtin_int16;
2055 append_composite_type_field (t, "s", elem);
2056
2057 tdep->vnh_type = t;
2058 }
2059
2060 return tdep->vnh_type;
2061}
2062
2063/* Return the type for an AdvSISD B register. */
2064
2065static struct type *
2066aarch64_vnb_type (struct gdbarch *gdbarch)
2067{
2068 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2069
2070 if (tdep->vnb_type == NULL)
2071 {
2072 struct type *t;
2073 struct type *elem;
2074
2075 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
2076 TYPE_CODE_UNION);
2077
2078 elem = builtin_type (gdbarch)->builtin_uint8;
2079 append_composite_type_field (t, "u", elem);
2080
2081 elem = builtin_type (gdbarch)->builtin_int8;
2082 append_composite_type_field (t, "s", elem);
2083
2084 tdep->vnb_type = t;
2085 }
2086
2087 return tdep->vnb_type;
2088}
2089
63bad7b6
AH		 2090/* Return the type for an AdvSISD V register. */
2091
2092static struct type *
2093aarch64_vnv_type (struct gdbarch *gdbarch)
2094{
2095 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2096
2097 if (tdep->vnv_type == NULL)
2098 {
09624f1f 2099 /* The other AArch64 pseudo registers (Q,D,H,S,B) refer to a single value
bffa1015
AH		 2100 slice from the non-pseudo vector registers. However NEON V registers
2101 are always vector registers, and need constructing as such. */
2102 const struct builtin_type *bt = builtin_type (gdbarch);
2103
63bad7b6
AH		 2104 struct type *t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnv",
2105 TYPE_CODE_UNION);
2106
bffa1015
AH		 2107 struct type *sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
2108 TYPE_CODE_UNION);
2109 append_composite_type_field (sub, "f",
2110 init_vector_type (bt->builtin_double, 2));
2111 append_composite_type_field (sub, "u",
2112 init_vector_type (bt->builtin_uint64, 2));
2113 append_composite_type_field (sub, "s",
2114 init_vector_type (bt->builtin_int64, 2));
2115 append_composite_type_field (t, "d", sub);
2116
2117 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
2118 TYPE_CODE_UNION);
2119 append_composite_type_field (sub, "f",
2120 init_vector_type (bt->builtin_float, 4));
2121 append_composite_type_field (sub, "u",
2122 init_vector_type (bt->builtin_uint32, 4));
2123 append_composite_type_field (sub, "s",
2124 init_vector_type (bt->builtin_int32, 4));
2125 append_composite_type_field (t, "s", sub);
2126
2127 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
2128 TYPE_CODE_UNION);
5291fe3c
SP		 2129 append_composite_type_field (sub, "bf",
2130 init_vector_type (bt->builtin_bfloat16, 8));
a6d0f249
AH		 2131 append_composite_type_field (sub, "f",
2132 init_vector_type (bt->builtin_half, 8));
bffa1015
AH		 2133 append_composite_type_field (sub, "u",
2134 init_vector_type (bt->builtin_uint16, 8));
2135 append_composite_type_field (sub, "s",
2136 init_vector_type (bt->builtin_int16, 8));
2137 append_composite_type_field (t, "h", sub);
2138
2139 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
2140 TYPE_CODE_UNION);
2141 append_composite_type_field (sub, "u",
2142 init_vector_type (bt->builtin_uint8, 16));
2143 append_composite_type_field (sub, "s",
2144 init_vector_type (bt->builtin_int8, 16));
2145 append_composite_type_field (t, "b", sub);
2146
2147 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
2148 TYPE_CODE_UNION);
2149 append_composite_type_field (sub, "u",
2150 init_vector_type (bt->builtin_uint128, 1));
2151 append_composite_type_field (sub, "s",
2152 init_vector_type (bt->builtin_int128, 1));
2153 append_composite_type_field (t, "q", sub);
63bad7b6
AH		 2154
2155 tdep->vnv_type = t;
2156 }
2157
2158 return tdep->vnv_type;
2159}
2160
07b287a0
MS		 2161/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
2162
2163static int
2164aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
2165{
34dcc7cf
AH		 2166 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2167
07b287a0
MS		 2168 if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30)
2169 return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0;
2170
2171 if (reg == AARCH64_DWARF_SP)
2172 return AARCH64_SP_REGNUM;
2173
2174 if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
2175 return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
2176
65d4cada
AH		 2177 if (reg == AARCH64_DWARF_SVE_VG)
2178 return AARCH64_SVE_VG_REGNUM;
2179
2180 if (reg == AARCH64_DWARF_SVE_FFR)
2181 return AARCH64_SVE_FFR_REGNUM;
2182
2183 if (reg >= AARCH64_DWARF_SVE_P0 && reg <= AARCH64_DWARF_SVE_P0 + 15)
2184 return AARCH64_SVE_P0_REGNUM + reg - AARCH64_DWARF_SVE_P0;
2185
2186 if (reg >= AARCH64_DWARF_SVE_Z0 && reg <= AARCH64_DWARF_SVE_Z0 + 15)
2187 return AARCH64_SVE_Z0_REGNUM + reg - AARCH64_DWARF_SVE_Z0;
2188
34dcc7cf
AH		 2189 if (tdep->has_pauth ())
2190 {
2191 if (reg >= AARCH64_DWARF_PAUTH_DMASK && reg <= AARCH64_DWARF_PAUTH_CMASK)
2192 return tdep->pauth_reg_base + reg - AARCH64_DWARF_PAUTH_DMASK;
2193
2194 if (reg == AARCH64_DWARF_PAUTH_RA_STATE)
2195 return tdep->pauth_ra_state_regnum;
2196 }
2197
07b287a0
MS		 2198 return -1;
2199}
07b287a0
MS		 2200
2201/* Implement the "print_insn" gdbarch method. */
2202
2203static int
2204aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
2205{
2206 info->symbols = NULL;
6394c606 2207 return default_print_insn (memaddr, info);
07b287a0
MS		 2208}
2209
2210/* AArch64 BRK software debug mode instruction.
2211 Note that AArch64 code is always little-endian.
2212 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
04180708 2213constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
07b287a0 2214
04180708 2215typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint;
07b287a0
MS		 2216
2217/* Extract from an array REGS containing the (raw) register state a
2218 function return value of type TYPE, and copy that, in virtual
2219 format, into VALBUF. */
2220
2221static void
2222aarch64_extract_return_value (struct type *type, struct regcache *regs,
2223 gdb_byte *valbuf)
2224{
ac7936df 2225 struct gdbarch *gdbarch = regs->arch ();
07b287a0 2226 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4f4aedeb
AH		 2227 int elements;
2228 struct type *fundamental_type;
07b287a0 2229
4f4aedeb
AH		 2230 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2231 &fundamental_type))
07b287a0 2232 {
4f4aedeb
AH		 2233 int len = TYPE_LENGTH (fundamental_type);
2234
2235 for (int i = 0; i < elements; i++)
2236 {
2237 int regno = AARCH64_V0_REGNUM + i;
3ff2c72e
AH		 2238 /* Enough space for a full vector register. */
2239 gdb_byte buf[register_size (gdbarch, regno)];
2240 gdb_assert (len <= sizeof (buf));
4f4aedeb 2241
c6185dce
SM		 2242 aarch64_debug_printf
2243 ("read HFA or HVA return value element %d from %s",
2244 i + 1, gdbarch_register_name (gdbarch, regno));
2245
4f4aedeb 2246 regs->cooked_read (regno, buf);
07b287a0 2247
4f4aedeb
AH		 2248 memcpy (valbuf, buf, len);
2249 valbuf += len;
2250 }
07b287a0 2251 }
78134374
SM		 2252 else if (type->code () == TYPE_CODE_INT
2253 || type->code () == TYPE_CODE_CHAR
2254 || type->code () == TYPE_CODE_BOOL
2255 || type->code () == TYPE_CODE_PTR
aa006118 2256 || TYPE_IS_REFERENCE (type)
78134374 2257 || type->code () == TYPE_CODE_ENUM)
07b287a0 2258 {
6471e7d2 2259 /* If the type is a plain integer, then the access is
07b287a0
MS		 2260 straight-forward. Otherwise we have to play around a bit
2261 more. */
2262 int len = TYPE_LENGTH (type);
2263 int regno = AARCH64_X0_REGNUM;
2264 ULONGEST tmp;
2265
2266 while (len > 0)
2267 {
2268 /* By using store_unsigned_integer we avoid having to do
2269 anything special for small big-endian values. */
2270 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2271 store_unsigned_integer (valbuf,
2272 (len > X_REGISTER_SIZE
2273 ? X_REGISTER_SIZE : len), byte_order, tmp);
2274 len -= X_REGISTER_SIZE;
2275 valbuf += X_REGISTER_SIZE;
2276 }
2277 }
07b287a0
MS		 2278 else
2279 {
2280 /* For a structure or union the behaviour is as if the value had
dda83cd7
SM		 2281 been stored to word-aligned memory and then loaded into
2282 registers with 64-bit load instruction(s). */
07b287a0
MS		 2283 int len = TYPE_LENGTH (type);
2284 int regno = AARCH64_X0_REGNUM;
2285 bfd_byte buf[X_REGISTER_SIZE];
2286
2287 while (len > 0)
2288 {
dca08e1f 2289 regs->cooked_read (regno++, buf);
07b287a0
MS		 2290 memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
2291 len -= X_REGISTER_SIZE;
2292 valbuf += X_REGISTER_SIZE;
2293 }
2294 }
2295}
2296
2297
2298/* Will a function return an aggregate type in memory or in a
2299 register? Return 0 if an aggregate type can be returned in a
2300 register, 1 if it must be returned in memory. */
2301
2302static int
2303aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2304{
f168693b 2305 type = check_typedef (type);
4f4aedeb
AH		 2306 int elements;
2307 struct type *fundamental_type;
07b287a0 2308
4f4aedeb
AH		 2309 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2310 &fundamental_type))
07b287a0 2311 {
cd635f74
YQ		 2312 /* v0-v7 are used to return values and one register is allocated
2313 for one member. However, HFA or HVA has at most four members. */
07b287a0
MS		 2314 return 0;
2315 }
2316
2317 if (TYPE_LENGTH (type) > 16)
2318 {
2319 /* PCS B.6 Aggregates larger than 16 bytes are passed by
dda83cd7 2320 invisible reference. */
07b287a0
MS		 2321
2322 return 1;
2323 }
2324
2325 return 0;
2326}
2327
2328/* Write into appropriate registers a function return value of type
2329 TYPE, given in virtual format. */
2330
2331static void
2332aarch64_store_return_value (struct type *type, struct regcache *regs,
2333 const gdb_byte *valbuf)
2334{
ac7936df 2335 struct gdbarch *gdbarch = regs->arch ();
07b287a0 2336 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4f4aedeb
AH		 2337 int elements;
2338 struct type *fundamental_type;
07b287a0 2339
4f4aedeb
AH		 2340 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2341 &fundamental_type))
07b287a0 2342 {
4f4aedeb
AH		 2343 int len = TYPE_LENGTH (fundamental_type);
2344
2345 for (int i = 0; i < elements; i++)
2346 {
2347 int regno = AARCH64_V0_REGNUM + i;
3ff2c72e
AH		 2348 /* Enough space for a full vector register. */
2349 gdb_byte tmpbuf[register_size (gdbarch, regno)];
2350 gdb_assert (len <= sizeof (tmpbuf));
4f4aedeb 2351
c6185dce
SM		 2352 aarch64_debug_printf
2353 ("write HFA or HVA return value element %d to %s",
2354 i + 1, gdbarch_register_name (gdbarch, regno));
07b287a0 2355
4f4aedeb
AH		 2356 memcpy (tmpbuf, valbuf,
2357 len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
2358 regs->cooked_write (regno, tmpbuf);
2359 valbuf += len;
2360 }
07b287a0 2361 }
78134374
SM		 2362 else if (type->code () == TYPE_CODE_INT
2363 || type->code () == TYPE_CODE_CHAR
2364 || type->code () == TYPE_CODE_BOOL
2365 || type->code () == TYPE_CODE_PTR
aa006118 2366 || TYPE_IS_REFERENCE (type)
78134374 2367 || type->code () == TYPE_CODE_ENUM)
07b287a0
MS		 2368 {
2369 if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
2370 {
2371 /* Values of one word or less are zero/sign-extended and
2372 returned in r0. */
2373 bfd_byte tmpbuf[X_REGISTER_SIZE];
2374 LONGEST val = unpack_long (type, valbuf);
2375
2376 store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
b66f5587 2377 regs->cooked_write (AARCH64_X0_REGNUM, tmpbuf);
07b287a0
MS		 2378 }
2379 else
2380 {
2381 /* Integral values greater than one word are stored in
2382 consecutive registers starting with r0. This will always
2383 be a multiple of the regiser size. */
2384 int len = TYPE_LENGTH (type);
2385 int regno = AARCH64_X0_REGNUM;
2386
2387 while (len > 0)
2388 {
b66f5587 2389 regs->cooked_write (regno++, valbuf);
07b287a0
MS		 2390 len -= X_REGISTER_SIZE;
2391 valbuf += X_REGISTER_SIZE;
2392 }
2393 }
2394 }
07b287a0
MS		 2395 else
2396 {
2397 /* For a structure or union the behaviour is as if the value had
2398 been stored to word-aligned memory and then loaded into
2399 registers with 64-bit load instruction(s). */
2400 int len = TYPE_LENGTH (type);
2401 int regno = AARCH64_X0_REGNUM;
2402 bfd_byte tmpbuf[X_REGISTER_SIZE];
2403
2404 while (len > 0)
2405 {
2406 memcpy (tmpbuf, valbuf,
2407 len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
b66f5587 2408 regs->cooked_write (regno++, tmpbuf);
07b287a0
MS		 2409 len -= X_REGISTER_SIZE;
2410 valbuf += X_REGISTER_SIZE;
2411 }
2412 }
2413}
2414
2415/* Implement the "return_value" gdbarch method. */
2416
2417static enum return_value_convention
2418aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
2419 struct type *valtype, struct regcache *regcache,
2420 gdb_byte *readbuf, const gdb_byte *writebuf)
2421{
07b287a0 2422
78134374
SM		 2423 if (valtype->code () == TYPE_CODE_STRUCT
2424 || valtype->code () == TYPE_CODE_UNION
2425 || valtype->code () == TYPE_CODE_ARRAY)
07b287a0
MS		 2426 {
2427 if (aarch64_return_in_memory (gdbarch, valtype))
2428 {
c6185dce 2429 aarch64_debug_printf ("return value in memory");
07b287a0
MS		 2430 return RETURN_VALUE_STRUCT_CONVENTION;
2431 }
2432 }
2433
2434 if (writebuf)
2435 aarch64_store_return_value (valtype, regcache, writebuf);
2436
2437 if (readbuf)
2438 aarch64_extract_return_value (valtype, regcache, readbuf);
2439
c6185dce 2440 aarch64_debug_printf ("return value in registers");
07b287a0
MS		 2441
2442 return RETURN_VALUE_REGISTER_CONVENTION;
2443}
2444
2445/* Implement the "get_longjmp_target" gdbarch method. */
2446
2447static int
2448aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2449{
2450 CORE_ADDR jb_addr;
2451 gdb_byte buf[X_REGISTER_SIZE];
2452 struct gdbarch *gdbarch = get_frame_arch (frame);
2453 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2454 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2455
2456 jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM);
2457
2458 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2459 X_REGISTER_SIZE))
2460 return 0;
2461
2462 *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order);
2463 return 1;
2464}
ea873d8e
PL		 2465
2466/* Implement the "gen_return_address" gdbarch method. */
2467
2468static void
2469aarch64_gen_return_address (struct gdbarch *gdbarch,
2470 struct agent_expr *ax, struct axs_value *value,
2471 CORE_ADDR scope)
2472{
2473 value->type = register_type (gdbarch, AARCH64_LR_REGNUM);
2474 value->kind = axs_lvalue_register;
2475 value->u.reg = AARCH64_LR_REGNUM;
2476}
07b287a0
MS		 2477\f
2478
2479/* Return the pseudo register name corresponding to register regnum. */
2480
2481static const char *
2482aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
2483{
63bad7b6
AH		 2484 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2485
07b287a0
MS		 2486 static const char *const q_name[] =
2487 {
2488 "q0", "q1", "q2", "q3",
2489 "q4", "q5", "q6", "q7",
2490 "q8", "q9", "q10", "q11",
2491 "q12", "q13", "q14", "q15",
2492 "q16", "q17", "q18", "q19",
2493 "q20", "q21", "q22", "q23",
2494 "q24", "q25", "q26", "q27",
2495 "q28", "q29", "q30", "q31",
2496 };
2497
2498 static const char *const d_name[] =
2499 {
2500 "d0", "d1", "d2", "d3",
2501 "d4", "d5", "d6", "d7",
2502 "d8", "d9", "d10", "d11",
2503 "d12", "d13", "d14", "d15",
2504 "d16", "d17", "d18", "d19",
2505 "d20", "d21", "d22", "d23",
2506 "d24", "d25", "d26", "d27",
2507 "d28", "d29", "d30", "d31",
2508 };
2509
2510 static const char *const s_name[] =
2511 {
2512 "s0", "s1", "s2", "s3",
2513 "s4", "s5", "s6", "s7",
2514 "s8", "s9", "s10", "s11",
2515 "s12", "s13", "s14", "s15",
2516 "s16", "s17", "s18", "s19",
2517 "s20", "s21", "s22", "s23",
2518 "s24", "s25", "s26", "s27",
2519 "s28", "s29", "s30", "s31",
2520 };
2521
2522 static const char *const h_name[] =
2523 {
2524 "h0", "h1", "h2", "h3",
2525 "h4", "h5", "h6", "h7",
2526 "h8", "h9", "h10", "h11",
2527 "h12", "h13", "h14", "h15",
2528 "h16", "h17", "h18", "h19",
2529 "h20", "h21", "h22", "h23",
2530 "h24", "h25", "h26", "h27",
2531 "h28", "h29", "h30", "h31",
2532 };
2533
2534 static const char *const b_name[] =
2535 {
2536 "b0", "b1", "b2", "b3",
2537 "b4", "b5", "b6", "b7",
2538 "b8", "b9", "b10", "b11",
2539 "b12", "b13", "b14", "b15",
2540 "b16", "b17", "b18", "b19",
2541 "b20", "b21", "b22", "b23",
2542 "b24", "b25", "b26", "b27",
2543 "b28", "b29", "b30", "b31",
2544 };
2545
34dcc7cf 2546 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2547
34dcc7cf
AH		 2548 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
2549 return q_name[p_regnum - AARCH64_Q0_REGNUM];
07b287a0 2550
34dcc7cf
AH		 2551 if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
2552 return d_name[p_regnum - AARCH64_D0_REGNUM];
07b287a0 2553
34dcc7cf
AH		 2554 if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
2555 return s_name[p_regnum - AARCH64_S0_REGNUM];
07b287a0 2556
34dcc7cf
AH		 2557 if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
2558 return h_name[p_regnum - AARCH64_H0_REGNUM];
07b287a0 2559
34dcc7cf
AH		 2560 if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
2561 return b_name[p_regnum - AARCH64_B0_REGNUM];
07b287a0 2562
63bad7b6
AH		 2563 if (tdep->has_sve ())
2564 {
2565 static const char *const sve_v_name[] =
2566 {
2567 "v0", "v1", "v2", "v3",
2568 "v4", "v5", "v6", "v7",
2569 "v8", "v9", "v10", "v11",
2570 "v12", "v13", "v14", "v15",
2571 "v16", "v17", "v18", "v19",
2572 "v20", "v21", "v22", "v23",
2573 "v24", "v25", "v26", "v27",
2574 "v28", "v29", "v30", "v31",
2575 };
2576
34dcc7cf
AH		 2577 if (p_regnum >= AARCH64_SVE_V0_REGNUM
2578 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2579 return sve_v_name[p_regnum - AARCH64_SVE_V0_REGNUM];
63bad7b6
AH		 2580 }
2581
34dcc7cf
AH		 2582 /* RA_STATE is used for unwinding only. Do not assign it a name - this
2583 prevents it from being read by methods such as
2584 mi_cmd_trace_frame_collected. */
2585 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2586 return "";
2587
07b287a0
MS		 2588 internal_error (__FILE__, __LINE__,
2589 _("aarch64_pseudo_register_name: bad register number %d"),
34dcc7cf 2590 p_regnum);
07b287a0
MS		 2591}
2592
2593/* Implement the "pseudo_register_type" tdesc_arch_data method. */
2594
2595static struct type *
2596aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2597{
63bad7b6
AH		 2598 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2599
34dcc7cf 2600 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2601
34dcc7cf 2602 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
07b287a0
MS		 2603 return aarch64_vnq_type (gdbarch);
2604
34dcc7cf 2605 if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
07b287a0
MS		 2606 return aarch64_vnd_type (gdbarch);
2607
34dcc7cf 2608 if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
07b287a0
MS		 2609 return aarch64_vns_type (gdbarch);
2610
34dcc7cf 2611 if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
07b287a0
MS		 2612 return aarch64_vnh_type (gdbarch);
2613
34dcc7cf 2614 if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
07b287a0
MS		 2615 return aarch64_vnb_type (gdbarch);
2616
34dcc7cf
AH		 2617 if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM
2618 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
63bad7b6
AH		 2619 return aarch64_vnv_type (gdbarch);
2620
34dcc7cf
AH		 2621 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2622 return builtin_type (gdbarch)->builtin_uint64;
2623
07b287a0
MS		 2624 internal_error (__FILE__, __LINE__,
2625 _("aarch64_pseudo_register_type: bad register number %d"),
34dcc7cf 2626 p_regnum);
07b287a0
MS		 2627}
2628
2629/* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2630
2631static int
2632aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2633 struct reggroup *group)
2634{
63bad7b6
AH		 2635 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2636
34dcc7cf 2637 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2638
34dcc7cf 2639 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
07b287a0 2640 return group == all_reggroup || group == vector_reggroup;
34dcc7cf 2641 else if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
07b287a0
MS		 2642 return (group == all_reggroup || group == vector_reggroup
2643 || group == float_reggroup);
34dcc7cf 2644 else if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
07b287a0
MS		 2645 return (group == all_reggroup || group == vector_reggroup
2646 || group == float_reggroup);
34dcc7cf 2647 else if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
07b287a0 2648 return group == all_reggroup || group == vector_reggroup;
34dcc7cf 2649 else if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
07b287a0 2650 return group == all_reggroup || group == vector_reggroup;
34dcc7cf
AH		 2651 else if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM
2652 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
63bad7b6 2653 return group == all_reggroup || group == vector_reggroup;
34dcc7cf
AH		 2654 /* RA_STATE is used for unwinding only. Do not assign it to any groups. */
2655 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2656 return 0;
07b287a0
MS		 2657
2658 return group == all_reggroup;
2659}
2660
3c5cd5c3
AH		 2661/* Helper for aarch64_pseudo_read_value. */
2662
2663static struct value *
63bad7b6
AH		 2664aarch64_pseudo_read_value_1 (struct gdbarch *gdbarch,
2665 readable_regcache *regcache, int regnum_offset,
3c5cd5c3
AH		 2666 int regsize, struct value *result_value)
2667{
3c5cd5c3
AH		 2668 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
2669
63bad7b6
AH		 2670 /* Enough space for a full vector register. */
2671 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2672 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2673
3c5cd5c3
AH		 2674 if (regcache->raw_read (v_regnum, reg_buf) != REG_VALID)
2675 mark_value_bytes_unavailable (result_value, 0,
2676 TYPE_LENGTH (value_type (result_value)));
2677 else
2678 memcpy (value_contents_raw (result_value), reg_buf, regsize);
63bad7b6 2679
3c5cd5c3
AH		 2680 return result_value;
2681 }
2682
07b287a0
MS		 2683/* Implement the "pseudo_register_read_value" gdbarch method. */
2684
2685static struct value *
3c5cd5c3 2686aarch64_pseudo_read_value (struct gdbarch *gdbarch, readable_regcache *regcache,
07b287a0
MS		 2687 int regnum)
2688{
63bad7b6 2689 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3c5cd5c3 2690 struct value *result_value = allocate_value (register_type (gdbarch, regnum));
07b287a0 2691
07b287a0
MS		 2692 VALUE_LVAL (result_value) = lval_register;
2693 VALUE_REGNUM (result_value) = regnum;
07b287a0
MS		 2694
2695 regnum -= gdbarch_num_regs (gdbarch);
2696
2697 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
63bad7b6
AH		 2698 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2699 regnum - AARCH64_Q0_REGNUM,
3c5cd5c3 2700 Q_REGISTER_SIZE, result_value);
07b287a0
MS		 2701
2702 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
63bad7b6
AH		 2703 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2704 regnum - AARCH64_D0_REGNUM,
3c5cd5c3 2705 D_REGISTER_SIZE, result_value);
07b287a0
MS		 2706
2707 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
63bad7b6
AH		 2708 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2709 regnum - AARCH64_S0_REGNUM,
3c5cd5c3 2710 S_REGISTER_SIZE, result_value);
07b287a0
MS		 2711
2712 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
63bad7b6
AH		 2713 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2714 regnum - AARCH64_H0_REGNUM,
3c5cd5c3 2715 H_REGISTER_SIZE, result_value);
07b287a0
MS		 2716
2717 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
63bad7b6
AH		 2718 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2719 regnum - AARCH64_B0_REGNUM,
3c5cd5c3 2720 B_REGISTER_SIZE, result_value);
07b287a0 2721
63bad7b6
AH		 2722 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2723 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2724 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2725 regnum - AARCH64_SVE_V0_REGNUM,
2726 V_REGISTER_SIZE, result_value);
2727
07b287a0
MS		 2728 gdb_assert_not_reached ("regnum out of bound");
2729}
2730
3c5cd5c3 2731/* Helper for aarch64_pseudo_write. */
07b287a0
MS		 2732
2733static void
63bad7b6
AH		 2734aarch64_pseudo_write_1 (struct gdbarch *gdbarch, struct regcache *regcache,
2735 int regnum_offset, int regsize, const gdb_byte *buf)
07b287a0 2736{
3c5cd5c3 2737 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
07b287a0 2738
63bad7b6
AH		 2739 /* Enough space for a full vector register. */
2740 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2741 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2742
07b287a0
MS		 2743 /* Ensure the register buffer is zero, we want gdb writes of the
2744 various 'scalar' pseudo registers to behavior like architectural
2745 writes, register width bytes are written the remainder are set to
2746 zero. */
63bad7b6 2747 memset (reg_buf, 0, register_size (gdbarch, AARCH64_V0_REGNUM));
07b287a0 2748
3c5cd5c3
AH		 2749 memcpy (reg_buf, buf, regsize);
2750 regcache->raw_write (v_regnum, reg_buf);
2751}
2752
2753/* Implement the "pseudo_register_write" gdbarch method. */
2754
2755static void
2756aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
2757 int regnum, const gdb_byte *buf)
2758{
63bad7b6 2759 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
07b287a0
MS		 2760 regnum -= gdbarch_num_regs (gdbarch);
2761
2762 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
63bad7b6
AH		 2763 return aarch64_pseudo_write_1 (gdbarch, regcache,
2764 regnum - AARCH64_Q0_REGNUM, Q_REGISTER_SIZE,
2765 buf);
07b287a0
MS		 2766
2767 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
63bad7b6
AH		 2768 return aarch64_pseudo_write_1 (gdbarch, regcache,
2769 regnum - AARCH64_D0_REGNUM, D_REGISTER_SIZE,
2770 buf);
07b287a0
MS		 2771
2772 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
63bad7b6
AH		 2773 return aarch64_pseudo_write_1 (gdbarch, regcache,
2774 regnum - AARCH64_S0_REGNUM, S_REGISTER_SIZE,
2775 buf);
07b287a0
MS		 2776
2777 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
63bad7b6
AH		 2778 return aarch64_pseudo_write_1 (gdbarch, regcache,
2779 regnum - AARCH64_H0_REGNUM, H_REGISTER_SIZE,
2780 buf);
07b287a0
MS		 2781
2782 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
63bad7b6
AH		 2783 return aarch64_pseudo_write_1 (gdbarch, regcache,
2784 regnum - AARCH64_B0_REGNUM, B_REGISTER_SIZE,
2785 buf);
2786
2787 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2788 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2789 return aarch64_pseudo_write_1 (gdbarch, regcache,
2790 regnum - AARCH64_SVE_V0_REGNUM,
2791 V_REGISTER_SIZE, buf);
07b287a0
MS		 2792
2793 gdb_assert_not_reached ("regnum out of bound");
2794}
2795
07b287a0
MS		 2796/* Callback function for user_reg_add. */
2797
2798static struct value *
2799value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
2800{
9a3c8263 2801 const int *reg_p = (const int *) baton;
07b287a0
MS		 2802
2803 return value_of_register (*reg_p, frame);
2804}
2805\f
2806
9404b58f
KM		 2807/* Implement the "software_single_step" gdbarch method, needed to
2808 single step through atomic sequences on AArch64. */
2809
a0ff9e1a 2810static std::vector<CORE_ADDR>
f5ea389a 2811aarch64_software_single_step (struct regcache *regcache)
9404b58f 2812{
ac7936df 2813 struct gdbarch *gdbarch = regcache->arch ();
9404b58f
KM		 2814 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2815 const int insn_size = 4;
2816 const int atomic_sequence_length = 16; /* Instruction sequence length. */
0187a92f 2817 CORE_ADDR pc = regcache_read_pc (regcache);
70ab8ccd 2818 CORE_ADDR breaks[2] = { CORE_ADDR_MAX, CORE_ADDR_MAX };
9404b58f
KM		 2819 CORE_ADDR loc = pc;
2820 CORE_ADDR closing_insn = 0;
2821 uint32_t insn = read_memory_unsigned_integer (loc, insn_size,
2822 byte_order_for_code);
2823 int index;
2824 int insn_count;
2825 int bc_insn_count = 0; /* Conditional branch instruction count. */
2826 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
f77ee802
YQ		 2827 aarch64_inst inst;
2828
561a72d4 2829 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2830 return {};
9404b58f
KM		 2831
2832 /* Look for a Load Exclusive instruction which begins the sequence. */
f77ee802 2833 if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
a0ff9e1a 2834 return {};
9404b58f
KM		 2835
2836 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2837 {
9404b58f
KM		 2838 loc += insn_size;
2839 insn = read_memory_unsigned_integer (loc, insn_size,
2840 byte_order_for_code);
2841
561a72d4 2842 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2843 return {};
9404b58f 2844 /* Check if the instruction is a conditional branch. */
f77ee802 2845 if (inst.opcode->iclass == condbranch)
9404b58f 2846 {
f77ee802
YQ		 2847 gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
2848
9404b58f 2849 if (bc_insn_count >= 1)
a0ff9e1a 2850 return {};
9404b58f
KM		 2851
2852 /* It is, so we'll try to set a breakpoint at the destination. */
f77ee802 2853 breaks[1] = loc + inst.operands[0].imm.value;
9404b58f
KM		 2854
2855 bc_insn_count++;
2856 last_breakpoint++;
2857 }
2858
2859 /* Look for the Store Exclusive which closes the atomic sequence. */
f77ee802 2860 if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
9404b58f
KM		 2861 {
2862 closing_insn = loc;
2863 break;
2864 }
2865 }
2866
2867 /* We didn't find a closing Store Exclusive instruction, fall back. */
2868 if (!closing_insn)
a0ff9e1a 2869 return {};
9404b58f
KM		 2870
2871 /* Insert breakpoint after the end of the atomic sequence. */
2872 breaks[0] = loc + insn_size;
2873
2874 /* Check for duplicated breakpoints, and also check that the second
2875 breakpoint is not within the atomic sequence. */
2876 if (last_breakpoint
2877 && (breaks[1] == breaks[0]
2878 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
2879 last_breakpoint = 0;
2880
a0ff9e1a
SM		 2881 std::vector<CORE_ADDR> next_pcs;
2882
9404b58f
KM		 2883 /* Insert the breakpoint at the end of the sequence, and one at the
2884 destination of the conditional branch, if it exists. */
2885 for (index = 0; index <= last_breakpoint; index++)
a0ff9e1a 2886 next_pcs.push_back (breaks[index]);
9404b58f 2887
93f9a11f 2888 return next_pcs;
9404b58f
KM		 2889}
2890
1152d984
SM		 2891struct aarch64_displaced_step_copy_insn_closure
2892 : public displaced_step_copy_insn_closure
b6542f81
YQ		 2893{
2894 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2895 is being displaced stepping. */
f0c702d4 2896 bool cond = false;
b6542f81 2897
0c271889
LM		 2898 /* PC adjustment offset after displaced stepping. If 0, then we don't
2899 write the PC back, assuming the PC is already the right address. */
cfba9872 2900 int32_t pc_adjust = 0;
b6542f81
YQ		 2901};
2902
2903/* Data when visiting instructions for displaced stepping. */
2904
2905struct aarch64_displaced_step_data
2906{
2907 struct aarch64_insn_data base;
2908
2909 /* The address where the instruction will be executed at. */
2910 CORE_ADDR new_addr;
2911 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
e935475c 2912 uint32_t insn_buf[AARCH64_DISPLACED_MODIFIED_INSNS];
b6542f81
YQ		 2913 /* Number of instructions in INSN_BUF. */
2914 unsigned insn_count;
2915 /* Registers when doing displaced stepping. */
2916 struct regcache *regs;
2917
1152d984 2918 aarch64_displaced_step_copy_insn_closure *dsc;
b6542f81
YQ		 2919};
2920
2921/* Implementation of aarch64_insn_visitor method "b". */
2922
2923static void
2924aarch64_displaced_step_b (const int is_bl, const int32_t offset,
2925 struct aarch64_insn_data *data)
2926{
2927 struct aarch64_displaced_step_data *dsd
2928 = (struct aarch64_displaced_step_data *) data;
2ac09a5b 2929 int64_t new_offset = data->insn_addr - dsd->new_addr + offset;
b6542f81
YQ		 2930
2931 if (can_encode_int32 (new_offset, 28))
2932 {
2933 /* Emit B rather than BL, because executing BL on a new address
2934 will get the wrong address into LR. In order to avoid this,
2935 we emit B, and update LR if the instruction is BL. */
2936 emit_b (dsd->insn_buf, 0, new_offset);
2937 dsd->insn_count++;
2938 }
2939 else
2940 {
2941 /* Write NOP. */
2942 emit_nop (dsd->insn_buf);
2943 dsd->insn_count++;
2944 dsd->dsc->pc_adjust = offset;
2945 }
2946
2947 if (is_bl)
2948 {
2949 /* Update LR. */
2950 regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
2951 data->insn_addr + 4);
2952 }
2953}
2954
2955/* Implementation of aarch64_insn_visitor method "b_cond". */
2956
2957static void
2958aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
2959 struct aarch64_insn_data *data)
2960{
2961 struct aarch64_displaced_step_data *dsd
2962 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2963
2964 /* GDB has to fix up PC after displaced step this instruction
2965 differently according to the condition is true or false. Instead
2966 of checking COND against conditional flags, we can use
2967 the following instructions, and GDB can tell how to fix up PC
2968 according to the PC value.
2969
2970 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2971 INSN1 ;
2972 TAKEN:
2973 INSN2
2974 */
2975
2976 emit_bcond (dsd->insn_buf, cond, 8);
f0c702d4 2977 dsd->dsc->cond = true;
b6542f81
YQ		 2978 dsd->dsc->pc_adjust = offset;
2979 dsd->insn_count = 1;
2980}
2981
2982/* Dynamically allocate a new register. If we know the register
2983 statically, we should make it a global as above instead of using this
2984 helper function. */
2985
2986static struct aarch64_register
2987aarch64_register (unsigned num, int is64)
2988{
2989 return (struct aarch64_register) { num, is64 };
2990}
2991
2992/* Implementation of aarch64_insn_visitor method "cb". */
2993
2994static void
2995aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
2996 const unsigned rn, int is64,
2997 struct aarch64_insn_data *data)
2998{
2999 struct aarch64_displaced_step_data *dsd
3000 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 3001
3002 /* The offset is out of range for a compare and branch
3003 instruction. We can use the following instructions instead:
3004
3005 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
3006 INSN1 ;
3007 TAKEN:
3008 INSN2
3009 */
3010 emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
3011 dsd->insn_count = 1;
f0c702d4 3012 dsd->dsc->cond = true;
b6542f81
YQ		 3013 dsd->dsc->pc_adjust = offset;
3014}
3015
3016/* Implementation of aarch64_insn_visitor method "tb". */
3017
3018static void
3019aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
3020 const unsigned rt, unsigned bit,
3021 struct aarch64_insn_data *data)
3022{
3023 struct aarch64_displaced_step_data *dsd
3024 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 3025
3026 /* The offset is out of range for a test bit and branch
3027 instruction We can use the following instructions instead:
3028
3029 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
3030 INSN1 ;
3031 TAKEN:
3032 INSN2
3033
3034 */
3035 emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
3036 dsd->insn_count = 1;
f0c702d4 3037 dsd->dsc->cond = true;
b6542f81
YQ		 3038 dsd->dsc->pc_adjust = offset;
3039}
3040
3041/* Implementation of aarch64_insn_visitor method "adr". */
3042
3043static void
3044aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
3045 const int is_adrp, struct aarch64_insn_data *data)
3046{
3047 struct aarch64_displaced_step_data *dsd
3048 = (struct aarch64_displaced_step_data *) data;
3049 /* We know exactly the address the ADR{P,} instruction will compute.
3050 We can just write it to the destination register. */
3051 CORE_ADDR address = data->insn_addr + offset;
3052
3053 if (is_adrp)
3054 {
3055 /* Clear the lower 12 bits of the offset to get the 4K page. */
3056 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
3057 address & ~0xfff);
3058 }
3059 else
3060 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
3061 address);
3062
3063 dsd->dsc->pc_adjust = 4;
3064 emit_nop (dsd->insn_buf);
3065 dsd->insn_count = 1;
3066}
3067
3068/* Implementation of aarch64_insn_visitor method "ldr_literal". */
3069
3070static void
3071aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
3072 const unsigned rt, const int is64,
3073 struct aarch64_insn_data *data)
3074{
3075 struct aarch64_displaced_step_data *dsd
3076 = (struct aarch64_displaced_step_data *) data;
3077 CORE_ADDR address = data->insn_addr + offset;
3078 struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 };
3079
3080 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt,
3081 address);
3082
3083 if (is_sw)
3084 dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1),
3085 aarch64_register (rt, 1), zero);
3086 else
3087 dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64),
3088 aarch64_register (rt, 1), zero);
3089
3090 dsd->dsc->pc_adjust = 4;
3091}
3092
3093/* Implementation of aarch64_insn_visitor method "others". */
3094
3095static void
3096aarch64_displaced_step_others (const uint32_t insn,
3097 struct aarch64_insn_data *data)
3098{
3099 struct aarch64_displaced_step_data *dsd
3100 = (struct aarch64_displaced_step_data *) data;
3101
807f647c
MM		 3102 uint32_t masked_insn = (insn & CLEAR_Rn_MASK);
3103 if (masked_insn == BLR)
b6542f81 3104 {
807f647c
MM		 3105 /* Emit a BR to the same register and then update LR to the original
3106 address (similar to aarch64_displaced_step_b). */
3107 aarch64_emit_insn (dsd->insn_buf, insn & 0xffdfffff);
3108 regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
3109 data->insn_addr + 4);
b6542f81 3110 }
807f647c
MM		 3111 else
3112 aarch64_emit_insn (dsd->insn_buf, insn);
3113 dsd->insn_count = 1;
3114
3115 if (masked_insn == RET || masked_insn == BR || masked_insn == BLR)
3116 dsd->dsc->pc_adjust = 0;
b6542f81
YQ		 3117 else
3118 dsd->dsc->pc_adjust = 4;
3119}
3120
3121static const struct aarch64_insn_visitor visitor =
3122{
3123 aarch64_displaced_step_b,
3124 aarch64_displaced_step_b_cond,
3125 aarch64_displaced_step_cb,
3126 aarch64_displaced_step_tb,
3127 aarch64_displaced_step_adr,
3128 aarch64_displaced_step_ldr_literal,
3129 aarch64_displaced_step_others,
3130};
3131
3132/* Implement the "displaced_step_copy_insn" gdbarch method. */
3133
1152d984 3134displaced_step_copy_insn_closure_up
b6542f81
YQ		 3135aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
3136 CORE_ADDR from, CORE_ADDR to,
3137 struct regcache *regs)
3138{
b6542f81
YQ		 3139 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3140 uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
3141 struct aarch64_displaced_step_data dsd;
c86a40c6
YQ		 3142 aarch64_inst inst;
3143
561a72d4 3144 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
c86a40c6 3145 return NULL;
b6542f81
YQ		 3146
3147 /* Look for a Load Exclusive instruction which begins the sequence. */
c86a40c6 3148 if (inst.opcode->iclass == ldstexcl && bit (insn, 22))
b6542f81
YQ		 3149 {
3150 /* We can't displaced step atomic sequences. */
3151 return NULL;
3152 }
3153
1152d984
SM		 3154 std::unique_ptr<aarch64_displaced_step_copy_insn_closure> dsc
3155 (new aarch64_displaced_step_copy_insn_closure);
b6542f81
YQ		 3156 dsd.base.insn_addr = from;
3157 dsd.new_addr = to;
3158 dsd.regs = regs;
cfba9872 3159 dsd.dsc = dsc.get ();
034f1a81 3160 dsd.insn_count = 0;
b6542f81
YQ		 3161 aarch64_relocate_instruction (insn, &visitor,
3162 (struct aarch64_insn_data *) &dsd);
e935475c 3163 gdb_assert (dsd.insn_count <= AARCH64_DISPLACED_MODIFIED_INSNS);
b6542f81
YQ		 3164
3165 if (dsd.insn_count != 0)
3166 {
3167 int i;
3168
3169 /* Instruction can be relocated to scratch pad. Copy
3170 relocated instruction(s) there. */
3171 for (i = 0; i < dsd.insn_count; i++)
3172 {
136821d9
SM		 3173 displaced_debug_printf ("writing insn %.8x at %s",
3174 dsd.insn_buf[i],
3175 paddress (gdbarch, to + i * 4));
3176
b6542f81
YQ		 3177 write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
3178 (ULONGEST) dsd.insn_buf[i]);
3179 }
3180 }
3181 else
3182 {
b6542f81
YQ		 3183 dsc = NULL;
3184 }
3185
6d0cf446 3186 /* This is a work around for a problem with g++ 4.8. */
1152d984 3187 return displaced_step_copy_insn_closure_up (dsc.release ());
b6542f81
YQ		 3188}
3189
3190/* Implement the "displaced_step_fixup" gdbarch method. */
3191
3192void
3193aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
1152d984 3194 struct displaced_step_copy_insn_closure *dsc_,
b6542f81
YQ		 3195 CORE_ADDR from, CORE_ADDR to,
3196 struct regcache *regs)
3197{
1152d984
SM		 3198 aarch64_displaced_step_copy_insn_closure *dsc
3199 = (aarch64_displaced_step_copy_insn_closure *) dsc_;
cfba9872 3200
0c271889
LM		 3201 ULONGEST pc;
3202
3203 regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
3204
136821d9
SM		 3205 displaced_debug_printf ("PC after stepping: %s (was %s).",
3206 paddress (gdbarch, pc), paddress (gdbarch, to));
1ab139e5 3207
b6542f81
YQ		 3208 if (dsc->cond)
3209 {
136821d9
SM		 3210 displaced_debug_printf ("[Conditional] pc_adjust before: %d",
3211 dsc->pc_adjust);
1ab139e5 3212
b6542f81
YQ		 3213 if (pc - to == 8)
3214 {
3215 /* Condition is true. */
3216 }
3217 else if (pc - to == 4)
3218 {
3219 /* Condition is false. */
3220 dsc->pc_adjust = 4;
3221 }
3222 else
3223 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
1ab139e5 3224
136821d9
SM		 3225 displaced_debug_printf ("[Conditional] pc_adjust after: %d",
3226 dsc->pc_adjust);
b6542f81
YQ		 3227 }
3228
136821d9
SM		 3229 displaced_debug_printf ("%s PC by %d",
3230 dsc->pc_adjust ? "adjusting" : "not adjusting",
3231 dsc->pc_adjust);
1ab139e5 3232
b6542f81
YQ		 3233 if (dsc->pc_adjust != 0)
3234 {
0c271889
LM		 3235 /* Make sure the previous instruction was executed (that is, the PC
3236 has changed). If the PC didn't change, then discard the adjustment
3237 offset. Otherwise we may skip an instruction before its execution
3238 took place. */
3239 if ((pc - to) == 0)
1ab139e5 3240 {
136821d9 3241 displaced_debug_printf ("PC did not move. Discarding PC adjustment.");
1ab139e5
LM		 3242 dsc->pc_adjust = 0;
3243 }
0c271889 3244
136821d9
SM		 3245 displaced_debug_printf ("fixup: set PC to %s:%d",
3246 paddress (gdbarch, from), dsc->pc_adjust);
3247
b6542f81
YQ		 3248 regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
3249 from + dsc->pc_adjust);
3250 }
3251}
3252
3253/* Implement the "displaced_step_hw_singlestep" gdbarch method. */
3254
07fbbd01 3255bool
40a53766 3256aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch)
b6542f81 3257{
07fbbd01 3258 return true;
b6542f81
YQ		 3259}
3260
95228a0d
AH		 3261/* Get the correct target description for the given VQ value.
3262 If VQ is zero then it is assumed SVE is not supported.
3263 (It is not possible to set VQ to zero on an SVE system). */
da434ccb
AH		 3264
3265const target_desc *
6dc0ebde 3266aarch64_read_description (uint64_t vq, bool pauth_p)
da434ccb 3267{
95228a0d 3268 if (vq > AARCH64_MAX_SVE_VQ)
39bfb937 3269 error (_("VQ is %" PRIu64 ", maximum supported value is %d"), vq,
95228a0d
AH		 3270 AARCH64_MAX_SVE_VQ);
3271
6dc0ebde 3272 struct target_desc *tdesc = tdesc_aarch64_list[vq][pauth_p];
da434ccb 3273
95228a0d
AH		 3274 if (tdesc == NULL)
3275 {
6dc0ebde
AH		 3276 tdesc = aarch64_create_target_description (vq, pauth_p);
3277 tdesc_aarch64_list[vq][pauth_p] = tdesc;
95228a0d 3278 }
da434ccb 3279
95228a0d 3280 return tdesc;
da434ccb
AH		 3281}
3282
ba2d2bb2
AH		 3283/* Return the VQ used when creating the target description TDESC. */
3284
1332a140 3285static uint64_t
ba2d2bb2
AH		 3286aarch64_get_tdesc_vq (const struct target_desc *tdesc)
3287{
3288 const struct tdesc_feature *feature_sve;
3289
3290 if (!tdesc_has_registers (tdesc))
3291 return 0;
3292
3293 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
3294
3295 if (feature_sve == nullptr)
3296 return 0;
3297
12863263
AH		 3298 uint64_t vl = tdesc_register_bitsize (feature_sve,
3299 aarch64_sve_register_names[0]) / 8;
ba2d2bb2
AH		 3300 return sve_vq_from_vl (vl);
3301}
3302
0ef8a082
AH		 3303/* Add all the expected register sets into GDBARCH. */
3304
3305static void
3306aarch64_add_reggroups (struct gdbarch *gdbarch)
3307{
3308 reggroup_add (gdbarch, general_reggroup);
3309 reggroup_add (gdbarch, float_reggroup);
3310 reggroup_add (gdbarch, system_reggroup);
3311 reggroup_add (gdbarch, vector_reggroup);
3312 reggroup_add (gdbarch, all_reggroup);
3313 reggroup_add (gdbarch, save_reggroup);
3314 reggroup_add (gdbarch, restore_reggroup);
3315}
ba2d2bb2 3316
76bed0fd
AH		 3317/* Implement the "cannot_store_register" gdbarch method. */
3318
3319static int
3320aarch64_cannot_store_register (struct gdbarch *gdbarch, int regnum)
3321{
3322 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3323
3324 if (!tdep->has_pauth ())
3325 return 0;
3326
3327 /* Pointer authentication registers are read-only. */
3328 return (regnum == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
3329 || regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base));
3330}
3331
07b287a0
MS		 3332/* Initialize the current architecture based on INFO. If possible,
3333 re-use an architecture from ARCHES, which is a list of
3334 architectures already created during this debugging session.
3335
3336 Called e.g. at program startup, when reading a core file, and when
3337 reading a binary file. */
3338
3339static struct gdbarch *
3340aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3341{
ccb8d7e8 3342 const struct tdesc_feature *feature_core, *feature_fpu, *feature_sve;
76bed0fd 3343 const struct tdesc_feature *feature_pauth;
ccb8d7e8
AH		 3344 bool valid_p = true;
3345 int i, num_regs = 0, num_pseudo_regs = 0;
3346 int first_pauth_regnum = -1, pauth_ra_state_offset = -1;
3347
4da037ef
AH		 3348 /* Use the vector length passed via the target info. Here -1 is used for no
3349 SVE, and 0 is unset. If unset then use the vector length from the existing
3350 tdesc. */
3351 uint64_t vq = 0;
3352 if (info.id == (int *) -1)
3353 vq = 0;
3354 else if (info.id != 0)
3355 vq = (uint64_t) info.id;
3356 else
3357 vq = aarch64_get_tdesc_vq (info.target_desc);
3358
3359 if (vq > AARCH64_MAX_SVE_VQ)
596179f7
SDJ		 3360 internal_error (__FILE__, __LINE__, _("VQ out of bounds: %s (max %d)"),
3361 pulongest (vq), AARCH64_MAX_SVE_VQ);
4da037ef 3362
ccb8d7e8
AH		 3363 /* If there is already a candidate, use it. */
3364 for (gdbarch_list *best_arch = gdbarch_list_lookup_by_info (arches, &info);
3365 best_arch != nullptr;
3366 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
3367 {
3368 struct gdbarch_tdep *tdep = gdbarch_tdep (best_arch->gdbarch);
4da037ef 3369 if (tdep && tdep->vq == vq)
ccb8d7e8
AH		 3370 return best_arch->gdbarch;
3371 }
07b287a0 3372
4da037ef
AH		 3373 /* Ensure we always have a target descriptor, and that it is for the given VQ
3374 value. */
ccb8d7e8 3375 const struct target_desc *tdesc = info.target_desc;
4da037ef
AH		 3376 if (!tdesc_has_registers (tdesc) || vq != aarch64_get_tdesc_vq (tdesc))
3377 tdesc = aarch64_read_description (vq, false);
07b287a0
MS		 3378 gdb_assert (tdesc);
3379
ccb8d7e8 3380 feature_core = tdesc_find_feature (tdesc,"org.gnu.gdb.aarch64.core");
ba2d2bb2
AH		 3381 feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
3382 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
76bed0fd 3383 feature_pauth = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.pauth");
07b287a0 3384
ccb8d7e8
AH		 3385 if (feature_core == nullptr)
3386 return nullptr;
07b287a0 3387
c1e1314d 3388 tdesc_arch_data_up tdesc_data = tdesc_data_alloc ();
07b287a0 3389
ba2d2bb2 3390 /* Validate the description provides the mandatory core R registers
07b287a0
MS		 3391 and allocate their numbers. */
3392 for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
c1e1314d 3393 valid_p &= tdesc_numbered_register (feature_core, tdesc_data.get (),
ba2d2bb2
AH		 3394 AARCH64_X0_REGNUM + i,
3395 aarch64_r_register_names[i]);
07b287a0
MS		 3396
3397 num_regs = AARCH64_X0_REGNUM + i;
3398
ba2d2bb2 3399 /* Add the V registers. */
ccb8d7e8 3400 if (feature_fpu != nullptr)
07b287a0 3401 {
ccb8d7e8 3402 if (feature_sve != nullptr)
ba2d2bb2
AH		 3403 error (_("Program contains both fpu and SVE features."));
3404
3405 /* Validate the description provides the mandatory V registers
3406 and allocate their numbers. */
07b287a0 3407 for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
c1e1314d 3408 valid_p &= tdesc_numbered_register (feature_fpu, tdesc_data.get (),
ba2d2bb2
AH		 3409 AARCH64_V0_REGNUM + i,
3410 aarch64_v_register_names[i]);
07b287a0
MS		 3411
3412 num_regs = AARCH64_V0_REGNUM + i;
ba2d2bb2 3413 }
07b287a0 3414
ba2d2bb2 3415 /* Add the SVE registers. */
ccb8d7e8 3416 if (feature_sve != nullptr)
ba2d2bb2
AH		 3417 {
3418 /* Validate the description provides the mandatory SVE registers
3419 and allocate their numbers. */
3420 for (i = 0; i < ARRAY_SIZE (aarch64_sve_register_names); i++)
c1e1314d 3421 valid_p &= tdesc_numbered_register (feature_sve, tdesc_data.get (),
ba2d2bb2
AH		 3422 AARCH64_SVE_Z0_REGNUM + i,
3423 aarch64_sve_register_names[i]);
3424
3425 num_regs = AARCH64_SVE_Z0_REGNUM + i;
3426 num_pseudo_regs += 32; /* add the Vn register pseudos. */
3427 }
3428
ccb8d7e8 3429 if (feature_fpu != nullptr || feature_sve != nullptr)
ba2d2bb2 3430 {
07b287a0
MS		 3431 num_pseudo_regs += 32; /* add the Qn scalar register pseudos */
3432 num_pseudo_regs += 32; /* add the Dn scalar register pseudos */
3433 num_pseudo_regs += 32; /* add the Sn scalar register pseudos */
3434 num_pseudo_regs += 32; /* add the Hn scalar register pseudos */
3435 num_pseudo_regs += 32; /* add the Bn scalar register pseudos */
3436 }
3437
76bed0fd
AH		 3438 /* Add the pauth registers. */
3439 if (feature_pauth != NULL)
3440 {
3441 first_pauth_regnum = num_regs;
34dcc7cf 3442 pauth_ra_state_offset = num_pseudo_regs;
76bed0fd
AH		 3443 /* Validate the descriptor provides the mandatory PAUTH registers and
3444 allocate their numbers. */
3445 for (i = 0; i < ARRAY_SIZE (aarch64_pauth_register_names); i++)
c1e1314d 3446 valid_p &= tdesc_numbered_register (feature_pauth, tdesc_data.get (),
76bed0fd
AH		 3447 first_pauth_regnum + i,
3448 aarch64_pauth_register_names[i]);
3449
3450 num_regs += i;
34dcc7cf 3451 num_pseudo_regs += 1; /* Count RA_STATE pseudo register. */
76bed0fd
AH		 3452 }
3453
07b287a0 3454 if (!valid_p)
c1e1314d 3455 return nullptr;
07b287a0
MS		 3456
3457 /* AArch64 code is always little-endian. */
3458 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
3459
ccb8d7e8
AH		 3460 struct gdbarch_tdep *tdep = XCNEW (struct gdbarch_tdep);
3461 struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep);
07b287a0
MS		 3462
3463 /* This should be low enough for everything. */
3464 tdep->lowest_pc = 0x20;
3465 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
3466 tdep->jb_elt_size = 8;
4da037ef 3467 tdep->vq = vq;
76bed0fd 3468 tdep->pauth_reg_base = first_pauth_regnum;
34dcc7cf
AH		 3469 tdep->pauth_ra_state_regnum = (feature_pauth == NULL) ? -1
3470 : pauth_ra_state_offset + num_regs;
3471
07b287a0
MS		 3472 set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
3473 set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
3474
07b287a0
MS		 3475 /* Advance PC across function entry code. */
3476 set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue);
3477
3478 /* The stack grows downward. */
3479 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3480
3481 /* Breakpoint manipulation. */
04180708
YQ		 3482 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
3483 aarch64_breakpoint::kind_from_pc);
3484 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
3485 aarch64_breakpoint::bp_from_kind);
07b287a0 3486 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
9404b58f 3487 set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step);
07b287a0
MS		 3488
3489 /* Information about registers, etc. */
3490 set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM);
3491 set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM);
3492 set_gdbarch_num_regs (gdbarch, num_regs);
3493
3494 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
3495 set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value);
3496 set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write);
3497 set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name);
3498 set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type);
3499 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3500 aarch64_pseudo_register_reggroup_p);
76bed0fd 3501 set_gdbarch_cannot_store_register (gdbarch, aarch64_cannot_store_register);
07b287a0
MS		 3502
3503 /* ABI */
3504 set_gdbarch_short_bit (gdbarch, 16);
3505 set_gdbarch_int_bit (gdbarch, 32);
3506 set_gdbarch_float_bit (gdbarch, 32);
3507 set_gdbarch_double_bit (gdbarch, 64);
3508 set_gdbarch_long_double_bit (gdbarch, 128);
3509 set_gdbarch_long_bit (gdbarch, 64);
3510 set_gdbarch_long_long_bit (gdbarch, 64);
3511 set_gdbarch_ptr_bit (gdbarch, 64);
3512 set_gdbarch_char_signed (gdbarch, 0);
53375380 3513 set_gdbarch_wchar_signed (gdbarch, 0);
07b287a0
MS		 3514 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
3515 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3516 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
b907456c 3517 set_gdbarch_type_align (gdbarch, aarch64_type_align);
07b287a0
MS		 3518
3519 /* Internal <-> external register number maps. */
3520 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum);
3521
3522 /* Returning results. */
3523 set_gdbarch_return_value (gdbarch, aarch64_return_value);
3524
3525 /* Disassembly. */
3526 set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn);
3527
3528 /* Virtual tables. */
3529 set_gdbarch_vbit_in_delta (gdbarch, 1);
3530
0ef8a082
AH		 3531 /* Register architecture. */
3532 aarch64_add_reggroups (gdbarch);
3533
07b287a0
MS		 3534 /* Hook in the ABI-specific overrides, if they have been registered. */
3535 info.target_desc = tdesc;
c1e1314d 3536 info.tdesc_data = tdesc_data.get ();
07b287a0
MS		 3537 gdbarch_init_osabi (info, gdbarch);
3538
3539 dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
11e1b75f
AH		 3540 /* Register DWARF CFA vendor handler. */
3541 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch,
3542 aarch64_execute_dwarf_cfa_vendor_op);
07b287a0 3543
5133a315
LM		 3544 /* Permanent/Program breakpoint handling. */
3545 set_gdbarch_program_breakpoint_here_p (gdbarch,
3546 aarch64_program_breakpoint_here_p);
3547
07b287a0
MS		 3548 /* Add some default predicates. */
3549 frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind);
3550 dwarf2_append_unwinders (gdbarch);
3551 frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind);
3552
3553 frame_base_set_default (gdbarch, &aarch64_normal_base);
3554
3555 /* Now we have tuned the configuration, set a few final things,
3556 based on what the OS ABI has told us. */
3557
3558 if (tdep->jb_pc >= 0)
3559 set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target);
3560
ea873d8e
PL		 3561 set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address);
3562
aa7ca1bb
AH		 3563 set_gdbarch_get_pc_address_flags (gdbarch, aarch64_get_pc_address_flags);
3564
c1e1314d 3565 tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data));
07b287a0
MS		 3566
3567 /* Add standard register aliases. */
3568 for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
3569 user_reg_add (gdbarch, aarch64_register_aliases[i].name,
3570 value_of_aarch64_user_reg,
3571 &aarch64_register_aliases[i].regnum);
3572
e8bf1ce4
JB		 3573 register_aarch64_ravenscar_ops (gdbarch);
3574
07b287a0
MS		 3575 return gdbarch;
3576}
3577
3578static void
3579aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3580{
3581 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3582
3583 if (tdep == NULL)
3584 return;
3585
3586 fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3587 paddress (gdbarch, tdep->lowest_pc));
3588}
3589
0d4c07af 3590#if GDB_SELF_TEST
1e2b521d
YQ		 3591namespace selftests
3592{
3593static void aarch64_process_record_test (void);
3594}
0d4c07af 3595#endif
1e2b521d 3596
6c265988 3597void _initialize_aarch64_tdep ();
07b287a0 3598void
6c265988 3599_initialize_aarch64_tdep ()
07b287a0
MS		 3600{
3601 gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
3602 aarch64_dump_tdep);
3603
07b287a0
MS		 3604 /* Debug this file's internals. */
3605 add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
3606Set AArch64 debugging."), _("\
3607Show AArch64 debugging."), _("\
3608When on, AArch64 specific debugging is enabled."),
3609 NULL,
3610 show_aarch64_debug,
3611 &setdebuglist, &showdebuglist);
4d9a9006
YQ		 3612
3613#if GDB_SELF_TEST
1526853e
SM		 3614 selftests::register_test ("aarch64-analyze-prologue",
3615 selftests::aarch64_analyze_prologue_test);
3616 selftests::register_test ("aarch64-process-record",
3617 selftests::aarch64_process_record_test);
4d9a9006 3618#endif
07b287a0 3619}
99afc88b
OJ		 3620
3621/* AArch64 process record-replay related structures, defines etc. */
3622
99afc88b 3623#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
dda83cd7
SM		 3624 do \
3625 { \
3626 unsigned int reg_len = LENGTH; \
3627 if (reg_len) \
3628 { \
3629 REGS = XNEWVEC (uint32_t, reg_len); \
3630 memcpy(&REGS[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3631 } \
3632 } \
3633 while (0)
99afc88b
OJ		 3634
3635#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
dda83cd7
SM		 3636 do \
3637 { \
3638 unsigned int mem_len = LENGTH; \
3639 if (mem_len) \
3640 { \
3641 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3642 memcpy(&MEMS->len, &RECORD_BUF[0], \
3643 sizeof(struct aarch64_mem_r) * LENGTH); \
3644 } \
3645 } \
3646 while (0)
99afc88b
OJ		 3647
3648/* AArch64 record/replay structures and enumerations. */
3649
3650struct aarch64_mem_r
3651{
3652 uint64_t len; /* Record length. */
3653 uint64_t addr; /* Memory address. */
3654};
3655
3656enum aarch64_record_result
3657{
3658 AARCH64_RECORD_SUCCESS,
99afc88b
OJ		 3659 AARCH64_RECORD_UNSUPPORTED,
3660 AARCH64_RECORD_UNKNOWN
3661};
3662
3663typedef struct insn_decode_record_t
3664{
3665 struct gdbarch *gdbarch;
3666 struct regcache *regcache;
3667 CORE_ADDR this_addr; /* Address of insn to be recorded. */
3668 uint32_t aarch64_insn; /* Insn to be recorded. */
3669 uint32_t mem_rec_count; /* Count of memory records. */
3670 uint32_t reg_rec_count; /* Count of register records. */
3671 uint32_t *aarch64_regs; /* Registers to be recorded. */
3672 struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */
3673} insn_decode_record;
3674
3675/* Record handler for data processing - register instructions. */
3676
3677static unsigned int
3678aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
3679{
3680 uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
3681 uint32_t record_buf[4];
3682
3683 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3684 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3685 insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23);
3686
3687 if (!bit (aarch64_insn_r->aarch64_insn, 28))
3688 {
3689 uint8_t setflags;
3690
3691 /* Logical (shifted register). */
3692 if (insn_bits24_27 == 0x0a)
3693 setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03);
3694 /* Add/subtract. */
3695 else if (insn_bits24_27 == 0x0b)
3696 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3697 else
3698 return AARCH64_RECORD_UNKNOWN;
3699
3700 record_buf[0] = reg_rd;
3701 aarch64_insn_r->reg_rec_count = 1;
3702 if (setflags)
3703 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3704 }
3705 else
3706 {
3707 if (insn_bits24_27 == 0x0b)
3708 {
3709 /* Data-processing (3 source). */
3710 record_buf[0] = reg_rd;
3711 aarch64_insn_r->reg_rec_count = 1;
3712 }
3713 else if (insn_bits24_27 == 0x0a)
3714 {
3715 if (insn_bits21_23 == 0x00)
3716 {
3717 /* Add/subtract (with carry). */
3718 record_buf[0] = reg_rd;
3719 aarch64_insn_r->reg_rec_count = 1;
3720 if (bit (aarch64_insn_r->aarch64_insn, 29))
3721 {
3722 record_buf[1] = AARCH64_CPSR_REGNUM;
3723 aarch64_insn_r->reg_rec_count = 2;
3724 }
3725 }
3726 else if (insn_bits21_23 == 0x02)
3727 {
3728 /* Conditional compare (register) and conditional compare
3729 (immediate) instructions. */
3730 record_buf[0] = AARCH64_CPSR_REGNUM;
3731 aarch64_insn_r->reg_rec_count = 1;
3732 }
3733 else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
3734 {
85102364 3735 /* Conditional select. */
99afc88b
OJ		 3736 /* Data-processing (2 source). */
3737 /* Data-processing (1 source). */
3738 record_buf[0] = reg_rd;
3739 aarch64_insn_r->reg_rec_count = 1;
3740 }
3741 else
3742 return AARCH64_RECORD_UNKNOWN;
3743 }
3744 }
3745
3746 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3747 record_buf);
3748 return AARCH64_RECORD_SUCCESS;
3749}
3750
3751/* Record handler for data processing - immediate instructions. */
3752
3753static unsigned int
3754aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
3755{
78cc6c2d 3756 uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags;
99afc88b
OJ		 3757 uint32_t record_buf[4];
3758
3759 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
99afc88b
OJ		 3760 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3761 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3762
3763 if (insn_bits24_27 == 0x00 /* PC rel addressing. */
3764 || insn_bits24_27 == 0x03 /* Bitfield and Extract. */
3765 || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */
3766 {
3767 record_buf[0] = reg_rd;
3768 aarch64_insn_r->reg_rec_count = 1;
3769 }
3770 else if (insn_bits24_27 == 0x01)
3771 {
3772 /* Add/Subtract (immediate). */
3773 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3774 record_buf[0] = reg_rd;
3775 aarch64_insn_r->reg_rec_count = 1;
3776 if (setflags)
3777 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3778 }
3779 else if (insn_bits24_27 == 0x02 && !insn_bit23)
3780 {
3781 /* Logical (immediate). */
3782 setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03;
3783 record_buf[0] = reg_rd;
3784 aarch64_insn_r->reg_rec_count = 1;
3785 if (setflags)
3786 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3787 }
3788 else
3789 return AARCH64_RECORD_UNKNOWN;
3790
3791 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3792 record_buf);
3793 return AARCH64_RECORD_SUCCESS;
3794}
3795
3796/* Record handler for branch, exception generation and system instructions. */
3797
3798static unsigned int
3799aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
3800{
3801 struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch);
3802 uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
3803 uint32_t record_buf[4];
3804
3805 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3806 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3807 insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3808
3809 if (insn_bits28_31 == 0x0d)
3810 {
3811 /* Exception generation instructions. */
3812 if (insn_bits24_27 == 0x04)
3813 {
5d98d3cd
YQ		 3814 if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
3815 && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
3816 && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
99afc88b
OJ		 3817 {
3818 ULONGEST svc_number;
3819
3820 regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8,
3821 &svc_number);
3822 return tdep->aarch64_syscall_record (aarch64_insn_r->regcache,
3823 svc_number);
3824 }
3825 else
3826 return AARCH64_RECORD_UNSUPPORTED;
3827 }
3828 /* System instructions. */
3829 else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
3830 {
3831 uint32_t reg_rt, reg_crn;
3832
3833 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3834 reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3835
3836 /* Record rt in case of sysl and mrs instructions. */
3837 if (bit (aarch64_insn_r->aarch64_insn, 21))
3838 {
3839 record_buf[0] = reg_rt;
3840 aarch64_insn_r->reg_rec_count = 1;
3841 }
3842 /* Record cpsr for hint and msr(immediate) instructions. */
3843 else if (reg_crn == 0x02 || reg_crn == 0x04)
3844 {
3845 record_buf[0] = AARCH64_CPSR_REGNUM;
3846 aarch64_insn_r->reg_rec_count = 1;
3847 }
3848 }
3849 /* Unconditional branch (register). */
3850 else if((insn_bits24_27 & 0x0e) == 0x06)
3851 {
3852 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3853 if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01)
3854 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3855 }
3856 else
3857 return AARCH64_RECORD_UNKNOWN;
3858 }
3859 /* Unconditional branch (immediate). */
3860 else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04)
3861 {
3862 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3863 if (bit (aarch64_insn_r->aarch64_insn, 31))
3864 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3865 }
3866 else
3867 /* Compare & branch (immediate), Test & branch (immediate) and
3868 Conditional branch (immediate). */
3869 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3870
3871 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3872 record_buf);
3873 return AARCH64_RECORD_SUCCESS;
3874}
3875
3876/* Record handler for advanced SIMD load and store instructions. */
3877
3878static unsigned int
3879aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
3880{
3881 CORE_ADDR address;
3882 uint64_t addr_offset = 0;
3883 uint32_t record_buf[24];
3884 uint64_t record_buf_mem[24];
3885 uint32_t reg_rn, reg_rt;
3886 uint32_t reg_index = 0, mem_index = 0;
3887 uint8_t opcode_bits, size_bits;
3888
3889 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3890 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3891 size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3892 opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3893 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
3894
3895 if (record_debug)
b277c936 3896 debug_printf ("Process record: Advanced SIMD load/store\n");
99afc88b
OJ		 3897
3898 /* Load/store single structure. */
3899 if (bit (aarch64_insn_r->aarch64_insn, 24))
3900 {
3901 uint8_t sindex, scale, selem, esize, replicate = 0;
3902 scale = opcode_bits >> 2;
3903 selem = ((opcode_bits & 0x02) |
dda83cd7 3904 bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
99afc88b 3905 switch (scale)
dda83cd7
SM		 3906 {
3907 case 1:
3908 if (size_bits & 0x01)
3909 return AARCH64_RECORD_UNKNOWN;
3910 break;
3911 case 2:
3912 if ((size_bits >> 1) & 0x01)
3913 return AARCH64_RECORD_UNKNOWN;
3914 if (size_bits & 0x01)
3915 {
3916 if (!((opcode_bits >> 1) & 0x01))
3917 scale = 3;
3918 else
3919 return AARCH64_RECORD_UNKNOWN;
3920 }
3921 break;
3922 case 3:
3923 if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
3924 {
3925 scale = size_bits;
3926 replicate = 1;
3927 break;
3928 }
3929 else
3930 return AARCH64_RECORD_UNKNOWN;
3931 default:
3932 break;
3933 }
99afc88b
OJ		 3934 esize = 8 << scale;
3935 if (replicate)
dda83cd7
SM		 3936 for (sindex = 0; sindex < selem; sindex++)
3937 {
3938 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3939 reg_rt = (reg_rt + 1) % 32;
3940 }
99afc88b 3941 else
dda83cd7
SM		 3942 {
3943 for (sindex = 0; sindex < selem; sindex++)
a2e3e93f
SM		 3944 {
3945 if (bit (aarch64_insn_r->aarch64_insn, 22))
3946 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3947 else
3948 {
3949 record_buf_mem[mem_index++] = esize / 8;
3950 record_buf_mem[mem_index++] = address + addr_offset;
3951 }
3952 addr_offset = addr_offset + (esize / 8);
3953 reg_rt = (reg_rt + 1) % 32;
3954 }
dda83cd7 3955 }
99afc88b
OJ		 3956 }
3957 /* Load/store multiple structure. */
3958 else
3959 {
3960 uint8_t selem, esize, rpt, elements;
3961 uint8_t eindex, rindex;
3962
3963 esize = 8 << size_bits;
3964 if (bit (aarch64_insn_r->aarch64_insn, 30))
dda83cd7 3965 elements = 128 / esize;
99afc88b 3966 else
dda83cd7 3967 elements = 64 / esize;
99afc88b
OJ		 3968
3969 switch (opcode_bits)
dda83cd7
SM		 3970 {
3971 /*LD/ST4 (4 Registers). */
3972 case 0:
3973 rpt = 1;
3974 selem = 4;
3975 break;
3976 /*LD/ST1 (4 Registers). */
3977 case 2:
3978 rpt = 4;
3979 selem = 1;
3980 break;
3981 /*LD/ST3 (3 Registers). */
3982 case 4:
3983 rpt = 1;
3984 selem = 3;
3985 break;
3986 /*LD/ST1 (3 Registers). */
3987 case 6:
3988 rpt = 3;
3989 selem = 1;
3990 break;
3991 /*LD/ST1 (1 Register). */
3992 case 7:
3993 rpt = 1;
3994 selem = 1;
3995 break;
3996 /*LD/ST2 (2 Registers). */
3997 case 8:
3998 rpt = 1;
3999 selem = 2;
4000 break;
4001 /*LD/ST1 (2 Registers). */
4002 case 10:
4003 rpt = 2;
4004 selem = 1;
4005 break;
4006 default:
4007 return AARCH64_RECORD_UNSUPPORTED;
4008 break;
4009 }
99afc88b 4010 for (rindex = 0; rindex < rpt; rindex++)
dda83cd7
SM		 4011 for (eindex = 0; eindex < elements; eindex++)
4012 {
4013 uint8_t reg_tt, sindex;
4014 reg_tt = (reg_rt + rindex) % 32;
4015 for (sindex = 0; sindex < selem; sindex++)
4016 {
4017 if (bit (aarch64_insn_r->aarch64_insn, 22))
4018 record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
4019 else
4020 {
4021 record_buf_mem[mem_index++] = esize / 8;
4022 record_buf_mem[mem_index++] = address + addr_offset;
4023 }
4024 addr_offset = addr_offset + (esize / 8);
4025 reg_tt = (reg_tt + 1) % 32;
4026 }
4027 }
99afc88b
OJ		 4028 }
4029
4030 if (bit (aarch64_insn_r->aarch64_insn, 23))
4031 record_buf[reg_index++] = reg_rn;
4032
4033 aarch64_insn_r->reg_rec_count = reg_index;
4034 aarch64_insn_r->mem_rec_count = mem_index / 2;
4035 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
dda83cd7 4036 record_buf_mem);
99afc88b 4037 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
dda83cd7 4038 record_buf);
99afc88b
OJ		 4039 return AARCH64_RECORD_SUCCESS;
4040}
4041
4042/* Record handler for load and store instructions. */
4043
4044static unsigned int
4045aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
4046{
4047 uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
4048 uint8_t insn_bit23, insn_bit21;
4049 uint8_t opc, size_bits, ld_flag, vector_flag;
4050 uint32_t reg_rn, reg_rt, reg_rt2;
4051 uint64_t datasize, offset;
4052 uint32_t record_buf[8];
4053 uint64_t record_buf_mem[8];
4054 CORE_ADDR address;
4055
4056 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
4057 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
4058 insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29);
4059 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
4060 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
4061 ld_flag = bit (aarch64_insn_r->aarch64_insn, 22);
4062 vector_flag = bit (aarch64_insn_r->aarch64_insn, 26);
4063 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
4064 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
4065 reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14);
4066 size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31);
4067
4068 /* Load/store exclusive. */
4069 if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
4070 {
4071 if (record_debug)
b277c936 4072 debug_printf ("Process record: load/store exclusive\n");
99afc88b
OJ		 4073
4074 if (ld_flag)
4075 {
4076 record_buf[0] = reg_rt;
4077 aarch64_insn_r->reg_rec_count = 1;
4078 if (insn_bit21)
4079 {
4080 record_buf[1] = reg_rt2;
4081 aarch64_insn_r->reg_rec_count = 2;
4082 }
4083 }
4084 else
4085 {
4086 if (insn_bit21)
4087 datasize = (8 << size_bits) * 2;
4088 else
4089 datasize = (8 << size_bits);
4090 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4091 &address);
4092 record_buf_mem[0] = datasize / 8;
4093 record_buf_mem[1] = address;
4094 aarch64_insn_r->mem_rec_count = 1;
4095 if (!insn_bit23)
4096 {
4097 /* Save register rs. */
4098 record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20);
4099 aarch64_insn_r->reg_rec_count = 1;
4100 }
4101 }
4102 }
4103 /* Load register (literal) instructions decoding. */
4104 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
4105 {
4106 if (record_debug)
b277c936 4107 debug_printf ("Process record: load register (literal)\n");
99afc88b 4108 if (vector_flag)
dda83cd7 4109 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
99afc88b 4110 else
dda83cd7 4111 record_buf[0] = reg_rt;
99afc88b
OJ		 4112 aarch64_insn_r->reg_rec_count = 1;
4113 }
4114 /* All types of load/store pair instructions decoding. */
4115 else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
4116 {
4117 if (record_debug)
b277c936 4118 debug_printf ("Process record: load/store pair\n");
99afc88b
OJ		 4119
4120 if (ld_flag)
dda83cd7
SM		 4121 {
4122 if (vector_flag)
4123 {
4124 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4125 record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
4126 }
4127 else
4128 {
4129 record_buf[0] = reg_rt;
4130 record_buf[1] = reg_rt2;
4131 }
4132 aarch64_insn_r->reg_rec_count = 2;
4133 }
99afc88b 4134 else
dda83cd7
SM		 4135 {
4136 uint16_t imm7_off;
4137 imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
4138 if (!vector_flag)
4139 size_bits = size_bits >> 1;
4140 datasize = 8 << (2 + size_bits);
4141 offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
4142 offset = offset << (2 + size_bits);
4143 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4144 &address);
4145 if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
4146 {
4147 if (imm7_off & 0x40)
4148 address = address - offset;
4149 else
4150 address = address + offset;
4151 }
4152
4153 record_buf_mem[0] = datasize / 8;
4154 record_buf_mem[1] = address;
4155 record_buf_mem[2] = datasize / 8;
4156 record_buf_mem[3] = address + (datasize / 8);
4157 aarch64_insn_r->mem_rec_count = 2;
4158 }
99afc88b 4159 if (bit (aarch64_insn_r->aarch64_insn, 23))
dda83cd7 4160 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
99afc88b
OJ		 4161 }
4162 /* Load/store register (unsigned immediate) instructions. */
4163 else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
4164 {
4165 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4166 if (!(opc >> 1))
33877125
YQ		 4167 {
4168 if (opc & 0x01)
4169 ld_flag = 0x01;
4170 else
4171 ld_flag = 0x0;
4172 }
99afc88b 4173 else
33877125 4174 {
1e2b521d
YQ		 4175 if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2)
4176 {
4177 /* PRFM (immediate) */
4178 return AARCH64_RECORD_SUCCESS;
4179 }
4180 else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2)
4181 {
4182 /* LDRSW (immediate) */
4183 ld_flag = 0x1;
4184 }
33877125 4185 else
1e2b521d
YQ		 4186 {
4187 if (opc & 0x01)
4188 ld_flag = 0x01;
4189 else
4190 ld_flag = 0x0;
4191 }
33877125 4192 }
99afc88b
OJ		 4193
4194 if (record_debug)
4195 {
b277c936
PL		 4196 debug_printf ("Process record: load/store (unsigned immediate):"
4197 " size %x V %d opc %x\n", size_bits, vector_flag,
4198 opc);
99afc88b
OJ		 4199 }
4200
4201 if (!ld_flag)
dda83cd7
SM		 4202 {
4203 offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
4204 datasize = 8 << size_bits;
4205 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4206 &address);
4207 offset = offset << size_bits;
4208 address = address + offset;
4209
4210 record_buf_mem[0] = datasize >> 3;
4211 record_buf_mem[1] = address;
4212 aarch64_insn_r->mem_rec_count = 1;
4213 }
99afc88b 4214 else
dda83cd7
SM		 4215 {
4216 if (vector_flag)
4217 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4218 else
4219 record_buf[0] = reg_rt;
4220 aarch64_insn_r->reg_rec_count = 1;
4221 }
99afc88b
OJ		 4222 }
4223 /* Load/store register (register offset) instructions. */
5d98d3cd
YQ		 4224 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
4225 && insn_bits10_11 == 0x02 && insn_bit21)
99afc88b
OJ		 4226 {
4227 if (record_debug)
b277c936 4228 debug_printf ("Process record: load/store (register offset)\n");
99afc88b
OJ		 4229 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4230 if (!(opc >> 1))
dda83cd7
SM		 4231 if (opc & 0x01)
4232 ld_flag = 0x01;
4233 else
4234 ld_flag = 0x0;
99afc88b 4235 else
dda83cd7
SM		 4236 if (size_bits != 0x03)
4237 ld_flag = 0x01;
4238 else
4239 return AARCH64_RECORD_UNKNOWN;
99afc88b
OJ		 4240
4241 if (!ld_flag)
dda83cd7
SM		 4242 {
4243 ULONGEST reg_rm_val;
4244
4245 regcache_raw_read_unsigned (aarch64_insn_r->regcache,
4246 bits (aarch64_insn_r->aarch64_insn, 16, 20), &reg_rm_val);
4247 if (bit (aarch64_insn_r->aarch64_insn, 12))
4248 offset = reg_rm_val << size_bits;
4249 else
4250 offset = reg_rm_val;
4251 datasize = 8 << size_bits;
4252 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4253 &address);
4254 address = address + offset;
4255 record_buf_mem[0] = datasize >> 3;
4256 record_buf_mem[1] = address;
4257 aarch64_insn_r->mem_rec_count = 1;
4258 }
99afc88b 4259 else
dda83cd7
SM		 4260 {
4261 if (vector_flag)
4262 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4263 else
4264 record_buf[0] = reg_rt;
4265 aarch64_insn_r->reg_rec_count = 1;
4266 }
99afc88b
OJ		 4267 }
4268 /* Load/store register (immediate and unprivileged) instructions. */
5d98d3cd
YQ		 4269 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
4270 && !insn_bit21)
99afc88b
OJ		 4271 {
4272 if (record_debug)
4273 {
b277c936
PL		 4274 debug_printf ("Process record: load/store "
4275 "(immediate and unprivileged)\n");
99afc88b
OJ		 4276 }
4277 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4278 if (!(opc >> 1))
dda83cd7
SM		 4279 if (opc & 0x01)
4280 ld_flag = 0x01;
4281 else
4282 ld_flag = 0x0;
99afc88b 4283 else
dda83cd7
SM		 4284 if (size_bits != 0x03)
4285 ld_flag = 0x01;
4286 else
4287 return AARCH64_RECORD_UNKNOWN;
99afc88b
OJ		 4288
4289 if (!ld_flag)
dda83cd7
SM		 4290 {
4291 uint16_t imm9_off;
4292 imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
4293 offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
4294 datasize = 8 << size_bits;
4295 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4296 &address);
4297 if (insn_bits10_11 != 0x01)
4298 {
4299 if (imm9_off & 0x0100)
4300 address = address - offset;
4301 else
4302 address = address + offset;
4303 }
4304 record_buf_mem[0] = datasize >> 3;
4305 record_buf_mem[1] = address;
4306 aarch64_insn_r->mem_rec_count = 1;
4307 }
99afc88b 4308 else
dda83cd7
SM		 4309 {
4310 if (vector_flag)
4311 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4312 else
4313 record_buf[0] = reg_rt;
4314 aarch64_insn_r->reg_rec_count = 1;
4315 }
99afc88b 4316 if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
dda83cd7 4317 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
99afc88b
OJ		 4318 }
4319 /* Advanced SIMD load/store instructions. */
4320 else
4321 return aarch64_record_asimd_load_store (aarch64_insn_r);
4322
4323 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
dda83cd7 4324 record_buf_mem);
99afc88b 4325 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
dda83cd7 4326 record_buf);
99afc88b
OJ		 4327 return AARCH64_RECORD_SUCCESS;
4328}
4329
4330/* Record handler for data processing SIMD and floating point instructions. */
4331
4332static unsigned int
4333aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
4334{
4335 uint8_t insn_bit21, opcode, rmode, reg_rd;
4336 uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
4337 uint8_t insn_bits11_14;
4338 uint32_t record_buf[2];
4339
4340 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
4341 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
4342 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
4343 insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
4344 insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14);
4345 opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18);
4346 rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20);
4347 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
4348 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
4349
4350 if (record_debug)
b277c936 4351 debug_printf ("Process record: data processing SIMD/FP: ");
99afc88b
OJ		 4352
4353 if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
4354 {
4355 /* Floating point - fixed point conversion instructions. */
4356 if (!insn_bit21)
4357 {
4358 if (record_debug)
b277c936 4359 debug_printf ("FP - fixed point conversion");
99afc88b
OJ		 4360
4361 if ((opcode >> 1) == 0x0 && rmode == 0x03)
4362 record_buf[0] = reg_rd;
4363 else
4364 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4365 }
4366 /* Floating point - conditional compare instructions. */
4367 else if (insn_bits10_11 == 0x01)
4368 {
4369 if (record_debug)
b277c936 4370 debug_printf ("FP - conditional compare");
99afc88b
OJ		 4371
4372 record_buf[0] = AARCH64_CPSR_REGNUM;
4373 }
4374 /* Floating point - data processing (2-source) and
dda83cd7 4375 conditional select instructions. */
99afc88b
OJ		 4376 else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
4377 {
4378 if (record_debug)
b277c936 4379 debug_printf ("FP - DP (2-source)");
99afc88b
OJ		 4380
4381 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4382 }
4383 else if (insn_bits10_11 == 0x00)
4384 {
4385 /* Floating point - immediate instructions. */
4386 if ((insn_bits12_15 & 0x01) == 0x01
4387 || (insn_bits12_15 & 0x07) == 0x04)
4388 {
4389 if (record_debug)
b277c936 4390 debug_printf ("FP - immediate");
99afc88b
OJ		 4391 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4392 }
4393 /* Floating point - compare instructions. */
4394 else if ((insn_bits12_15 & 0x03) == 0x02)
4395 {
4396 if (record_debug)
b277c936 4397 debug_printf ("FP - immediate");
99afc88b
OJ		 4398 record_buf[0] = AARCH64_CPSR_REGNUM;
4399 }
4400 /* Floating point - integer conversions instructions. */
f62fce35 4401 else if (insn_bits12_15 == 0x00)
99afc88b
OJ		 4402 {
4403 /* Convert float to integer instruction. */
4404 if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
4405 {
4406 if (record_debug)
b277c936 4407 debug_printf ("float to int conversion");
99afc88b
OJ		 4408
4409 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4410 }
4411 /* Convert integer to float instruction. */
4412 else if ((opcode >> 1) == 0x01 && !rmode)
4413 {
4414 if (record_debug)
b277c936 4415 debug_printf ("int to float conversion");
99afc88b
OJ		 4416
4417 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4418 }
4419 /* Move float to integer instruction. */
4420 else if ((opcode >> 1) == 0x03)
4421 {
4422 if (record_debug)
b277c936 4423 debug_printf ("move float to int");
99afc88b
OJ		 4424
4425 if (!(opcode & 0x01))
4426 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4427 else
4428 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4429 }
f62fce35
YQ		 4430 else
4431 return AARCH64_RECORD_UNKNOWN;
dda83cd7 4432 }
f62fce35
YQ		 4433 else
4434 return AARCH64_RECORD_UNKNOWN;
dda83cd7 4435 }
f62fce35
YQ		 4436 else
4437 return AARCH64_RECORD_UNKNOWN;
99afc88b
OJ		 4438 }
4439 else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
4440 {
4441 if (record_debug)
b277c936 4442 debug_printf ("SIMD copy");
99afc88b
OJ		 4443
4444 /* Advanced SIMD copy instructions. */
4445 if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
4446 && !bit (aarch64_insn_r->aarch64_insn, 15)
4447 && bit (aarch64_insn_r->aarch64_insn, 10))
4448 {
4449 if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07)
4450 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4451 else
4452 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4453 }
4454 else
4455 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4456 }
4457 /* All remaining floating point or advanced SIMD instructions. */
4458 else
4459 {
4460 if (record_debug)
b277c936 4461 debug_printf ("all remain");
99afc88b
OJ		 4462
4463 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4464 }
4465
4466 if (record_debug)
b277c936 4467 debug_printf ("\n");
99afc88b 4468
bfbe4b84 4469 /* Record the V/X register. */
99afc88b 4470 aarch64_insn_r->reg_rec_count++;
bfbe4b84
LM		 4471
4472 /* Some of these instructions may set bits in the FPSR, so record it
4473 too. */
4474 record_buf[1] = AARCH64_FPSR_REGNUM;
4475 aarch64_insn_r->reg_rec_count++;
4476
4477 gdb_assert (aarch64_insn_r->reg_rec_count == 2);
99afc88b
OJ		 4478 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
4479 record_buf);
4480 return AARCH64_RECORD_SUCCESS;
4481}
4482
4483/* Decodes insns type and invokes its record handler. */
4484
4485static unsigned int
4486aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
4487{
4488 uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
4489
4490 ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25);
4491 ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26);
4492 ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27);
4493 ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
4494
4495 /* Data processing - immediate instructions. */
4496 if (!ins_bit26 && !ins_bit27 && ins_bit28)
4497 return aarch64_record_data_proc_imm (aarch64_insn_r);
4498
4499 /* Branch, exception generation and system instructions. */
4500 if (ins_bit26 && !ins_bit27 && ins_bit28)
4501 return aarch64_record_branch_except_sys (aarch64_insn_r);
4502
4503 /* Load and store instructions. */
4504 if (!ins_bit25 && ins_bit27)
4505 return aarch64_record_load_store (aarch64_insn_r);
4506
4507 /* Data processing - register instructions. */
4508 if (ins_bit25 && !ins_bit26 && ins_bit27)
4509 return aarch64_record_data_proc_reg (aarch64_insn_r);
4510
4511 /* Data processing - SIMD and floating point instructions. */
4512 if (ins_bit25 && ins_bit26 && ins_bit27)
4513 return aarch64_record_data_proc_simd_fp (aarch64_insn_r);
4514
4515 return AARCH64_RECORD_UNSUPPORTED;
4516}
4517
4518/* Cleans up local record registers and memory allocations. */
4519
4520static void
4521deallocate_reg_mem (insn_decode_record *record)
4522{
4523 xfree (record->aarch64_regs);
4524 xfree (record->aarch64_mems);
4525}
4526
1e2b521d
YQ		 4527#if GDB_SELF_TEST
4528namespace selftests {
4529
4530static void
4531aarch64_process_record_test (void)
4532{
4533 struct gdbarch_info info;
4534 uint32_t ret;
4535
4536 gdbarch_info_init (&info);
4537 info.bfd_arch_info = bfd_scan_arch ("aarch64");
4538
4539 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
4540 SELF_CHECK (gdbarch != NULL);
4541
4542 insn_decode_record aarch64_record;
4543
4544 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4545 aarch64_record.regcache = NULL;
4546 aarch64_record.this_addr = 0;
4547 aarch64_record.gdbarch = gdbarch;
4548
4549 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4550 aarch64_record.aarch64_insn = 0xf9800020;
4551 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4552 SELF_CHECK (ret == AARCH64_RECORD_SUCCESS);
4553 SELF_CHECK (aarch64_record.reg_rec_count == 0);
4554 SELF_CHECK (aarch64_record.mem_rec_count == 0);
4555
4556 deallocate_reg_mem (&aarch64_record);
4557}
4558
4559} // namespace selftests
4560#endif /* GDB_SELF_TEST */
4561
99afc88b
OJ		 4562/* Parse the current instruction and record the values of the registers and
4563 memory that will be changed in current instruction to record_arch_list
4564 return -1 if something is wrong. */
4565
4566int
4567aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4568 CORE_ADDR insn_addr)
4569{
4570 uint32_t rec_no = 0;
4571 uint8_t insn_size = 4;
4572 uint32_t ret = 0;
99afc88b
OJ		 4573 gdb_byte buf[insn_size];
4574 insn_decode_record aarch64_record;
4575
4576 memset (&buf[0], 0, insn_size);
4577 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4578 target_read_memory (insn_addr, &buf[0], insn_size);
4579 aarch64_record.aarch64_insn
4580 = (uint32_t) extract_unsigned_integer (&buf[0],
4581 insn_size,
4582 gdbarch_byte_order (gdbarch));
4583 aarch64_record.regcache = regcache;
4584 aarch64_record.this_addr = insn_addr;
4585 aarch64_record.gdbarch = gdbarch;
4586
4587 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4588 if (ret == AARCH64_RECORD_UNSUPPORTED)
4589 {
4590 printf_unfiltered (_("Process record does not support instruction "
4591 "0x%0x at address %s.\n"),
4592 aarch64_record.aarch64_insn,
4593 paddress (gdbarch, insn_addr));
4594 ret = -1;
4595 }
4596
4597 if (0 == ret)
4598 {
4599 /* Record registers. */
4600 record_full_arch_list_add_reg (aarch64_record.regcache,
4601 AARCH64_PC_REGNUM);
4602 /* Always record register CPSR. */
4603 record_full_arch_list_add_reg (aarch64_record.regcache,
4604 AARCH64_CPSR_REGNUM);
4605 if (aarch64_record.aarch64_regs)
4606 for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
4607 if (record_full_arch_list_add_reg (aarch64_record.regcache,
4608 aarch64_record.aarch64_regs[rec_no]))
4609 ret = -1;
4610
4611 /* Record memories. */
4612 if (aarch64_record.aarch64_mems)
4613 for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++)
4614 if (record_full_arch_list_add_mem
4615 ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr,
4616 aarch64_record.aarch64_mems[rec_no].len))
4617 ret = -1;
4618
4619 if (record_full_arch_list_add_end ())
4620 ret = -1;
4621 }
4622
4623 deallocate_reg_mem (&aarch64_record);
4624 return ret;
4625}
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