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[thirdparty/binutils-gdb.git] / gdb / aarch64-tdep.c
CommitLineData
07b287a0
MS		 1/* Common target dependent code for GDB on AArch64 systems.
2
b811d2c2 3 Copyright (C) 2009-2020 Free Software Foundation, Inc.
07b287a0
MS		 4 Contributed by ARM Ltd.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "defs.h"
22
23#include "frame.h"
07b287a0
MS		 24#include "gdbcmd.h"
25#include "gdbcore.h"
4de283e4 26#include "dis-asm.h"
d55e5aa6
TT		 27#include "regcache.h"
28#include "reggroups.h"
4de283e4
TT		 29#include "value.h"
30#include "arch-utils.h"
31#include "osabi.h"
32#include "frame-unwind.h"
33#include "frame-base.h"
d55e5aa6 34#include "trad-frame.h"
4de283e4
TT		 35#include "objfiles.h"
36#include "dwarf2.h"
82ca8957 37#include "dwarf2/frame.h"
4de283e4
TT		 38#include "gdbtypes.h"
39#include "prologue-value.h"
40#include "target-descriptions.h"
07b287a0 41#include "user-regs.h"
4de283e4 42#include "ax-gdb.h"
268a13a5 43#include "gdbsupport/selftest.h"
4de283e4
TT		 44
45#include "aarch64-tdep.h"
46#include "aarch64-ravenscar-thread.h"
47
4de283e4
TT		 48#include "record.h"
49#include "record-full.h"
50#include "arch/aarch64-insn.h"
0d12e84c 51#include "gdbarch.h"
4de283e4
TT		 52
53#include "opcode/aarch64.h"
54#include <algorithm>
f77ee802
YQ		 55
56#define submask(x) ((1L << ((x) + 1)) - 1)
57#define bit(obj,st) (((obj) >> (st)) & 1)
58#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
59
ea92689a
AH		 60/* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
61 four members. */
62#define HA_MAX_NUM_FLDS 4
63
95228a0d 64/* All possible aarch64 target descriptors. */
6dc0ebde 65struct target_desc *tdesc_aarch64_list[AARCH64_MAX_SVE_VQ + 1][2/*pauth*/];
95228a0d 66
07b287a0
MS		 67/* The standard register names, and all the valid aliases for them. */
68static const struct
69{
70 const char *const name;
71 int regnum;
72} aarch64_register_aliases[] =
73{
74 /* 64-bit register names. */
75 {"fp", AARCH64_FP_REGNUM},
76 {"lr", AARCH64_LR_REGNUM},
77 {"sp", AARCH64_SP_REGNUM},
78
79 /* 32-bit register names. */
80 {"w0", AARCH64_X0_REGNUM + 0},
81 {"w1", AARCH64_X0_REGNUM + 1},
82 {"w2", AARCH64_X0_REGNUM + 2},
83 {"w3", AARCH64_X0_REGNUM + 3},
84 {"w4", AARCH64_X0_REGNUM + 4},
85 {"w5", AARCH64_X0_REGNUM + 5},
86 {"w6", AARCH64_X0_REGNUM + 6},
87 {"w7", AARCH64_X0_REGNUM + 7},
88 {"w8", AARCH64_X0_REGNUM + 8},
89 {"w9", AARCH64_X0_REGNUM + 9},
90 {"w10", AARCH64_X0_REGNUM + 10},
91 {"w11", AARCH64_X0_REGNUM + 11},
92 {"w12", AARCH64_X0_REGNUM + 12},
93 {"w13", AARCH64_X0_REGNUM + 13},
94 {"w14", AARCH64_X0_REGNUM + 14},
95 {"w15", AARCH64_X0_REGNUM + 15},
96 {"w16", AARCH64_X0_REGNUM + 16},
97 {"w17", AARCH64_X0_REGNUM + 17},
98 {"w18", AARCH64_X0_REGNUM + 18},
99 {"w19", AARCH64_X0_REGNUM + 19},
100 {"w20", AARCH64_X0_REGNUM + 20},
101 {"w21", AARCH64_X0_REGNUM + 21},
102 {"w22", AARCH64_X0_REGNUM + 22},
103 {"w23", AARCH64_X0_REGNUM + 23},
104 {"w24", AARCH64_X0_REGNUM + 24},
105 {"w25", AARCH64_X0_REGNUM + 25},
106 {"w26", AARCH64_X0_REGNUM + 26},
107 {"w27", AARCH64_X0_REGNUM + 27},
108 {"w28", AARCH64_X0_REGNUM + 28},
109 {"w29", AARCH64_X0_REGNUM + 29},
110 {"w30", AARCH64_X0_REGNUM + 30},
111
112 /* specials */
113 {"ip0", AARCH64_X0_REGNUM + 16},
114 {"ip1", AARCH64_X0_REGNUM + 17}
115};
116
117/* The required core 'R' registers. */
118static const char *const aarch64_r_register_names[] =
119{
120 /* These registers must appear in consecutive RAW register number
121 order and they must begin with AARCH64_X0_REGNUM! */
122 "x0", "x1", "x2", "x3",
123 "x4", "x5", "x6", "x7",
124 "x8", "x9", "x10", "x11",
125 "x12", "x13", "x14", "x15",
126 "x16", "x17", "x18", "x19",
127 "x20", "x21", "x22", "x23",
128 "x24", "x25", "x26", "x27",
129 "x28", "x29", "x30", "sp",
130 "pc", "cpsr"
131};
132
133/* The FP/SIMD 'V' registers. */
134static const char *const aarch64_v_register_names[] =
135{
136 /* These registers must appear in consecutive RAW register number
137 order and they must begin with AARCH64_V0_REGNUM! */
138 "v0", "v1", "v2", "v3",
139 "v4", "v5", "v6", "v7",
140 "v8", "v9", "v10", "v11",
141 "v12", "v13", "v14", "v15",
142 "v16", "v17", "v18", "v19",
143 "v20", "v21", "v22", "v23",
144 "v24", "v25", "v26", "v27",
145 "v28", "v29", "v30", "v31",
146 "fpsr",
147 "fpcr"
148};
149
739e8682
AH		 150/* The SVE 'Z' and 'P' registers. */
151static const char *const aarch64_sve_register_names[] =
152{
153 /* These registers must appear in consecutive RAW register number
154 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
155 "z0", "z1", "z2", "z3",
156 "z4", "z5", "z6", "z7",
157 "z8", "z9", "z10", "z11",
158 "z12", "z13", "z14", "z15",
159 "z16", "z17", "z18", "z19",
160 "z20", "z21", "z22", "z23",
161 "z24", "z25", "z26", "z27",
162 "z28", "z29", "z30", "z31",
163 "fpsr", "fpcr",
164 "p0", "p1", "p2", "p3",
165 "p4", "p5", "p6", "p7",
166 "p8", "p9", "p10", "p11",
167 "p12", "p13", "p14", "p15",
168 "ffr", "vg"
169};
170
76bed0fd
AH		 171static const char *const aarch64_pauth_register_names[] =
172{
173 /* Authentication mask for data pointer. */
174 "pauth_dmask",
175 /* Authentication mask for code pointer. */
176 "pauth_cmask"
177};
178
07b287a0
MS		 179/* AArch64 prologue cache structure. */
180struct aarch64_prologue_cache
181{
db634143
PL		 182 /* The program counter at the start of the function. It is used to
183 identify this frame as a prologue frame. */
184 CORE_ADDR func;
185
186 /* The program counter at the time this frame was created; i.e. where
187 this function was called from. It is used to identify this frame as a
188 stub frame. */
189 CORE_ADDR prev_pc;
190
07b287a0
MS		 191 /* The stack pointer at the time this frame was created; i.e. the
192 caller's stack pointer when this function was called. It is used
193 to identify this frame. */
194 CORE_ADDR prev_sp;
195
7dfa3edc
PL		 196 /* Is the target available to read from? */
197 int available_p;
198
07b287a0
MS		 199 /* The frame base for this frame is just prev_sp - frame size.
200 FRAMESIZE is the distance from the frame pointer to the
201 initial stack pointer. */
202 int framesize;
203
204 /* The register used to hold the frame pointer for this frame. */
205 int framereg;
206
207 /* Saved register offsets. */
208 struct trad_frame_saved_reg *saved_regs;
209};
210
07b287a0
MS		 211static void
212show_aarch64_debug (struct ui_file *file, int from_tty,
213 struct cmd_list_element *c, const char *value)
214{
215 fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
216}
217
ffdbe864
YQ		 218namespace {
219
4d9a9006
YQ		 220/* Abstract instruction reader. */
221
222class abstract_instruction_reader
223{
224public:
225 /* Read in one instruction. */
226 virtual ULONGEST read (CORE_ADDR memaddr, int len,
227 enum bfd_endian byte_order) = 0;
228};
229
230/* Instruction reader from real target. */
231
232class instruction_reader : public abstract_instruction_reader
233{
234 public:
235 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 236 override
4d9a9006 237 {
fc2f703e 238 return read_code_unsigned_integer (memaddr, len, byte_order);
4d9a9006
YQ		 239 }
240};
241
ffdbe864
YQ		 242} // namespace
243
3d31bc39
AH		 244/* If address signing is enabled, mask off the signature bits from the link
245 register, which is passed by value in ADDR, using the register values in
246 THIS_FRAME. */
11e1b75f
AH		 247
248static CORE_ADDR
3d31bc39
AH		 249aarch64_frame_unmask_lr (struct gdbarch_tdep *tdep,
250 struct frame_info *this_frame, CORE_ADDR addr)
11e1b75f
AH		 251{
252 if (tdep->has_pauth ()
253 && frame_unwind_register_unsigned (this_frame,
254 tdep->pauth_ra_state_regnum))
255 {
256 int cmask_num = AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base);
257 CORE_ADDR cmask = frame_unwind_register_unsigned (this_frame, cmask_num);
258 addr = addr & ~cmask;
3d31bc39
AH		 259
260 /* Record in the frame that the link register required unmasking. */
261 set_frame_previous_pc_masked (this_frame);
11e1b75f
AH		 262 }
263
264 return addr;
265}
266
aa7ca1bb
AH		 267/* Implement the "get_pc_address_flags" gdbarch method. */
268
269static std::string
270aarch64_get_pc_address_flags (frame_info *frame, CORE_ADDR pc)
271{
272 if (pc != 0 && get_frame_pc_masked (frame))
273 return "PAC";
274
275 return "";
276}
277
07b287a0
MS		 278/* Analyze a prologue, looking for a recognizable stack frame
279 and frame pointer. Scan until we encounter a store that could
280 clobber the stack frame unexpectedly, or an unknown instruction. */
281
282static CORE_ADDR
283aarch64_analyze_prologue (struct gdbarch *gdbarch,
284 CORE_ADDR start, CORE_ADDR limit,
4d9a9006
YQ		 285 struct aarch64_prologue_cache *cache,
286 abstract_instruction_reader& reader)
07b287a0
MS		 287{
288 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
289 int i;
187f5d00
YQ		 290 /* Track X registers and D registers in prologue. */
291 pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
07b287a0 292
187f5d00 293 for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
07b287a0 294 regs[i] = pv_register (i, 0);
f7b7ed97 295 pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
07b287a0
MS		 296
297 for (; start < limit; start += 4)
298 {
299 uint32_t insn;
d9ebcbce 300 aarch64_inst inst;
07b287a0 301
4d9a9006 302 insn = reader.read (start, 4, byte_order_for_code);
07b287a0 303
561a72d4 304 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
d9ebcbce
YQ		 305 break;
306
307 if (inst.opcode->iclass == addsub_imm
308 && (inst.opcode->op == OP_ADD
309 || strcmp ("sub", inst.opcode->name) == 0))
07b287a0 310 {
d9ebcbce
YQ		 311 unsigned rd = inst.operands[0].reg.regno;
312 unsigned rn = inst.operands[1].reg.regno;
313
314 gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
315 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
316 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
317 gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
318
319 if (inst.opcode->op == OP_ADD)
320 {
321 regs[rd] = pv_add_constant (regs[rn],
322 inst.operands[2].imm.value);
323 }
324 else
325 {
326 regs[rd] = pv_add_constant (regs[rn],
327 -inst.operands[2].imm.value);
328 }
329 }
330 else if (inst.opcode->iclass == pcreladdr
331 && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
332 {
333 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
334 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
335
336 regs[inst.operands[0].reg.regno] = pv_unknown ();
07b287a0 337 }
d9ebcbce 338 else if (inst.opcode->iclass == branch_imm)
07b287a0
MS		 339 {
340 /* Stop analysis on branch. */
341 break;
342 }
d9ebcbce 343 else if (inst.opcode->iclass == condbranch)
07b287a0
MS		 344 {
345 /* Stop analysis on branch. */
346 break;
347 }
d9ebcbce 348 else if (inst.opcode->iclass == branch_reg)
07b287a0
MS		 349 {
350 /* Stop analysis on branch. */
351 break;
352 }
d9ebcbce 353 else if (inst.opcode->iclass == compbranch)
07b287a0
MS		 354 {
355 /* Stop analysis on branch. */
356 break;
357 }
d9ebcbce
YQ		 358 else if (inst.opcode->op == OP_MOVZ)
359 {
360 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
361 regs[inst.operands[0].reg.regno] = pv_unknown ();
362 }
363 else if (inst.opcode->iclass == log_shift
364 && strcmp (inst.opcode->name, "orr") == 0)
07b287a0 365 {
d9ebcbce
YQ		 366 unsigned rd = inst.operands[0].reg.regno;
367 unsigned rn = inst.operands[1].reg.regno;
368 unsigned rm = inst.operands[2].reg.regno;
369
370 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
371 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
372 gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
373
374 if (inst.operands[2].shifter.amount == 0
375 && rn == AARCH64_SP_REGNUM)
07b287a0
MS		 376 regs[rd] = regs[rm];
377 else
378 {
379 if (aarch64_debug)
b277c936
PL		 380 {
381 debug_printf ("aarch64: prologue analysis gave up "
0a0da556 382 "addr=%s opcode=0x%x (orr x register)\n",
b277c936
PL		 383 core_addr_to_string_nz (start), insn);
384 }
07b287a0
MS		 385 break;
386 }
387 }
d9ebcbce 388 else if (inst.opcode->op == OP_STUR)
07b287a0 389 {
d9ebcbce
YQ		 390 unsigned rt = inst.operands[0].reg.regno;
391 unsigned rn = inst.operands[1].addr.base_regno;
75faf5c4 392 int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
d9ebcbce
YQ		 393
394 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
395 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
396 gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
397 gdb_assert (!inst.operands[1].addr.offset.is_reg);
398
75faf5c4
AH		 399 stack.store
400 (pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm),
401 size, regs[rt]);
07b287a0 402 }
d9ebcbce 403 else if ((inst.opcode->iclass == ldstpair_off
03bcd739
YQ		 404 || (inst.opcode->iclass == ldstpair_indexed
405 && inst.operands[2].addr.preind))
d9ebcbce 406 && strcmp ("stp", inst.opcode->name) == 0)
07b287a0 407 {
03bcd739 408 /* STP with addressing mode Pre-indexed and Base register. */
187f5d00
YQ		 409 unsigned rt1;
410 unsigned rt2;
d9ebcbce
YQ		 411 unsigned rn = inst.operands[2].addr.base_regno;
412 int32_t imm = inst.operands[2].addr.offset.imm;
75faf5c4 413 int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
d9ebcbce 414
187f5d00
YQ		 415 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
416 || inst.operands[0].type == AARCH64_OPND_Ft);
417 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
418 || inst.operands[1].type == AARCH64_OPND_Ft2);
d9ebcbce
YQ		 419 gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
420 gdb_assert (!inst.operands[2].addr.offset.is_reg);
421
07b287a0
MS		 422 /* If recording this store would invalidate the store area
423 (perhaps because rn is not known) then we should abandon
424 further prologue analysis. */
f7b7ed97 425 if (stack.store_would_trash (pv_add_constant (regs[rn], imm)))
07b287a0
MS		 426 break;
427
f7b7ed97 428 if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8)))
07b287a0
MS		 429 break;
430
187f5d00
YQ		 431 rt1 = inst.operands[0].reg.regno;
432 rt2 = inst.operands[1].reg.regno;
433 if (inst.operands[0].type == AARCH64_OPND_Ft)
434 {
187f5d00
YQ		 435 rt1 += AARCH64_X_REGISTER_COUNT;
436 rt2 += AARCH64_X_REGISTER_COUNT;
437 }
438
75faf5c4
AH		 439 stack.store (pv_add_constant (regs[rn], imm), size, regs[rt1]);
440 stack.store (pv_add_constant (regs[rn], imm + size), size, regs[rt2]);
14ac654f 441
d9ebcbce 442 if (inst.operands[2].addr.writeback)
93d96012 443 regs[rn] = pv_add_constant (regs[rn], imm);
07b287a0 444
07b287a0 445 }
432ec081
YQ		 446 else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
447 || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
448 && (inst.opcode->op == OP_STR_POS
449 || inst.opcode->op == OP_STRF_POS)))
450 && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
451 && strcmp ("str", inst.opcode->name) == 0)
452 {
453 /* STR (immediate) */
454 unsigned int rt = inst.operands[0].reg.regno;
455 int32_t imm = inst.operands[1].addr.offset.imm;
456 unsigned int rn = inst.operands[1].addr.base_regno;
75faf5c4 457 int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
432ec081
YQ		 458 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
459 || inst.operands[0].type == AARCH64_OPND_Ft);
460
461 if (inst.operands[0].type == AARCH64_OPND_Ft)
75faf5c4 462 rt += AARCH64_X_REGISTER_COUNT;
432ec081 463
75faf5c4 464 stack.store (pv_add_constant (regs[rn], imm), size, regs[rt]);
432ec081
YQ		 465 if (inst.operands[1].addr.writeback)
466 regs[rn] = pv_add_constant (regs[rn], imm);
467 }
d9ebcbce 468 else if (inst.opcode->iclass == testbranch)
07b287a0
MS		 469 {
470 /* Stop analysis on branch. */
471 break;
472 }
17e116a7
AH		 473 else if (inst.opcode->iclass == ic_system)
474 {
475 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
476 int ra_state_val = 0;
477
478 if (insn == 0xd503233f /* paciasp. */
479 || insn == 0xd503237f /* pacibsp. */)
480 {
481 /* Return addresses are mangled. */
482 ra_state_val = 1;
483 }
484 else if (insn == 0xd50323bf /* autiasp. */
485 || insn == 0xd50323ff /* autibsp. */)
486 {
487 /* Return addresses are not mangled. */
488 ra_state_val = 0;
489 }
490 else
491 {
492 if (aarch64_debug)
493 debug_printf ("aarch64: prologue analysis gave up addr=%s"
494 " opcode=0x%x (iclass)\n",
495 core_addr_to_string_nz (start), insn);
496 break;
497 }
498
499 if (tdep->has_pauth () && cache != nullptr)
500 trad_frame_set_value (cache->saved_regs,
501 tdep->pauth_ra_state_regnum,
502 ra_state_val);
503 }
07b287a0
MS		 504 else
505 {
506 if (aarch64_debug)
b277c936 507 {
0a0da556 508 debug_printf ("aarch64: prologue analysis gave up addr=%s"
b277c936
PL		 509 " opcode=0x%x\n",
510 core_addr_to_string_nz (start), insn);
511 }
07b287a0
MS		 512 break;
513 }
514 }
515
516 if (cache == NULL)
f7b7ed97 517 return start;
07b287a0
MS		 518
519 if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
520 {
521 /* Frame pointer is fp. Frame size is constant. */
522 cache->framereg = AARCH64_FP_REGNUM;
523 cache->framesize = -regs[AARCH64_FP_REGNUM].k;
524 }
525 else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
526 {
527 /* Try the stack pointer. */
528 cache->framesize = -regs[AARCH64_SP_REGNUM].k;
529 cache->framereg = AARCH64_SP_REGNUM;
530 }
531 else
532 {
533 /* We're just out of luck. We don't know where the frame is. */
534 cache->framereg = -1;
535 cache->framesize = 0;
536 }
537
538 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
539 {
540 CORE_ADDR offset;
541
f7b7ed97 542 if (stack.find_reg (gdbarch, i, &offset))
07b287a0
MS		 543 cache->saved_regs[i].addr = offset;
544 }
545
187f5d00
YQ		 546 for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
547 {
548 int regnum = gdbarch_num_regs (gdbarch);
549 CORE_ADDR offset;
550
f7b7ed97
TT		 551 if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT,
552 &offset))
187f5d00
YQ		 553 cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset;
554 }
555
07b287a0
MS		 556 return start;
557}
558
4d9a9006
YQ		 559static CORE_ADDR
560aarch64_analyze_prologue (struct gdbarch *gdbarch,
561 CORE_ADDR start, CORE_ADDR limit,
562 struct aarch64_prologue_cache *cache)
563{
564 instruction_reader reader;
565
566 return aarch64_analyze_prologue (gdbarch, start, limit, cache,
567 reader);
568}
569
570#if GDB_SELF_TEST
571
572namespace selftests {
573
574/* Instruction reader from manually cooked instruction sequences. */
575
576class instruction_reader_test : public abstract_instruction_reader
577{
578public:
579 template<size_t SIZE>
580 explicit instruction_reader_test (const uint32_t (&insns)[SIZE])
581 : m_insns (insns), m_insns_size (SIZE)
582 {}
583
584 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 585 override
4d9a9006
YQ		 586 {
587 SELF_CHECK (len == 4);
588 SELF_CHECK (memaddr % 4 == 0);
589 SELF_CHECK (memaddr / 4 < m_insns_size);
590
591 return m_insns[memaddr / 4];
592 }
593
594private:
595 const uint32_t *m_insns;
596 size_t m_insns_size;
597};
598
599static void
600aarch64_analyze_prologue_test (void)
601{
602 struct gdbarch_info info;
603
604 gdbarch_info_init (&info);
605 info.bfd_arch_info = bfd_scan_arch ("aarch64");
606
607 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
608 SELF_CHECK (gdbarch != NULL);
609
17e116a7
AH		 610 struct aarch64_prologue_cache cache;
611 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
612
613 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
614
4d9a9006
YQ		 615 /* Test the simple prologue in which frame pointer is used. */
616 {
4d9a9006
YQ		 617 static const uint32_t insns[] = {
618 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
619 0x910003fd, /* mov x29, sp */
620 0x97ffffe6, /* bl 0x400580 */
621 };
622 instruction_reader_test reader (insns);
623
624 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
625 SELF_CHECK (end == 4 * 2);
626
627 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
628 SELF_CHECK (cache.framesize == 272);
629
630 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
631 {
632 if (i == AARCH64_FP_REGNUM)
633 SELF_CHECK (cache.saved_regs[i].addr == -272);
634 else if (i == AARCH64_LR_REGNUM)
635 SELF_CHECK (cache.saved_regs[i].addr == -264);
636 else
637 SELF_CHECK (cache.saved_regs[i].addr == -1);
638 }
639
640 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
641 {
642 int regnum = gdbarch_num_regs (gdbarch);
643
644 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
645 == -1);
646 }
647 }
432ec081
YQ		 648
649 /* Test a prologue in which STR is used and frame pointer is not
650 used. */
651 {
432ec081
YQ		 652 static const uint32_t insns[] = {
653 0xf81d0ff3, /* str x19, [sp, #-48]! */
654 0xb9002fe0, /* str w0, [sp, #44] */
655 0xf90013e1, /* str x1, [sp, #32]*/
656 0xfd000fe0, /* str d0, [sp, #24] */
657 0xaa0203f3, /* mov x19, x2 */
658 0xf94013e0, /* ldr x0, [sp, #32] */
659 };
660 instruction_reader_test reader (insns);
661
68811f8f 662 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
432ec081
YQ		 663 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
664
665 SELF_CHECK (end == 4 * 5);
666
667 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
668 SELF_CHECK (cache.framesize == 48);
669
670 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
671 {
672 if (i == 1)
673 SELF_CHECK (cache.saved_regs[i].addr == -16);
674 else if (i == 19)
675 SELF_CHECK (cache.saved_regs[i].addr == -48);
676 else
677 SELF_CHECK (cache.saved_regs[i].addr == -1);
678 }
679
680 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
681 {
682 int regnum = gdbarch_num_regs (gdbarch);
683
684 if (i == 0)
685 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
686 == -24);
687 else
688 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
689 == -1);
690 }
691 }
17e116a7
AH		 692
693 /* Test a prologue in which there is a return address signing instruction. */
694 if (tdep->has_pauth ())
695 {
696 static const uint32_t insns[] = {
697 0xd503233f, /* paciasp */
698 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
699 0x910003fd, /* mov x29, sp */
700 0xf801c3f3, /* str x19, [sp, #28] */
701 0xb9401fa0, /* ldr x19, [x29, #28] */
702 };
703 instruction_reader_test reader (insns);
704
68811f8f 705 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
17e116a7
AH		 706 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache,
707 reader);
708
709 SELF_CHECK (end == 4 * 4);
710 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
711 SELF_CHECK (cache.framesize == 48);
712
713 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
714 {
715 if (i == 19)
716 SELF_CHECK (cache.saved_regs[i].addr == -20);
717 else if (i == AARCH64_FP_REGNUM)
718 SELF_CHECK (cache.saved_regs[i].addr == -48);
719 else if (i == AARCH64_LR_REGNUM)
720 SELF_CHECK (cache.saved_regs[i].addr == -40);
721 else
722 SELF_CHECK (cache.saved_regs[i].addr == -1);
723 }
724
725 if (tdep->has_pauth ())
726 {
727 SELF_CHECK (trad_frame_value_p (cache.saved_regs,
728 tdep->pauth_ra_state_regnum));
729 SELF_CHECK (cache.saved_regs[tdep->pauth_ra_state_regnum].addr == 1);
730 }
731 }
4d9a9006
YQ		 732}
733} // namespace selftests
734#endif /* GDB_SELF_TEST */
735
07b287a0
MS		 736/* Implement the "skip_prologue" gdbarch method. */
737
738static CORE_ADDR
739aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
740{
07b287a0 741 CORE_ADDR func_addr, limit_pc;
07b287a0
MS		 742
743 /* See if we can determine the end of the prologue via the symbol
744 table. If so, then return either PC, or the PC after the
745 prologue, whichever is greater. */
746 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
747 {
748 CORE_ADDR post_prologue_pc
749 = skip_prologue_using_sal (gdbarch, func_addr);
750
751 if (post_prologue_pc != 0)
325fac50 752 return std::max (pc, post_prologue_pc);
07b287a0
MS		 753 }
754
755 /* Can't determine prologue from the symbol table, need to examine
756 instructions. */
757
758 /* Find an upper limit on the function prologue using the debug
759 information. If the debug information could not be used to
760 provide that bound, then use an arbitrary large number as the
761 upper bound. */
762 limit_pc = skip_prologue_using_sal (gdbarch, pc);
763 if (limit_pc == 0)
764 limit_pc = pc + 128; /* Magic. */
765
766 /* Try disassembling prologue. */
767 return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
768}
769
770/* Scan the function prologue for THIS_FRAME and populate the prologue
771 cache CACHE. */
772
773static void
774aarch64_scan_prologue (struct frame_info *this_frame,
775 struct aarch64_prologue_cache *cache)
776{
777 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
778 CORE_ADDR prologue_start;
779 CORE_ADDR prologue_end;
780 CORE_ADDR prev_pc = get_frame_pc (this_frame);
781 struct gdbarch *gdbarch = get_frame_arch (this_frame);
782
db634143
PL		 783 cache->prev_pc = prev_pc;
784
07b287a0
MS		 785 /* Assume we do not find a frame. */
786 cache->framereg = -1;
787 cache->framesize = 0;
788
789 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
790 &prologue_end))
791 {
792 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
793
794 if (sal.line == 0)
795 {
796 /* No line info so use the current PC. */
797 prologue_end = prev_pc;
798 }
799 else if (sal.end < prologue_end)
800 {
801 /* The next line begins after the function end. */
802 prologue_end = sal.end;
803 }
804
325fac50 805 prologue_end = std::min (prologue_end, prev_pc);
07b287a0
MS		 806 aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
807 }
808 else
809 {
810 CORE_ADDR frame_loc;
07b287a0
MS		 811
812 frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
813 if (frame_loc == 0)
814 return;
815
816 cache->framereg = AARCH64_FP_REGNUM;
817 cache->framesize = 16;
818 cache->saved_regs[29].addr = 0;
819 cache->saved_regs[30].addr = 8;
820 }
821}
822
7dfa3edc
PL		 823/* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
824 function may throw an exception if the inferior's registers or memory is
825 not available. */
07b287a0 826
7dfa3edc
PL		 827static void
828aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
829 struct aarch64_prologue_cache *cache)
07b287a0 830{
07b287a0
MS		 831 CORE_ADDR unwound_fp;
832 int reg;
833
07b287a0
MS		 834 aarch64_scan_prologue (this_frame, cache);
835
836 if (cache->framereg == -1)
7dfa3edc 837 return;
07b287a0
MS		 838
839 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
840 if (unwound_fp == 0)
7dfa3edc 841 return;
07b287a0
MS		 842
843 cache->prev_sp = unwound_fp + cache->framesize;
844
845 /* Calculate actual addresses of saved registers using offsets
846 determined by aarch64_analyze_prologue. */
847 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
848 if (trad_frame_addr_p (cache->saved_regs, reg))
849 cache->saved_regs[reg].addr += cache->prev_sp;
850
db634143
PL		 851 cache->func = get_frame_func (this_frame);
852
7dfa3edc
PL		 853 cache->available_p = 1;
854}
855
856/* Allocate and fill in *THIS_CACHE with information about the prologue of
857 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
858 Return a pointer to the current aarch64_prologue_cache in
859 *THIS_CACHE. */
860
861static struct aarch64_prologue_cache *
862aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
863{
864 struct aarch64_prologue_cache *cache;
865
866 if (*this_cache != NULL)
9a3c8263 867 return (struct aarch64_prologue_cache *) *this_cache;
7dfa3edc
PL		 868
869 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
870 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
871 *this_cache = cache;
872
a70b8144 873 try
7dfa3edc
PL		 874 {
875 aarch64_make_prologue_cache_1 (this_frame, cache);
876 }
230d2906 877 catch (const gdb_exception_error &ex)
7dfa3edc
PL		 878 {
879 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 880 throw;
7dfa3edc 881 }
7dfa3edc 882
07b287a0
MS		 883 return cache;
884}
885
7dfa3edc
PL		 886/* Implement the "stop_reason" frame_unwind method. */
887
888static enum unwind_stop_reason
889aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame,
890 void **this_cache)
891{
892 struct aarch64_prologue_cache *cache
893 = aarch64_make_prologue_cache (this_frame, this_cache);
894
895 if (!cache->available_p)
896 return UNWIND_UNAVAILABLE;
897
898 /* Halt the backtrace at "_start". */
899 if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
900 return UNWIND_OUTERMOST;
901
902 /* We've hit a wall, stop. */
903 if (cache->prev_sp == 0)
904 return UNWIND_OUTERMOST;
905
906 return UNWIND_NO_REASON;
907}
908
07b287a0
MS		 909/* Our frame ID for a normal frame is the current function's starting
910 PC and the caller's SP when we were called. */
911
912static void
913aarch64_prologue_this_id (struct frame_info *this_frame,
914 void **this_cache, struct frame_id *this_id)
915{
7c8edfae
PL		 916 struct aarch64_prologue_cache *cache
917 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0 918
7dfa3edc
PL		 919 if (!cache->available_p)
920 *this_id = frame_id_build_unavailable_stack (cache->func);
921 else
922 *this_id = frame_id_build (cache->prev_sp, cache->func);
07b287a0
MS		 923}
924
925/* Implement the "prev_register" frame_unwind method. */
926
927static struct value *
928aarch64_prologue_prev_register (struct frame_info *this_frame,
929 void **this_cache, int prev_regnum)
930{
7c8edfae
PL		 931 struct aarch64_prologue_cache *cache
932 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 933
934 /* If we are asked to unwind the PC, then we need to return the LR
935 instead. The prologue may save PC, but it will point into this
936 frame's prologue, not the next frame's resume location. */
937 if (prev_regnum == AARCH64_PC_REGNUM)
938 {
939 CORE_ADDR lr;
17e116a7
AH		 940 struct gdbarch *gdbarch = get_frame_arch (this_frame);
941 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
07b287a0
MS		 942
943 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
17e116a7
AH		 944
945 if (tdep->has_pauth ()
946 && trad_frame_value_p (cache->saved_regs,
947 tdep->pauth_ra_state_regnum))
3d31bc39 948 lr = aarch64_frame_unmask_lr (tdep, this_frame, lr);
17e116a7 949
07b287a0
MS		 950 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
951 }
952
953 /* SP is generally not saved to the stack, but this frame is
954 identified by the next frame's stack pointer at the time of the
955 call. The value was already reconstructed into PREV_SP. */
956 /*
957 +----------+ ^
958 | saved lr | |
959 +->| saved fp |--+
960 | | |
961 | | | <- Previous SP
962 | +----------+
963 | | saved lr |
964 +--| saved fp |<- FP
965 | |
966 | |<- SP
967 +----------+ */
968 if (prev_regnum == AARCH64_SP_REGNUM)
969 return frame_unwind_got_constant (this_frame, prev_regnum,
970 cache->prev_sp);
971
972 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
973 prev_regnum);
974}
975
976/* AArch64 prologue unwinder. */
977struct frame_unwind aarch64_prologue_unwind =
978{
979 NORMAL_FRAME,
7dfa3edc 980 aarch64_prologue_frame_unwind_stop_reason,
07b287a0
MS		 981 aarch64_prologue_this_id,
982 aarch64_prologue_prev_register,
983 NULL,
984 default_frame_sniffer
985};
986
8b61f75d
PL		 987/* Allocate and fill in *THIS_CACHE with information about the prologue of
988 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
989 Return a pointer to the current aarch64_prologue_cache in
990 *THIS_CACHE. */
07b287a0
MS		 991
992static struct aarch64_prologue_cache *
8b61f75d 993aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache)
07b287a0 994{
07b287a0 995 struct aarch64_prologue_cache *cache;
8b61f75d
PL		 996
997 if (*this_cache != NULL)
9a3c8263 998 return (struct aarch64_prologue_cache *) *this_cache;
07b287a0
MS		 999
1000 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
1001 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
8b61f75d 1002 *this_cache = cache;
07b287a0 1003
a70b8144 1004 try
02a2a705
PL		 1005 {
1006 cache->prev_sp = get_frame_register_unsigned (this_frame,
1007 AARCH64_SP_REGNUM);
1008 cache->prev_pc = get_frame_pc (this_frame);
1009 cache->available_p = 1;
1010 }
230d2906 1011 catch (const gdb_exception_error &ex)
02a2a705
PL		 1012 {
1013 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 1014 throw;
02a2a705 1015 }
07b287a0
MS		 1016
1017 return cache;
1018}
1019
02a2a705
PL		 1020/* Implement the "stop_reason" frame_unwind method. */
1021
1022static enum unwind_stop_reason
1023aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame,
1024 void **this_cache)
1025{
1026 struct aarch64_prologue_cache *cache
1027 = aarch64_make_stub_cache (this_frame, this_cache);
1028
1029 if (!cache->available_p)
1030 return UNWIND_UNAVAILABLE;
1031
1032 return UNWIND_NO_REASON;
1033}
1034
07b287a0
MS		 1035/* Our frame ID for a stub frame is the current SP and LR. */
1036
1037static void
1038aarch64_stub_this_id (struct frame_info *this_frame,
1039 void **this_cache, struct frame_id *this_id)
1040{
8b61f75d
PL		 1041 struct aarch64_prologue_cache *cache
1042 = aarch64_make_stub_cache (this_frame, this_cache);
07b287a0 1043
02a2a705
PL		 1044 if (cache->available_p)
1045 *this_id = frame_id_build (cache->prev_sp, cache->prev_pc);
1046 else
1047 *this_id = frame_id_build_unavailable_stack (cache->prev_pc);
07b287a0
MS		 1048}
1049
1050/* Implement the "sniffer" frame_unwind method. */
1051
1052static int
1053aarch64_stub_unwind_sniffer (const struct frame_unwind *self,
1054 struct frame_info *this_frame,
1055 void **this_prologue_cache)
1056{
1057 CORE_ADDR addr_in_block;
1058 gdb_byte dummy[4];
1059
1060 addr_in_block = get_frame_address_in_block (this_frame);
3e5d3a5a 1061 if (in_plt_section (addr_in_block)
07b287a0
MS		 1062 /* We also use the stub winder if the target memory is unreadable
1063 to avoid having the prologue unwinder trying to read it. */
1064 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
1065 return 1;
1066
1067 return 0;
1068}
1069
1070/* AArch64 stub unwinder. */
1071struct frame_unwind aarch64_stub_unwind =
1072{
1073 NORMAL_FRAME,
02a2a705 1074 aarch64_stub_frame_unwind_stop_reason,
07b287a0
MS		 1075 aarch64_stub_this_id,
1076 aarch64_prologue_prev_register,
1077 NULL,
1078 aarch64_stub_unwind_sniffer
1079};
1080
1081/* Return the frame base address of *THIS_FRAME. */
1082
1083static CORE_ADDR
1084aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache)
1085{
7c8edfae
PL		 1086 struct aarch64_prologue_cache *cache
1087 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 1088
1089 return cache->prev_sp - cache->framesize;
1090}
1091
1092/* AArch64 default frame base information. */
1093struct frame_base aarch64_normal_base =
1094{
1095 &aarch64_prologue_unwind,
1096 aarch64_normal_frame_base,
1097 aarch64_normal_frame_base,
1098 aarch64_normal_frame_base
1099};
1100
07b287a0
MS		 1101/* Return the value of the REGNUM register in the previous frame of
1102 *THIS_FRAME. */
1103
1104static struct value *
1105aarch64_dwarf2_prev_register (struct frame_info *this_frame,
1106 void **this_cache, int regnum)
1107{
11e1b75f 1108 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
07b287a0
MS		 1109 CORE_ADDR lr;
1110
1111 switch (regnum)
1112 {
1113 case AARCH64_PC_REGNUM:
1114 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
3d31bc39 1115 lr = aarch64_frame_unmask_lr (tdep, this_frame, lr);
07b287a0
MS		 1116 return frame_unwind_got_constant (this_frame, regnum, lr);
1117
1118 default:
1119 internal_error (__FILE__, __LINE__,
1120 _("Unexpected register %d"), regnum);
1121 }
1122}
1123
11e1b75f
AH		 1124static const unsigned char op_lit0 = DW_OP_lit0;
1125static const unsigned char op_lit1 = DW_OP_lit1;
1126
07b287a0
MS		 1127/* Implement the "init_reg" dwarf2_frame_ops method. */
1128
1129static void
1130aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1131 struct dwarf2_frame_state_reg *reg,
1132 struct frame_info *this_frame)
1133{
11e1b75f
AH		 1134 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1135
07b287a0
MS		 1136 switch (regnum)
1137 {
1138 case AARCH64_PC_REGNUM:
1139 reg->how = DWARF2_FRAME_REG_FN;
1140 reg->loc.fn = aarch64_dwarf2_prev_register;
11e1b75f
AH		 1141 return;
1142
07b287a0
MS		 1143 case AARCH64_SP_REGNUM:
1144 reg->how = DWARF2_FRAME_REG_CFA;
11e1b75f
AH		 1145 return;
1146 }
1147
1148 /* Init pauth registers. */
1149 if (tdep->has_pauth ())
1150 {
1151 if (regnum == tdep->pauth_ra_state_regnum)
1152 {
1153 /* Initialize RA_STATE to zero. */
1154 reg->how = DWARF2_FRAME_REG_SAVED_VAL_EXP;
1155 reg->loc.exp.start = &op_lit0;
1156 reg->loc.exp.len = 1;
1157 return;
1158 }
1159 else if (regnum == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
1160 || regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base))
1161 {
1162 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1163 return;
1164 }
07b287a0
MS		 1165 }
1166}
1167
11e1b75f
AH		 1168/* Implement the execute_dwarf_cfa_vendor_op method. */
1169
1170static bool
1171aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op,
1172 struct dwarf2_frame_state *fs)
1173{
1174 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1175 struct dwarf2_frame_state_reg *ra_state;
1176
8fca4da0 1177 if (op == DW_CFA_AARCH64_negate_ra_state)
11e1b75f 1178 {
8fca4da0
AH		 1179 /* On systems without pauth, treat as a nop. */
1180 if (!tdep->has_pauth ())
1181 return true;
1182
11e1b75f
AH		 1183 /* Allocate RA_STATE column if it's not allocated yet. */
1184 fs->regs.alloc_regs (AARCH64_DWARF_PAUTH_RA_STATE + 1);
1185
1186 /* Toggle the status of RA_STATE between 0 and 1. */
1187 ra_state = &(fs->regs.reg[AARCH64_DWARF_PAUTH_RA_STATE]);
1188 ra_state->how = DWARF2_FRAME_REG_SAVED_VAL_EXP;
1189
1190 if (ra_state->loc.exp.start == nullptr
1191 || ra_state->loc.exp.start == &op_lit0)
1192 ra_state->loc.exp.start = &op_lit1;
1193 else
1194 ra_state->loc.exp.start = &op_lit0;
1195
1196 ra_state->loc.exp.len = 1;
1197
1198 return true;
1199 }
1200
1201 return false;
1202}
1203
5133a315
LM		 1204/* Used for matching BRK instructions for AArch64. */
1205static constexpr uint32_t BRK_INSN_MASK = 0xffe0001f;
1206static constexpr uint32_t BRK_INSN_BASE = 0xd4200000;
1207
1208/* Implementation of gdbarch_program_breakpoint_here_p for aarch64. */
1209
1210static bool
1211aarch64_program_breakpoint_here_p (gdbarch *gdbarch, CORE_ADDR address)
1212{
1213 const uint32_t insn_len = 4;
1214 gdb_byte target_mem[4];
1215
1216 /* Enable the automatic memory restoration from breakpoints while
1217 we read the memory. Otherwise we may find temporary breakpoints, ones
1218 inserted by GDB, and flag them as permanent breakpoints. */
1219 scoped_restore restore_memory
1220 = make_scoped_restore_show_memory_breakpoints (0);
1221
1222 if (target_read_memory (address, target_mem, insn_len) == 0)
1223 {
1224 uint32_t insn =
1225 (uint32_t) extract_unsigned_integer (target_mem, insn_len,
1226 gdbarch_byte_order_for_code (gdbarch));
1227
1228 /* Check if INSN is a BRK instruction pattern. There are multiple choices
1229 of such instructions with different immediate values. Different OS'
1230 may use a different variation, but they have the same outcome. */
1231 return ((insn & BRK_INSN_MASK) == BRK_INSN_BASE);
1232 }
1233
1234 return false;
1235}
1236
07b287a0
MS		 1237/* When arguments must be pushed onto the stack, they go on in reverse
1238 order. The code below implements a FILO (stack) to do this. */
1239
89055eaa 1240struct stack_item_t
07b287a0 1241{
c3c87445
YQ		 1242 /* Value to pass on stack. It can be NULL if this item is for stack
1243 padding. */
7c543f7b 1244 const gdb_byte *data;
07b287a0
MS		 1245
1246 /* Size in bytes of value to pass on stack. */
1247 int len;
89055eaa 1248};
07b287a0 1249
b907456c
AB		 1250/* Implement the gdbarch type alignment method, overrides the generic
1251 alignment algorithm for anything that is aarch64 specific. */
07b287a0 1252
b907456c
AB		 1253static ULONGEST
1254aarch64_type_align (gdbarch *gdbarch, struct type *t)
07b287a0 1255{
07b287a0 1256 t = check_typedef (t);
b907456c 1257 if (TYPE_CODE (t) == TYPE_CODE_ARRAY && TYPE_VECTOR (t))
07b287a0 1258 {
b907456c
AB		 1259 /* Use the natural alignment for vector types (the same for
1260 scalar type), but the maximum alignment is 128-bit. */
1261 if (TYPE_LENGTH (t) > 16)
1262 return 16;
238f2452 1263 else
b907456c 1264 return TYPE_LENGTH (t);
07b287a0 1265 }
b907456c
AB		 1266
1267 /* Allow the common code to calculate the alignment. */
1268 return 0;
07b287a0
MS		 1269}
1270
ea92689a
AH		 1271/* Worker function for aapcs_is_vfp_call_or_return_candidate.
1272
1273 Return the number of register required, or -1 on failure.
1274
1275 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1276 to the element, else fail if the type of this element does not match the
1277 existing value. */
1278
1279static int
1280aapcs_is_vfp_call_or_return_candidate_1 (struct type *type,
1281 struct type **fundamental_type)
1282{
1283 if (type == nullptr)
1284 return -1;
1285
1286 switch (TYPE_CODE (type))
1287 {
1288 case TYPE_CODE_FLT:
1289 if (TYPE_LENGTH (type) > 16)
1290 return -1;
1291
1292 if (*fundamental_type == nullptr)
1293 *fundamental_type = type;
1294 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
1295 || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
1296 return -1;
1297
1298 return 1;
1299
1300 case TYPE_CODE_COMPLEX:
1301 {
1302 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
1303 if (TYPE_LENGTH (target_type) > 16)
1304 return -1;
1305
1306 if (*fundamental_type == nullptr)
1307 *fundamental_type = target_type;
1308 else if (TYPE_LENGTH (target_type) != TYPE_LENGTH (*fundamental_type)
1309 || TYPE_CODE (target_type) != TYPE_CODE (*fundamental_type))
1310 return -1;
1311
1312 return 2;
1313 }
1314
1315 case TYPE_CODE_ARRAY:
1316 {
1317 if (TYPE_VECTOR (type))
1318 {
1319 if (TYPE_LENGTH (type) != 8 && TYPE_LENGTH (type) != 16)
1320 return -1;
1321
1322 if (*fundamental_type == nullptr)
1323 *fundamental_type = type;
1324 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
1325 || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
1326 return -1;
1327
1328 return 1;
1329 }
1330 else
1331 {
1332 struct type *target_type = TYPE_TARGET_TYPE (type);
1333 int count = aapcs_is_vfp_call_or_return_candidate_1
1334 (target_type, fundamental_type);
1335
1336 if (count == -1)
1337 return count;
1338
d4718d5c 1339 count *= (TYPE_LENGTH (type) / TYPE_LENGTH (target_type));
ea92689a
AH		 1340 return count;
1341 }
1342 }
1343
1344 case TYPE_CODE_STRUCT:
1345 case TYPE_CODE_UNION:
1346 {
1347 int count = 0;
1348
1349 for (int i = 0; i < TYPE_NFIELDS (type); i++)
1350 {
353229bf
AH		 1351 /* Ignore any static fields. */
1352 if (field_is_static (&TYPE_FIELD (type, i)))
1353 continue;
1354
ea92689a
AH		 1355 struct type *member = check_typedef (TYPE_FIELD_TYPE (type, i));
1356
1357 int sub_count = aapcs_is_vfp_call_or_return_candidate_1
1358 (member, fundamental_type);
1359 if (sub_count == -1)
1360 return -1;
1361 count += sub_count;
1362 }
73021deb
AH		 1363
1364 /* Ensure there is no padding between the fields (allowing for empty
1365 zero length structs) */
1366 int ftype_length = (*fundamental_type == nullptr)
1367 ? 0 : TYPE_LENGTH (*fundamental_type);
1368 if (count * ftype_length != TYPE_LENGTH (type))
1369 return -1;
1370
ea92689a
AH		 1371 return count;
1372 }
1373
1374 default:
1375 break;
1376 }
1377
1378 return -1;
1379}
1380
1381/* Return true if an argument, whose type is described by TYPE, can be passed or
1382 returned in simd/fp registers, providing enough parameter passing registers
1383 are available. This is as described in the AAPCS64.
1384
1385 Upon successful return, *COUNT returns the number of needed registers,
1386 *FUNDAMENTAL_TYPE contains the type of those registers.
1387
1388 Candidate as per the AAPCS64 5.4.2.C is either a:
1389 - float.
1390 - short-vector.
1391 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1392 all the members are floats and has at most 4 members.
1393 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1394 all the members are short vectors and has at most 4 members.
1395 - Complex (7.1.1)
1396
1397 Note that HFAs and HVAs can include nested structures and arrays. */
1398
0e745c60 1399static bool
ea92689a
AH		 1400aapcs_is_vfp_call_or_return_candidate (struct type *type, int *count,
1401 struct type **fundamental_type)
1402{
1403 if (type == nullptr)
1404 return false;
1405
1406 *fundamental_type = nullptr;
1407
1408 int ag_count = aapcs_is_vfp_call_or_return_candidate_1 (type,
1409 fundamental_type);
1410
1411 if (ag_count > 0 && ag_count <= HA_MAX_NUM_FLDS)
1412 {
1413 *count = ag_count;
1414 return true;
1415 }
1416 else
1417 return false;
1418}
1419
07b287a0
MS		 1420/* AArch64 function call information structure. */
1421struct aarch64_call_info
1422{
1423 /* the current argument number. */
89055eaa 1424 unsigned argnum = 0;
07b287a0
MS		 1425
1426 /* The next general purpose register number, equivalent to NGRN as
1427 described in the AArch64 Procedure Call Standard. */
89055eaa 1428 unsigned ngrn = 0;
07b287a0
MS		 1429
1430 /* The next SIMD and floating point register number, equivalent to
1431 NSRN as described in the AArch64 Procedure Call Standard. */
89055eaa 1432 unsigned nsrn = 0;
07b287a0
MS		 1433
1434 /* The next stacked argument address, equivalent to NSAA as
1435 described in the AArch64 Procedure Call Standard. */
89055eaa 1436 unsigned nsaa = 0;
07b287a0
MS		 1437
1438 /* Stack item vector. */
89055eaa 1439 std::vector<stack_item_t> si;
07b287a0
MS		 1440};
1441
1442/* Pass a value in a sequence of consecutive X registers. The caller
30baf67b 1443 is responsible for ensuring sufficient registers are available. */
07b287a0
MS		 1444
1445static void
1446pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
1447 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1448 struct value *arg)
07b287a0
MS		 1449{
1450 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1451 int len = TYPE_LENGTH (type);
1452 enum type_code typecode = TYPE_CODE (type);
1453 int regnum = AARCH64_X0_REGNUM + info->ngrn;
8e80f9d1 1454 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1455
1456 info->argnum++;
1457
1458 while (len > 0)
1459 {
1460 int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE;
1461 CORE_ADDR regval = extract_unsigned_integer (buf, partial_len,
1462 byte_order);
1463
1464
1465 /* Adjust sub-word struct/union args when big-endian. */
1466 if (byte_order == BFD_ENDIAN_BIG
1467 && partial_len < X_REGISTER_SIZE
1468 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
1469 regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
1470
1471 if (aarch64_debug)
b277c936
PL		 1472 {
1473 debug_printf ("arg %d in %s = 0x%s\n", info->argnum,
1474 gdbarch_register_name (gdbarch, regnum),
1475 phex (regval, X_REGISTER_SIZE));
1476 }
07b287a0
MS		 1477 regcache_cooked_write_unsigned (regcache, regnum, regval);
1478 len -= partial_len;
1479 buf += partial_len;
1480 regnum++;
1481 }
1482}
1483
1484/* Attempt to marshall a value in a V register. Return 1 if
1485 successful, or 0 if insufficient registers are available. This
1486 function, unlike the equivalent pass_in_x() function does not
1487 handle arguments spread across multiple registers. */
1488
1489static int
1490pass_in_v (struct gdbarch *gdbarch,
1491 struct regcache *regcache,
1492 struct aarch64_call_info *info,
0735fddd 1493 int len, const bfd_byte *buf)
07b287a0
MS		 1494{
1495 if (info->nsrn < 8)
1496 {
07b287a0 1497 int regnum = AARCH64_V0_REGNUM + info->nsrn;
3ff2c72e
AH		 1498 /* Enough space for a full vector register. */
1499 gdb_byte reg[register_size (gdbarch, regnum)];
1500 gdb_assert (len <= sizeof (reg));
07b287a0
MS		 1501
1502 info->argnum++;
1503 info->nsrn++;
1504
0735fddd
YQ		 1505 memset (reg, 0, sizeof (reg));
1506 /* PCS C.1, the argument is allocated to the least significant
1507 bits of V register. */
1508 memcpy (reg, buf, len);
b66f5587 1509 regcache->cooked_write (regnum, reg);
0735fddd 1510
07b287a0 1511 if (aarch64_debug)
b277c936
PL		 1512 {
1513 debug_printf ("arg %d in %s\n", info->argnum,
1514 gdbarch_register_name (gdbarch, regnum));
1515 }
07b287a0
MS		 1516 return 1;
1517 }
1518 info->nsrn = 8;
1519 return 0;
1520}
1521
1522/* Marshall an argument onto the stack. */
1523
1524static void
1525pass_on_stack (struct aarch64_call_info *info, struct type *type,
8e80f9d1 1526 struct value *arg)
07b287a0 1527{
8e80f9d1 1528 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1529 int len = TYPE_LENGTH (type);
1530 int align;
1531 stack_item_t item;
1532
1533 info->argnum++;
1534
b907456c 1535 align = type_align (type);
07b287a0
MS		 1536
1537 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1538 Natural alignment of the argument's type. */
1539 align = align_up (align, 8);
1540
1541 /* The AArch64 PCS requires at most doubleword alignment. */
1542 if (align > 16)
1543 align = 16;
1544
1545 if (aarch64_debug)
b277c936
PL		 1546 {
1547 debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
1548 info->nsaa);
1549 }
07b287a0
MS		 1550
1551 item.len = len;
1552 item.data = buf;
89055eaa 1553 info->si.push_back (item);
07b287a0
MS		 1554
1555 info->nsaa += len;
1556 if (info->nsaa & (align - 1))
1557 {
1558 /* Push stack alignment padding. */
1559 int pad = align - (info->nsaa & (align - 1));
1560
1561 item.len = pad;
c3c87445 1562 item.data = NULL;
07b287a0 1563
89055eaa 1564 info->si.push_back (item);
07b287a0
MS		 1565 info->nsaa += pad;
1566 }
1567}
1568
1569/* Marshall an argument into a sequence of one or more consecutive X
1570 registers or, if insufficient X registers are available then onto
1571 the stack. */
1572
1573static void
1574pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache,
1575 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1576 struct value *arg)
07b287a0
MS		 1577{
1578 int len = TYPE_LENGTH (type);
1579 int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE;
1580
1581 /* PCS C.13 - Pass in registers if we have enough spare */
1582 if (info->ngrn + nregs <= 8)
1583 {
8e80f9d1 1584 pass_in_x (gdbarch, regcache, info, type, arg);
07b287a0
MS		 1585 info->ngrn += nregs;
1586 }
1587 else
1588 {
1589 info->ngrn = 8;
8e80f9d1 1590 pass_on_stack (info, type, arg);
07b287a0
MS		 1591 }
1592}
1593
0e745c60
AH		 1594/* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1595 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1596 registers. A return value of false is an error state as the value will have
1597 been partially passed to the stack. */
1598static bool
1599pass_in_v_vfp_candidate (struct gdbarch *gdbarch, struct regcache *regcache,
1600 struct aarch64_call_info *info, struct type *arg_type,
1601 struct value *arg)
07b287a0 1602{
0e745c60
AH		 1603 switch (TYPE_CODE (arg_type))
1604 {
1605 case TYPE_CODE_FLT:
1606 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1607 value_contents (arg));
1608 break;
1609
1610 case TYPE_CODE_COMPLEX:
1611 {
1612 const bfd_byte *buf = value_contents (arg);
1613 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (arg_type));
1614
1615 if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1616 buf))
1617 return false;
1618
1619 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1620 buf + TYPE_LENGTH (target_type));
1621 }
1622
1623 case TYPE_CODE_ARRAY:
1624 if (TYPE_VECTOR (arg_type))
1625 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1626 value_contents (arg));
1627 /* fall through. */
1628
1629 case TYPE_CODE_STRUCT:
1630 case TYPE_CODE_UNION:
1631 for (int i = 0; i < TYPE_NFIELDS (arg_type); i++)
1632 {
353229bf
AH		 1633 /* Don't include static fields. */
1634 if (field_is_static (&TYPE_FIELD (arg_type, i)))
1635 continue;
1636
0e745c60
AH		 1637 struct value *field = value_primitive_field (arg, 0, i, arg_type);
1638 struct type *field_type = check_typedef (value_type (field));
1639
1640 if (!pass_in_v_vfp_candidate (gdbarch, regcache, info, field_type,
1641 field))
1642 return false;
1643 }
1644 return true;
1645
1646 default:
1647 return false;
1648 }
07b287a0
MS		 1649}
1650
1651/* Implement the "push_dummy_call" gdbarch method. */
1652
1653static CORE_ADDR
1654aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1655 struct regcache *regcache, CORE_ADDR bp_addr,
1656 int nargs,
cf84fa6b
AH		 1657 struct value **args, CORE_ADDR sp,
1658 function_call_return_method return_method,
07b287a0
MS		 1659 CORE_ADDR struct_addr)
1660{
07b287a0 1661 int argnum;
07b287a0 1662 struct aarch64_call_info info;
07b287a0 1663
07b287a0
MS		 1664 /* We need to know what the type of the called function is in order
1665 to determine the number of named/anonymous arguments for the
1666 actual argument placement, and the return type in order to handle
1667 return value correctly.
1668
1669 The generic code above us views the decision of return in memory
1670 or return in registers as a two stage processes. The language
1671 handler is consulted first and may decide to return in memory (eg
1672 class with copy constructor returned by value), this will cause
1673 the generic code to allocate space AND insert an initial leading
1674 argument.
1675
1676 If the language code does not decide to pass in memory then the
1677 target code is consulted.
1678
1679 If the language code decides to pass in memory we want to move
1680 the pointer inserted as the initial argument from the argument
1681 list and into X8, the conventional AArch64 struct return pointer
38a72da0 1682 register. */
07b287a0
MS		 1683
1684 /* Set the return address. For the AArch64, the return breakpoint
1685 is always at BP_ADDR. */
1686 regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr);
1687
38a72da0
AH		 1688 /* If we were given an initial argument for the return slot, lose it. */
1689 if (return_method == return_method_hidden_param)
07b287a0
MS		 1690 {
1691 args++;
1692 nargs--;
1693 }
1694
1695 /* The struct_return pointer occupies X8. */
38a72da0 1696 if (return_method != return_method_normal)
07b287a0
MS		 1697 {
1698 if (aarch64_debug)
b277c936
PL		 1699 {
1700 debug_printf ("struct return in %s = 0x%s\n",
1701 gdbarch_register_name (gdbarch,
1702 AARCH64_STRUCT_RETURN_REGNUM),
1703 paddress (gdbarch, struct_addr));
1704 }
07b287a0
MS		 1705 regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
1706 struct_addr);
1707 }
1708
1709 for (argnum = 0; argnum < nargs; argnum++)
1710 {
1711 struct value *arg = args[argnum];
0e745c60
AH		 1712 struct type *arg_type, *fundamental_type;
1713 int len, elements;
07b287a0
MS		 1714
1715 arg_type = check_typedef (value_type (arg));
1716 len = TYPE_LENGTH (arg_type);
1717
0e745c60
AH		 1718 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1719 if there are enough spare registers. */
1720 if (aapcs_is_vfp_call_or_return_candidate (arg_type, &elements,
1721 &fundamental_type))
1722 {
1723 if (info.nsrn + elements <= 8)
1724 {
1725 /* We know that we have sufficient registers available therefore
1726 this will never need to fallback to the stack. */
1727 if (!pass_in_v_vfp_candidate (gdbarch, regcache, &info, arg_type,
1728 arg))
1729 gdb_assert_not_reached ("Failed to push args");
1730 }
1731 else
1732 {
1733 info.nsrn = 8;
1734 pass_on_stack (&info, arg_type, arg);
1735 }
1736 continue;
1737 }
1738
07b287a0
MS		 1739 switch (TYPE_CODE (arg_type))
1740 {
1741 case TYPE_CODE_INT:
1742 case TYPE_CODE_BOOL:
1743 case TYPE_CODE_CHAR:
1744 case TYPE_CODE_RANGE:
1745 case TYPE_CODE_ENUM:
1746 if (len < 4)
1747 {
1748 /* Promote to 32 bit integer. */
1749 if (TYPE_UNSIGNED (arg_type))
1750 arg_type = builtin_type (gdbarch)->builtin_uint32;
1751 else
1752 arg_type = builtin_type (gdbarch)->builtin_int32;
1753 arg = value_cast (arg_type, arg);
1754 }
8e80f9d1 1755 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1756 break;
1757
07b287a0
MS		 1758 case TYPE_CODE_STRUCT:
1759 case TYPE_CODE_ARRAY:
1760 case TYPE_CODE_UNION:
0e745c60 1761 if (len > 16)
07b287a0
MS		 1762 {
1763 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1764 invisible reference. */
1765
1766 /* Allocate aligned storage. */
1767 sp = align_down (sp - len, 16);
1768
1769 /* Write the real data into the stack. */
1770 write_memory (sp, value_contents (arg), len);
1771
1772 /* Construct the indirection. */
1773 arg_type = lookup_pointer_type (arg_type);
1774 arg = value_from_pointer (arg_type, sp);
8e80f9d1 1775 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1776 }
1777 else
1778 /* PCS C.15 / C.18 multiple values pass. */
8e80f9d1 1779 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1780 break;
1781
1782 default:
8e80f9d1 1783 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1784 break;
1785 }
1786 }
1787
1788 /* Make sure stack retains 16 byte alignment. */
1789 if (info.nsaa & 15)
1790 sp -= 16 - (info.nsaa & 15);
1791
89055eaa 1792 while (!info.si.empty ())
07b287a0 1793 {
89055eaa 1794 const stack_item_t &si = info.si.back ();
07b287a0 1795
89055eaa
TT		 1796 sp -= si.len;
1797 if (si.data != NULL)
1798 write_memory (sp, si.data, si.len);
1799 info.si.pop_back ();
07b287a0
MS		 1800 }
1801
07b287a0
MS		 1802 /* Finally, update the SP register. */
1803 regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp);
1804
1805 return sp;
1806}
1807
1808/* Implement the "frame_align" gdbarch method. */
1809
1810static CORE_ADDR
1811aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1812{
1813 /* Align the stack to sixteen bytes. */
1814 return sp & ~(CORE_ADDR) 15;
1815}
1816
1817/* Return the type for an AdvSISD Q register. */
1818
1819static struct type *
1820aarch64_vnq_type (struct gdbarch *gdbarch)
1821{
1822 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1823
1824 if (tdep->vnq_type == NULL)
1825 {
1826 struct type *t;
1827 struct type *elem;
1828
1829 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1830 TYPE_CODE_UNION);
1831
1832 elem = builtin_type (gdbarch)->builtin_uint128;
1833 append_composite_type_field (t, "u", elem);
1834
1835 elem = builtin_type (gdbarch)->builtin_int128;
1836 append_composite_type_field (t, "s", elem);
1837
1838 tdep->vnq_type = t;
1839 }
1840
1841 return tdep->vnq_type;
1842}
1843
1844/* Return the type for an AdvSISD D register. */
1845
1846static struct type *
1847aarch64_vnd_type (struct gdbarch *gdbarch)
1848{
1849 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1850
1851 if (tdep->vnd_type == NULL)
1852 {
1853 struct type *t;
1854 struct type *elem;
1855
1856 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1857 TYPE_CODE_UNION);
1858
1859 elem = builtin_type (gdbarch)->builtin_double;
1860 append_composite_type_field (t, "f", elem);
1861
1862 elem = builtin_type (gdbarch)->builtin_uint64;
1863 append_composite_type_field (t, "u", elem);
1864
1865 elem = builtin_type (gdbarch)->builtin_int64;
1866 append_composite_type_field (t, "s", elem);
1867
1868 tdep->vnd_type = t;
1869 }
1870
1871 return tdep->vnd_type;
1872}
1873
1874/* Return the type for an AdvSISD S register. */
1875
1876static struct type *
1877aarch64_vns_type (struct gdbarch *gdbarch)
1878{
1879 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1880
1881 if (tdep->vns_type == NULL)
1882 {
1883 struct type *t;
1884 struct type *elem;
1885
1886 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1887 TYPE_CODE_UNION);
1888
1889 elem = builtin_type (gdbarch)->builtin_float;
1890 append_composite_type_field (t, "f", elem);
1891
1892 elem = builtin_type (gdbarch)->builtin_uint32;
1893 append_composite_type_field (t, "u", elem);
1894
1895 elem = builtin_type (gdbarch)->builtin_int32;
1896 append_composite_type_field (t, "s", elem);
1897
1898 tdep->vns_type = t;
1899 }
1900
1901 return tdep->vns_type;
1902}
1903
1904/* Return the type for an AdvSISD H register. */
1905
1906static struct type *
1907aarch64_vnh_type (struct gdbarch *gdbarch)
1908{
1909 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1910
1911 if (tdep->vnh_type == NULL)
1912 {
1913 struct type *t;
1914 struct type *elem;
1915
1916 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1917 TYPE_CODE_UNION);
1918
a6d0f249
AH		 1919 elem = builtin_type (gdbarch)->builtin_half;
1920 append_composite_type_field (t, "f", elem);
1921
07b287a0
MS		 1922 elem = builtin_type (gdbarch)->builtin_uint16;
1923 append_composite_type_field (t, "u", elem);
1924
1925 elem = builtin_type (gdbarch)->builtin_int16;
1926 append_composite_type_field (t, "s", elem);
1927
1928 tdep->vnh_type = t;
1929 }
1930
1931 return tdep->vnh_type;
1932}
1933
1934/* Return the type for an AdvSISD B register. */
1935
1936static struct type *
1937aarch64_vnb_type (struct gdbarch *gdbarch)
1938{
1939 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1940
1941 if (tdep->vnb_type == NULL)
1942 {
1943 struct type *t;
1944 struct type *elem;
1945
1946 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1947 TYPE_CODE_UNION);
1948
1949 elem = builtin_type (gdbarch)->builtin_uint8;
1950 append_composite_type_field (t, "u", elem);
1951
1952 elem = builtin_type (gdbarch)->builtin_int8;
1953 append_composite_type_field (t, "s", elem);
1954
1955 tdep->vnb_type = t;
1956 }
1957
1958 return tdep->vnb_type;
1959}
1960
63bad7b6
AH		 1961/* Return the type for an AdvSISD V register. */
1962
1963static struct type *
1964aarch64_vnv_type (struct gdbarch *gdbarch)
1965{
1966 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1967
1968 if (tdep->vnv_type == NULL)
1969 {
bffa1015
AH		 1970 /* The other AArch64 psuedo registers (Q,D,H,S,B) refer to a single value
1971 slice from the non-pseudo vector registers. However NEON V registers
1972 are always vector registers, and need constructing as such. */
1973 const struct builtin_type *bt = builtin_type (gdbarch);
1974
63bad7b6
AH		 1975 struct type *t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnv",
1976 TYPE_CODE_UNION);
1977
bffa1015
AH		 1978 struct type *sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1979 TYPE_CODE_UNION);
1980 append_composite_type_field (sub, "f",
1981 init_vector_type (bt->builtin_double, 2));
1982 append_composite_type_field (sub, "u",
1983 init_vector_type (bt->builtin_uint64, 2));
1984 append_composite_type_field (sub, "s",
1985 init_vector_type (bt->builtin_int64, 2));
1986 append_composite_type_field (t, "d", sub);
1987
1988 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1989 TYPE_CODE_UNION);
1990 append_composite_type_field (sub, "f",
1991 init_vector_type (bt->builtin_float, 4));
1992 append_composite_type_field (sub, "u",
1993 init_vector_type (bt->builtin_uint32, 4));
1994 append_composite_type_field (sub, "s",
1995 init_vector_type (bt->builtin_int32, 4));
1996 append_composite_type_field (t, "s", sub);
1997
1998 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1999 TYPE_CODE_UNION);
a6d0f249
AH		 2000 append_composite_type_field (sub, "f",
2001 init_vector_type (bt->builtin_half, 8));
bffa1015
AH		 2002 append_composite_type_field (sub, "u",
2003 init_vector_type (bt->builtin_uint16, 8));
2004 append_composite_type_field (sub, "s",
2005 init_vector_type (bt->builtin_int16, 8));
2006 append_composite_type_field (t, "h", sub);
2007
2008 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
2009 TYPE_CODE_UNION);
2010 append_composite_type_field (sub, "u",
2011 init_vector_type (bt->builtin_uint8, 16));
2012 append_composite_type_field (sub, "s",
2013 init_vector_type (bt->builtin_int8, 16));
2014 append_composite_type_field (t, "b", sub);
2015
2016 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
2017 TYPE_CODE_UNION);
2018 append_composite_type_field (sub, "u",
2019 init_vector_type (bt->builtin_uint128, 1));
2020 append_composite_type_field (sub, "s",
2021 init_vector_type (bt->builtin_int128, 1));
2022 append_composite_type_field (t, "q", sub);
63bad7b6
AH		 2023
2024 tdep->vnv_type = t;
2025 }
2026
2027 return tdep->vnv_type;
2028}
2029
07b287a0
MS		 2030/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
2031
2032static int
2033aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
2034{
34dcc7cf
AH		 2035 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2036
07b287a0
MS		 2037 if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30)
2038 return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0;
2039
2040 if (reg == AARCH64_DWARF_SP)
2041 return AARCH64_SP_REGNUM;
2042
2043 if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
2044 return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
2045
65d4cada
AH		 2046 if (reg == AARCH64_DWARF_SVE_VG)
2047 return AARCH64_SVE_VG_REGNUM;
2048
2049 if (reg == AARCH64_DWARF_SVE_FFR)
2050 return AARCH64_SVE_FFR_REGNUM;
2051
2052 if (reg >= AARCH64_DWARF_SVE_P0 && reg <= AARCH64_DWARF_SVE_P0 + 15)
2053 return AARCH64_SVE_P0_REGNUM + reg - AARCH64_DWARF_SVE_P0;
2054
2055 if (reg >= AARCH64_DWARF_SVE_Z0 && reg <= AARCH64_DWARF_SVE_Z0 + 15)
2056 return AARCH64_SVE_Z0_REGNUM + reg - AARCH64_DWARF_SVE_Z0;
2057
34dcc7cf
AH		 2058 if (tdep->has_pauth ())
2059 {
2060 if (reg >= AARCH64_DWARF_PAUTH_DMASK && reg <= AARCH64_DWARF_PAUTH_CMASK)
2061 return tdep->pauth_reg_base + reg - AARCH64_DWARF_PAUTH_DMASK;
2062
2063 if (reg == AARCH64_DWARF_PAUTH_RA_STATE)
2064 return tdep->pauth_ra_state_regnum;
2065 }
2066
07b287a0
MS		 2067 return -1;
2068}
07b287a0
MS		 2069
2070/* Implement the "print_insn" gdbarch method. */
2071
2072static int
2073aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
2074{
2075 info->symbols = NULL;
6394c606 2076 return default_print_insn (memaddr, info);
07b287a0
MS		 2077}
2078
2079/* AArch64 BRK software debug mode instruction.
2080 Note that AArch64 code is always little-endian.
2081 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
04180708 2082constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
07b287a0 2083
04180708 2084typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint;
07b287a0
MS		 2085
2086/* Extract from an array REGS containing the (raw) register state a
2087 function return value of type TYPE, and copy that, in virtual
2088 format, into VALBUF. */
2089
2090static void
2091aarch64_extract_return_value (struct type *type, struct regcache *regs,
2092 gdb_byte *valbuf)
2093{
ac7936df 2094 struct gdbarch *gdbarch = regs->arch ();
07b287a0 2095 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4f4aedeb
AH		 2096 int elements;
2097 struct type *fundamental_type;
07b287a0 2098
4f4aedeb
AH		 2099 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2100 &fundamental_type))
07b287a0 2101 {
4f4aedeb
AH		 2102 int len = TYPE_LENGTH (fundamental_type);
2103
2104 for (int i = 0; i < elements; i++)
2105 {
2106 int regno = AARCH64_V0_REGNUM + i;
3ff2c72e
AH		 2107 /* Enough space for a full vector register. */
2108 gdb_byte buf[register_size (gdbarch, regno)];
2109 gdb_assert (len <= sizeof (buf));
4f4aedeb
AH		 2110
2111 if (aarch64_debug)
2112 {
2113 debug_printf ("read HFA or HVA return value element %d from %s\n",
2114 i + 1,
2115 gdbarch_register_name (gdbarch, regno));
2116 }
2117 regs->cooked_read (regno, buf);
07b287a0 2118
4f4aedeb
AH		 2119 memcpy (valbuf, buf, len);
2120 valbuf += len;
2121 }
07b287a0
MS		 2122 }
2123 else if (TYPE_CODE (type) == TYPE_CODE_INT
2124 || TYPE_CODE (type) == TYPE_CODE_CHAR
2125 || TYPE_CODE (type) == TYPE_CODE_BOOL
2126 || TYPE_CODE (type) == TYPE_CODE_PTR
aa006118 2127 || TYPE_IS_REFERENCE (type)
07b287a0
MS		 2128 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2129 {
6471e7d2 2130 /* If the type is a plain integer, then the access is
07b287a0
MS		 2131 straight-forward. Otherwise we have to play around a bit
2132 more. */
2133 int len = TYPE_LENGTH (type);
2134 int regno = AARCH64_X0_REGNUM;
2135 ULONGEST tmp;
2136
2137 while (len > 0)
2138 {
2139 /* By using store_unsigned_integer we avoid having to do
2140 anything special for small big-endian values. */
2141 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2142 store_unsigned_integer (valbuf,
2143 (len > X_REGISTER_SIZE
2144 ? X_REGISTER_SIZE : len), byte_order, tmp);
2145 len -= X_REGISTER_SIZE;
2146 valbuf += X_REGISTER_SIZE;
2147 }
2148 }
07b287a0
MS		 2149 else
2150 {
2151 /* For a structure or union the behaviour is as if the value had
2152 been stored to word-aligned memory and then loaded into
2153 registers with 64-bit load instruction(s). */
2154 int len = TYPE_LENGTH (type);
2155 int regno = AARCH64_X0_REGNUM;
2156 bfd_byte buf[X_REGISTER_SIZE];
2157
2158 while (len > 0)
2159 {
dca08e1f 2160 regs->cooked_read (regno++, buf);
07b287a0
MS		 2161 memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
2162 len -= X_REGISTER_SIZE;
2163 valbuf += X_REGISTER_SIZE;
2164 }
2165 }
2166}
2167
2168
2169/* Will a function return an aggregate type in memory or in a
2170 register? Return 0 if an aggregate type can be returned in a
2171 register, 1 if it must be returned in memory. */
2172
2173static int
2174aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2175{
f168693b 2176 type = check_typedef (type);
4f4aedeb
AH		 2177 int elements;
2178 struct type *fundamental_type;
07b287a0 2179
4f4aedeb
AH		 2180 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2181 &fundamental_type))
07b287a0 2182 {
cd635f74
YQ		 2183 /* v0-v7 are used to return values and one register is allocated
2184 for one member. However, HFA or HVA has at most four members. */
07b287a0
MS		 2185 return 0;
2186 }
2187
2188 if (TYPE_LENGTH (type) > 16)
2189 {
2190 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2191 invisible reference. */
2192
2193 return 1;
2194 }
2195
2196 return 0;
2197}
2198
2199/* Write into appropriate registers a function return value of type
2200 TYPE, given in virtual format. */
2201
2202static void
2203aarch64_store_return_value (struct type *type, struct regcache *regs,
2204 const gdb_byte *valbuf)
2205{
ac7936df 2206 struct gdbarch *gdbarch = regs->arch ();
07b287a0 2207 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4f4aedeb
AH		 2208 int elements;
2209 struct type *fundamental_type;
07b287a0 2210
4f4aedeb
AH		 2211 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2212 &fundamental_type))
07b287a0 2213 {
4f4aedeb
AH		 2214 int len = TYPE_LENGTH (fundamental_type);
2215
2216 for (int i = 0; i < elements; i++)
2217 {
2218 int regno = AARCH64_V0_REGNUM + i;
3ff2c72e
AH		 2219 /* Enough space for a full vector register. */
2220 gdb_byte tmpbuf[register_size (gdbarch, regno)];
2221 gdb_assert (len <= sizeof (tmpbuf));
4f4aedeb
AH		 2222
2223 if (aarch64_debug)
2224 {
2225 debug_printf ("write HFA or HVA return value element %d to %s\n",
2226 i + 1,
2227 gdbarch_register_name (gdbarch, regno));
2228 }
07b287a0 2229
4f4aedeb
AH		 2230 memcpy (tmpbuf, valbuf,
2231 len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
2232 regs->cooked_write (regno, tmpbuf);
2233 valbuf += len;
2234 }
07b287a0
MS		 2235 }
2236 else if (TYPE_CODE (type) == TYPE_CODE_INT
2237 || TYPE_CODE (type) == TYPE_CODE_CHAR
2238 || TYPE_CODE (type) == TYPE_CODE_BOOL
2239 || TYPE_CODE (type) == TYPE_CODE_PTR
aa006118 2240 || TYPE_IS_REFERENCE (type)
07b287a0
MS		 2241 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2242 {
2243 if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
2244 {
2245 /* Values of one word or less are zero/sign-extended and
2246 returned in r0. */
2247 bfd_byte tmpbuf[X_REGISTER_SIZE];
2248 LONGEST val = unpack_long (type, valbuf);
2249
2250 store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
b66f5587 2251 regs->cooked_write (AARCH64_X0_REGNUM, tmpbuf);
07b287a0
MS		 2252 }
2253 else
2254 {
2255 /* Integral values greater than one word are stored in
2256 consecutive registers starting with r0. This will always
2257 be a multiple of the regiser size. */
2258 int len = TYPE_LENGTH (type);
2259 int regno = AARCH64_X0_REGNUM;
2260
2261 while (len > 0)
2262 {
b66f5587 2263 regs->cooked_write (regno++, valbuf);
07b287a0
MS		 2264 len -= X_REGISTER_SIZE;
2265 valbuf += X_REGISTER_SIZE;
2266 }
2267 }
2268 }
07b287a0
MS		 2269 else
2270 {
2271 /* For a structure or union the behaviour is as if the value had
2272 been stored to word-aligned memory and then loaded into
2273 registers with 64-bit load instruction(s). */
2274 int len = TYPE_LENGTH (type);
2275 int regno = AARCH64_X0_REGNUM;
2276 bfd_byte tmpbuf[X_REGISTER_SIZE];
2277
2278 while (len > 0)
2279 {
2280 memcpy (tmpbuf, valbuf,
2281 len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
b66f5587 2282 regs->cooked_write (regno++, tmpbuf);
07b287a0
MS		 2283 len -= X_REGISTER_SIZE;
2284 valbuf += X_REGISTER_SIZE;
2285 }
2286 }
2287}
2288
2289/* Implement the "return_value" gdbarch method. */
2290
2291static enum return_value_convention
2292aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
2293 struct type *valtype, struct regcache *regcache,
2294 gdb_byte *readbuf, const gdb_byte *writebuf)
2295{
07b287a0
MS		 2296
2297 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2298 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2299 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2300 {
2301 if (aarch64_return_in_memory (gdbarch, valtype))
2302 {
2303 if (aarch64_debug)
b277c936 2304 debug_printf ("return value in memory\n");
07b287a0
MS		 2305 return RETURN_VALUE_STRUCT_CONVENTION;
2306 }
2307 }
2308
2309 if (writebuf)
2310 aarch64_store_return_value (valtype, regcache, writebuf);
2311
2312 if (readbuf)
2313 aarch64_extract_return_value (valtype, regcache, readbuf);
2314
2315 if (aarch64_debug)
b277c936 2316 debug_printf ("return value in registers\n");
07b287a0
MS		 2317
2318 return RETURN_VALUE_REGISTER_CONVENTION;
2319}
2320
2321/* Implement the "get_longjmp_target" gdbarch method. */
2322
2323static int
2324aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2325{
2326 CORE_ADDR jb_addr;
2327 gdb_byte buf[X_REGISTER_SIZE];
2328 struct gdbarch *gdbarch = get_frame_arch (frame);
2329 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2330 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2331
2332 jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM);
2333
2334 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2335 X_REGISTER_SIZE))
2336 return 0;
2337
2338 *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order);
2339 return 1;
2340}
ea873d8e
PL		 2341
2342/* Implement the "gen_return_address" gdbarch method. */
2343
2344static void
2345aarch64_gen_return_address (struct gdbarch *gdbarch,
2346 struct agent_expr *ax, struct axs_value *value,
2347 CORE_ADDR scope)
2348{
2349 value->type = register_type (gdbarch, AARCH64_LR_REGNUM);
2350 value->kind = axs_lvalue_register;
2351 value->u.reg = AARCH64_LR_REGNUM;
2352}
07b287a0
MS		 2353\f
2354
2355/* Return the pseudo register name corresponding to register regnum. */
2356
2357static const char *
2358aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
2359{
63bad7b6
AH		 2360 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2361
07b287a0
MS		 2362 static const char *const q_name[] =
2363 {
2364 "q0", "q1", "q2", "q3",
2365 "q4", "q5", "q6", "q7",
2366 "q8", "q9", "q10", "q11",
2367 "q12", "q13", "q14", "q15",
2368 "q16", "q17", "q18", "q19",
2369 "q20", "q21", "q22", "q23",
2370 "q24", "q25", "q26", "q27",
2371 "q28", "q29", "q30", "q31",
2372 };
2373
2374 static const char *const d_name[] =
2375 {
2376 "d0", "d1", "d2", "d3",
2377 "d4", "d5", "d6", "d7",
2378 "d8", "d9", "d10", "d11",
2379 "d12", "d13", "d14", "d15",
2380 "d16", "d17", "d18", "d19",
2381 "d20", "d21", "d22", "d23",
2382 "d24", "d25", "d26", "d27",
2383 "d28", "d29", "d30", "d31",
2384 };
2385
2386 static const char *const s_name[] =
2387 {
2388 "s0", "s1", "s2", "s3",
2389 "s4", "s5", "s6", "s7",
2390 "s8", "s9", "s10", "s11",
2391 "s12", "s13", "s14", "s15",
2392 "s16", "s17", "s18", "s19",
2393 "s20", "s21", "s22", "s23",
2394 "s24", "s25", "s26", "s27",
2395 "s28", "s29", "s30", "s31",
2396 };
2397
2398 static const char *const h_name[] =
2399 {
2400 "h0", "h1", "h2", "h3",
2401 "h4", "h5", "h6", "h7",
2402 "h8", "h9", "h10", "h11",
2403 "h12", "h13", "h14", "h15",
2404 "h16", "h17", "h18", "h19",
2405 "h20", "h21", "h22", "h23",
2406 "h24", "h25", "h26", "h27",
2407 "h28", "h29", "h30", "h31",
2408 };
2409
2410 static const char *const b_name[] =
2411 {
2412 "b0", "b1", "b2", "b3",
2413 "b4", "b5", "b6", "b7",
2414 "b8", "b9", "b10", "b11",
2415 "b12", "b13", "b14", "b15",
2416 "b16", "b17", "b18", "b19",
2417 "b20", "b21", "b22", "b23",
2418 "b24", "b25", "b26", "b27",
2419 "b28", "b29", "b30", "b31",
2420 };
2421
34dcc7cf 2422 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2423
34dcc7cf
AH		 2424 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
2425 return q_name[p_regnum - AARCH64_Q0_REGNUM];
07b287a0 2426
34dcc7cf
AH		 2427 if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
2428 return d_name[p_regnum - AARCH64_D0_REGNUM];
07b287a0 2429
34dcc7cf
AH		 2430 if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
2431 return s_name[p_regnum - AARCH64_S0_REGNUM];
07b287a0 2432
34dcc7cf
AH		 2433 if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
2434 return h_name[p_regnum - AARCH64_H0_REGNUM];
07b287a0 2435
34dcc7cf
AH		 2436 if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
2437 return b_name[p_regnum - AARCH64_B0_REGNUM];
07b287a0 2438
63bad7b6
AH		 2439 if (tdep->has_sve ())
2440 {
2441 static const char *const sve_v_name[] =
2442 {
2443 "v0", "v1", "v2", "v3",
2444 "v4", "v5", "v6", "v7",
2445 "v8", "v9", "v10", "v11",
2446 "v12", "v13", "v14", "v15",
2447 "v16", "v17", "v18", "v19",
2448 "v20", "v21", "v22", "v23",
2449 "v24", "v25", "v26", "v27",
2450 "v28", "v29", "v30", "v31",
2451 };
2452
34dcc7cf
AH		 2453 if (p_regnum >= AARCH64_SVE_V0_REGNUM
2454 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2455 return sve_v_name[p_regnum - AARCH64_SVE_V0_REGNUM];
63bad7b6
AH		 2456 }
2457
34dcc7cf
AH		 2458 /* RA_STATE is used for unwinding only. Do not assign it a name - this
2459 prevents it from being read by methods such as
2460 mi_cmd_trace_frame_collected. */
2461 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2462 return "";
2463
07b287a0
MS		 2464 internal_error (__FILE__, __LINE__,
2465 _("aarch64_pseudo_register_name: bad register number %d"),
34dcc7cf 2466 p_regnum);
07b287a0
MS		 2467}
2468
2469/* Implement the "pseudo_register_type" tdesc_arch_data method. */
2470
2471static struct type *
2472aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2473{
63bad7b6
AH		 2474 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2475
34dcc7cf 2476 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2477
34dcc7cf 2478 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
07b287a0
MS		 2479 return aarch64_vnq_type (gdbarch);
2480
34dcc7cf 2481 if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
07b287a0
MS		 2482 return aarch64_vnd_type (gdbarch);
2483
34dcc7cf 2484 if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
07b287a0
MS		 2485 return aarch64_vns_type (gdbarch);
2486
34dcc7cf 2487 if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
07b287a0
MS		 2488 return aarch64_vnh_type (gdbarch);
2489
34dcc7cf 2490 if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
07b287a0
MS		 2491 return aarch64_vnb_type (gdbarch);
2492
34dcc7cf
AH		 2493 if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM
2494 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
63bad7b6
AH		 2495 return aarch64_vnv_type (gdbarch);
2496
34dcc7cf
AH		 2497 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2498 return builtin_type (gdbarch)->builtin_uint64;
2499
07b287a0
MS		 2500 internal_error (__FILE__, __LINE__,
2501 _("aarch64_pseudo_register_type: bad register number %d"),
34dcc7cf 2502 p_regnum);
07b287a0
MS		 2503}
2504
2505/* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2506
2507static int
2508aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2509 struct reggroup *group)
2510{
63bad7b6
AH		 2511 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2512
34dcc7cf 2513 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2514
34dcc7cf 2515 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
07b287a0 2516 return group == all_reggroup || group == vector_reggroup;
34dcc7cf 2517 else if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
07b287a0
MS		 2518 return (group == all_reggroup || group == vector_reggroup
2519 || group == float_reggroup);
34dcc7cf 2520 else if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
07b287a0
MS		 2521 return (group == all_reggroup || group == vector_reggroup
2522 || group == float_reggroup);
34dcc7cf 2523 else if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
07b287a0 2524 return group == all_reggroup || group == vector_reggroup;
34dcc7cf 2525 else if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
07b287a0 2526 return group == all_reggroup || group == vector_reggroup;
34dcc7cf
AH		 2527 else if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM
2528 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
63bad7b6 2529 return group == all_reggroup || group == vector_reggroup;
34dcc7cf
AH		 2530 /* RA_STATE is used for unwinding only. Do not assign it to any groups. */
2531 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2532 return 0;
07b287a0
MS		 2533
2534 return group == all_reggroup;
2535}
2536
3c5cd5c3
AH		 2537/* Helper for aarch64_pseudo_read_value. */
2538
2539static struct value *
63bad7b6
AH		 2540aarch64_pseudo_read_value_1 (struct gdbarch *gdbarch,
2541 readable_regcache *regcache, int regnum_offset,
3c5cd5c3
AH		 2542 int regsize, struct value *result_value)
2543{
3c5cd5c3
AH		 2544 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
2545
63bad7b6
AH		 2546 /* Enough space for a full vector register. */
2547 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2548 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2549
3c5cd5c3
AH		 2550 if (regcache->raw_read (v_regnum, reg_buf) != REG_VALID)
2551 mark_value_bytes_unavailable (result_value, 0,
2552 TYPE_LENGTH (value_type (result_value)));
2553 else
2554 memcpy (value_contents_raw (result_value), reg_buf, regsize);
63bad7b6 2555
3c5cd5c3
AH		 2556 return result_value;
2557 }
2558
07b287a0
MS		 2559/* Implement the "pseudo_register_read_value" gdbarch method. */
2560
2561static struct value *
3c5cd5c3 2562aarch64_pseudo_read_value (struct gdbarch *gdbarch, readable_regcache *regcache,
07b287a0
MS		 2563 int regnum)
2564{
63bad7b6 2565 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3c5cd5c3 2566 struct value *result_value = allocate_value (register_type (gdbarch, regnum));
07b287a0 2567
07b287a0
MS		 2568 VALUE_LVAL (result_value) = lval_register;
2569 VALUE_REGNUM (result_value) = regnum;
07b287a0
MS		 2570
2571 regnum -= gdbarch_num_regs (gdbarch);
2572
2573 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
63bad7b6
AH		 2574 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2575 regnum - AARCH64_Q0_REGNUM,
3c5cd5c3 2576 Q_REGISTER_SIZE, result_value);
07b287a0
MS		 2577
2578 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
63bad7b6
AH		 2579 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2580 regnum - AARCH64_D0_REGNUM,
3c5cd5c3 2581 D_REGISTER_SIZE, result_value);
07b287a0
MS		 2582
2583 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
63bad7b6
AH		 2584 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2585 regnum - AARCH64_S0_REGNUM,
3c5cd5c3 2586 S_REGISTER_SIZE, result_value);
07b287a0
MS		 2587
2588 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
63bad7b6
AH		 2589 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2590 regnum - AARCH64_H0_REGNUM,
3c5cd5c3 2591 H_REGISTER_SIZE, result_value);
07b287a0
MS		 2592
2593 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
63bad7b6
AH		 2594 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2595 regnum - AARCH64_B0_REGNUM,
3c5cd5c3 2596 B_REGISTER_SIZE, result_value);
07b287a0 2597
63bad7b6
AH		 2598 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2599 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2600 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2601 regnum - AARCH64_SVE_V0_REGNUM,
2602 V_REGISTER_SIZE, result_value);
2603
07b287a0
MS		 2604 gdb_assert_not_reached ("regnum out of bound");
2605}
2606
3c5cd5c3 2607/* Helper for aarch64_pseudo_write. */
07b287a0
MS		 2608
2609static void
63bad7b6
AH		 2610aarch64_pseudo_write_1 (struct gdbarch *gdbarch, struct regcache *regcache,
2611 int regnum_offset, int regsize, const gdb_byte *buf)
07b287a0 2612{
3c5cd5c3 2613 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
07b287a0 2614
63bad7b6
AH		 2615 /* Enough space for a full vector register. */
2616 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2617 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2618
07b287a0
MS		 2619 /* Ensure the register buffer is zero, we want gdb writes of the
2620 various 'scalar' pseudo registers to behavior like architectural
2621 writes, register width bytes are written the remainder are set to
2622 zero. */
63bad7b6 2623 memset (reg_buf, 0, register_size (gdbarch, AARCH64_V0_REGNUM));
07b287a0 2624
3c5cd5c3
AH		 2625 memcpy (reg_buf, buf, regsize);
2626 regcache->raw_write (v_regnum, reg_buf);
2627}
2628
2629/* Implement the "pseudo_register_write" gdbarch method. */
2630
2631static void
2632aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
2633 int regnum, const gdb_byte *buf)
2634{
63bad7b6 2635 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
07b287a0
MS		 2636 regnum -= gdbarch_num_regs (gdbarch);
2637
2638 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
63bad7b6
AH		 2639 return aarch64_pseudo_write_1 (gdbarch, regcache,
2640 regnum - AARCH64_Q0_REGNUM, Q_REGISTER_SIZE,
2641 buf);
07b287a0
MS		 2642
2643 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
63bad7b6
AH		 2644 return aarch64_pseudo_write_1 (gdbarch, regcache,
2645 regnum - AARCH64_D0_REGNUM, D_REGISTER_SIZE,
2646 buf);
07b287a0
MS		 2647
2648 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
63bad7b6
AH		 2649 return aarch64_pseudo_write_1 (gdbarch, regcache,
2650 regnum - AARCH64_S0_REGNUM, S_REGISTER_SIZE,
2651 buf);
07b287a0
MS		 2652
2653 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
63bad7b6
AH		 2654 return aarch64_pseudo_write_1 (gdbarch, regcache,
2655 regnum - AARCH64_H0_REGNUM, H_REGISTER_SIZE,
2656 buf);
07b287a0
MS		 2657
2658 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
63bad7b6
AH		 2659 return aarch64_pseudo_write_1 (gdbarch, regcache,
2660 regnum - AARCH64_B0_REGNUM, B_REGISTER_SIZE,
2661 buf);
2662
2663 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2664 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2665 return aarch64_pseudo_write_1 (gdbarch, regcache,
2666 regnum - AARCH64_SVE_V0_REGNUM,
2667 V_REGISTER_SIZE, buf);
07b287a0
MS		 2668
2669 gdb_assert_not_reached ("regnum out of bound");
2670}
2671
07b287a0
MS		 2672/* Callback function for user_reg_add. */
2673
2674static struct value *
2675value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
2676{
9a3c8263 2677 const int *reg_p = (const int *) baton;
07b287a0
MS		 2678
2679 return value_of_register (*reg_p, frame);
2680}
2681\f
2682
9404b58f
KM		 2683/* Implement the "software_single_step" gdbarch method, needed to
2684 single step through atomic sequences on AArch64. */
2685
a0ff9e1a 2686static std::vector<CORE_ADDR>
f5ea389a 2687aarch64_software_single_step (struct regcache *regcache)
9404b58f 2688{
ac7936df 2689 struct gdbarch *gdbarch = regcache->arch ();
9404b58f
KM		 2690 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2691 const int insn_size = 4;
2692 const int atomic_sequence_length = 16; /* Instruction sequence length. */
0187a92f 2693 CORE_ADDR pc = regcache_read_pc (regcache);
70ab8ccd 2694 CORE_ADDR breaks[2] = { CORE_ADDR_MAX, CORE_ADDR_MAX };
9404b58f
KM		 2695 CORE_ADDR loc = pc;
2696 CORE_ADDR closing_insn = 0;
2697 uint32_t insn = read_memory_unsigned_integer (loc, insn_size,
2698 byte_order_for_code);
2699 int index;
2700 int insn_count;
2701 int bc_insn_count = 0; /* Conditional branch instruction count. */
2702 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
f77ee802
YQ		 2703 aarch64_inst inst;
2704
561a72d4 2705 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2706 return {};
9404b58f
KM		 2707
2708 /* Look for a Load Exclusive instruction which begins the sequence. */
f77ee802 2709 if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
a0ff9e1a 2710 return {};
9404b58f
KM		 2711
2712 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2713 {
9404b58f
KM		 2714 loc += insn_size;
2715 insn = read_memory_unsigned_integer (loc, insn_size,
2716 byte_order_for_code);
2717
561a72d4 2718 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2719 return {};
9404b58f 2720 /* Check if the instruction is a conditional branch. */
f77ee802 2721 if (inst.opcode->iclass == condbranch)
9404b58f 2722 {
f77ee802
YQ		 2723 gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
2724
9404b58f 2725 if (bc_insn_count >= 1)
a0ff9e1a 2726 return {};
9404b58f
KM		 2727
2728 /* It is, so we'll try to set a breakpoint at the destination. */
f77ee802 2729 breaks[1] = loc + inst.operands[0].imm.value;
9404b58f
KM		 2730
2731 bc_insn_count++;
2732 last_breakpoint++;
2733 }
2734
2735 /* Look for the Store Exclusive which closes the atomic sequence. */
f77ee802 2736 if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
9404b58f
KM		 2737 {
2738 closing_insn = loc;
2739 break;
2740 }
2741 }
2742
2743 /* We didn't find a closing Store Exclusive instruction, fall back. */
2744 if (!closing_insn)
a0ff9e1a 2745 return {};
9404b58f
KM		 2746
2747 /* Insert breakpoint after the end of the atomic sequence. */
2748 breaks[0] = loc + insn_size;
2749
2750 /* Check for duplicated breakpoints, and also check that the second
2751 breakpoint is not within the atomic sequence. */
2752 if (last_breakpoint
2753 && (breaks[1] == breaks[0]
2754 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
2755 last_breakpoint = 0;
2756
a0ff9e1a
SM		 2757 std::vector<CORE_ADDR> next_pcs;
2758
9404b58f
KM		 2759 /* Insert the breakpoint at the end of the sequence, and one at the
2760 destination of the conditional branch, if it exists. */
2761 for (index = 0; index <= last_breakpoint; index++)
a0ff9e1a 2762 next_pcs.push_back (breaks[index]);
9404b58f 2763
93f9a11f 2764 return next_pcs;
9404b58f
KM		 2765}
2766
cfba9872 2767struct aarch64_displaced_step_closure : public displaced_step_closure
b6542f81
YQ		 2768{
2769 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2770 is being displaced stepping. */
f0c702d4 2771 bool cond = false;
b6542f81 2772
0c271889
LM		 2773 /* PC adjustment offset after displaced stepping. If 0, then we don't
2774 write the PC back, assuming the PC is already the right address. */
cfba9872 2775 int32_t pc_adjust = 0;
b6542f81
YQ		 2776};
2777
2778/* Data when visiting instructions for displaced stepping. */
2779
2780struct aarch64_displaced_step_data
2781{
2782 struct aarch64_insn_data base;
2783
2784 /* The address where the instruction will be executed at. */
2785 CORE_ADDR new_addr;
2786 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
e935475c 2787 uint32_t insn_buf[AARCH64_DISPLACED_MODIFIED_INSNS];
b6542f81
YQ		 2788 /* Number of instructions in INSN_BUF. */
2789 unsigned insn_count;
2790 /* Registers when doing displaced stepping. */
2791 struct regcache *regs;
2792
cfba9872 2793 aarch64_displaced_step_closure *dsc;
b6542f81
YQ		 2794};
2795
2796/* Implementation of aarch64_insn_visitor method "b". */
2797
2798static void
2799aarch64_displaced_step_b (const int is_bl, const int32_t offset,
2800 struct aarch64_insn_data *data)
2801{
2802 struct aarch64_displaced_step_data *dsd
2803 = (struct aarch64_displaced_step_data *) data;
2ac09a5b 2804 int64_t new_offset = data->insn_addr - dsd->new_addr + offset;
b6542f81
YQ		 2805
2806 if (can_encode_int32 (new_offset, 28))
2807 {
2808 /* Emit B rather than BL, because executing BL on a new address
2809 will get the wrong address into LR. In order to avoid this,
2810 we emit B, and update LR if the instruction is BL. */
2811 emit_b (dsd->insn_buf, 0, new_offset);
2812 dsd->insn_count++;
2813 }
2814 else
2815 {
2816 /* Write NOP. */
2817 emit_nop (dsd->insn_buf);
2818 dsd->insn_count++;
2819 dsd->dsc->pc_adjust = offset;
2820 }
2821
2822 if (is_bl)
2823 {
2824 /* Update LR. */
2825 regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
2826 data->insn_addr + 4);
2827 }
2828}
2829
2830/* Implementation of aarch64_insn_visitor method "b_cond". */
2831
2832static void
2833aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
2834 struct aarch64_insn_data *data)
2835{
2836 struct aarch64_displaced_step_data *dsd
2837 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2838
2839 /* GDB has to fix up PC after displaced step this instruction
2840 differently according to the condition is true or false. Instead
2841 of checking COND against conditional flags, we can use
2842 the following instructions, and GDB can tell how to fix up PC
2843 according to the PC value.
2844
2845 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2846 INSN1 ;
2847 TAKEN:
2848 INSN2
2849 */
2850
2851 emit_bcond (dsd->insn_buf, cond, 8);
f0c702d4 2852 dsd->dsc->cond = true;
b6542f81
YQ		 2853 dsd->dsc->pc_adjust = offset;
2854 dsd->insn_count = 1;
2855}
2856
2857/* Dynamically allocate a new register. If we know the register
2858 statically, we should make it a global as above instead of using this
2859 helper function. */
2860
2861static struct aarch64_register
2862aarch64_register (unsigned num, int is64)
2863{
2864 return (struct aarch64_register) { num, is64 };
2865}
2866
2867/* Implementation of aarch64_insn_visitor method "cb". */
2868
2869static void
2870aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
2871 const unsigned rn, int is64,
2872 struct aarch64_insn_data *data)
2873{
2874 struct aarch64_displaced_step_data *dsd
2875 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2876
2877 /* The offset is out of range for a compare and branch
2878 instruction. We can use the following instructions instead:
2879
2880 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2881 INSN1 ;
2882 TAKEN:
2883 INSN2
2884 */
2885 emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
2886 dsd->insn_count = 1;
f0c702d4 2887 dsd->dsc->cond = true;
b6542f81
YQ		 2888 dsd->dsc->pc_adjust = offset;
2889}
2890
2891/* Implementation of aarch64_insn_visitor method "tb". */
2892
2893static void
2894aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
2895 const unsigned rt, unsigned bit,
2896 struct aarch64_insn_data *data)
2897{
2898 struct aarch64_displaced_step_data *dsd
2899 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2900
2901 /* The offset is out of range for a test bit and branch
2902 instruction We can use the following instructions instead:
2903
2904 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2905 INSN1 ;
2906 TAKEN:
2907 INSN2
2908
2909 */
2910 emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
2911 dsd->insn_count = 1;
f0c702d4 2912 dsd->dsc->cond = true;
b6542f81
YQ		 2913 dsd->dsc->pc_adjust = offset;
2914}
2915
2916/* Implementation of aarch64_insn_visitor method "adr". */
2917
2918static void
2919aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
2920 const int is_adrp, struct aarch64_insn_data *data)
2921{
2922 struct aarch64_displaced_step_data *dsd
2923 = (struct aarch64_displaced_step_data *) data;
2924 /* We know exactly the address the ADR{P,} instruction will compute.
2925 We can just write it to the destination register. */
2926 CORE_ADDR address = data->insn_addr + offset;
2927
2928 if (is_adrp)
2929 {
2930 /* Clear the lower 12 bits of the offset to get the 4K page. */
2931 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2932 address & ~0xfff);
2933 }
2934 else
2935 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2936 address);
2937
2938 dsd->dsc->pc_adjust = 4;
2939 emit_nop (dsd->insn_buf);
2940 dsd->insn_count = 1;
2941}
2942
2943/* Implementation of aarch64_insn_visitor method "ldr_literal". */
2944
2945static void
2946aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
2947 const unsigned rt, const int is64,
2948 struct aarch64_insn_data *data)
2949{
2950 struct aarch64_displaced_step_data *dsd
2951 = (struct aarch64_displaced_step_data *) data;
2952 CORE_ADDR address = data->insn_addr + offset;
2953 struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 };
2954
2955 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt,
2956 address);
2957
2958 if (is_sw)
2959 dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1),
2960 aarch64_register (rt, 1), zero);
2961 else
2962 dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64),
2963 aarch64_register (rt, 1), zero);
2964
2965 dsd->dsc->pc_adjust = 4;
2966}
2967
2968/* Implementation of aarch64_insn_visitor method "others". */
2969
2970static void
2971aarch64_displaced_step_others (const uint32_t insn,
2972 struct aarch64_insn_data *data)
2973{
2974 struct aarch64_displaced_step_data *dsd
2975 = (struct aarch64_displaced_step_data *) data;
2976
e1c587c3 2977 aarch64_emit_insn (dsd->insn_buf, insn);
b6542f81
YQ		 2978 dsd->insn_count = 1;
2979
2980 if ((insn & 0xfffffc1f) == 0xd65f0000)
2981 {
2982 /* RET */
2983 dsd->dsc->pc_adjust = 0;
2984 }
2985 else
2986 dsd->dsc->pc_adjust = 4;
2987}
2988
2989static const struct aarch64_insn_visitor visitor =
2990{
2991 aarch64_displaced_step_b,
2992 aarch64_displaced_step_b_cond,
2993 aarch64_displaced_step_cb,
2994 aarch64_displaced_step_tb,
2995 aarch64_displaced_step_adr,
2996 aarch64_displaced_step_ldr_literal,
2997 aarch64_displaced_step_others,
2998};
2999
3000/* Implement the "displaced_step_copy_insn" gdbarch method. */
3001
fdb61c6c 3002displaced_step_closure_up
b6542f81
YQ		 3003aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
3004 CORE_ADDR from, CORE_ADDR to,
3005 struct regcache *regs)
3006{
b6542f81
YQ		 3007 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3008 uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
3009 struct aarch64_displaced_step_data dsd;
c86a40c6
YQ		 3010 aarch64_inst inst;
3011
561a72d4 3012 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
c86a40c6 3013 return NULL;
b6542f81
YQ		 3014
3015 /* Look for a Load Exclusive instruction which begins the sequence. */
c86a40c6 3016 if (inst.opcode->iclass == ldstexcl && bit (insn, 22))
b6542f81
YQ		 3017 {
3018 /* We can't displaced step atomic sequences. */
3019 return NULL;
3020 }
3021
cfba9872
SM		 3022 std::unique_ptr<aarch64_displaced_step_closure> dsc
3023 (new aarch64_displaced_step_closure);
b6542f81
YQ		 3024 dsd.base.insn_addr = from;
3025 dsd.new_addr = to;
3026 dsd.regs = regs;
cfba9872 3027 dsd.dsc = dsc.get ();
034f1a81 3028 dsd.insn_count = 0;
b6542f81
YQ		 3029 aarch64_relocate_instruction (insn, &visitor,
3030 (struct aarch64_insn_data *) &dsd);
e935475c 3031 gdb_assert (dsd.insn_count <= AARCH64_DISPLACED_MODIFIED_INSNS);
b6542f81
YQ		 3032
3033 if (dsd.insn_count != 0)
3034 {
3035 int i;
3036
3037 /* Instruction can be relocated to scratch pad. Copy
3038 relocated instruction(s) there. */
3039 for (i = 0; i < dsd.insn_count; i++)
3040 {
3041 if (debug_displaced)
3042 {
3043 debug_printf ("displaced: writing insn ");
3044 debug_printf ("%.8x", dsd.insn_buf[i]);
3045 debug_printf (" at %s\n", paddress (gdbarch, to + i * 4));
3046 }
3047 write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
3048 (ULONGEST) dsd.insn_buf[i]);
3049 }
3050 }
3051 else
3052 {
b6542f81
YQ		 3053 dsc = NULL;
3054 }
3055
e8217e61 3056 return dsc;
b6542f81
YQ		 3057}
3058
3059/* Implement the "displaced_step_fixup" gdbarch method. */
3060
3061void
3062aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
cfba9872 3063 struct displaced_step_closure *dsc_,
b6542f81
YQ		 3064 CORE_ADDR from, CORE_ADDR to,
3065 struct regcache *regs)
3066{
cfba9872
SM		 3067 aarch64_displaced_step_closure *dsc = (aarch64_displaced_step_closure *) dsc_;
3068
0c271889
LM		 3069 ULONGEST pc;
3070
3071 regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
3072
1ab139e5
LM		 3073 if (debug_displaced)
3074 debug_printf ("Displaced: PC after stepping: %s (was %s).\n",
3075 paddress (gdbarch, pc), paddress (gdbarch, to));
3076
b6542f81
YQ		 3077 if (dsc->cond)
3078 {
1ab139e5
LM		 3079 if (debug_displaced)
3080 debug_printf ("Displaced: [Conditional] pc_adjust before: %d\n",
3081 dsc->pc_adjust);
3082
b6542f81
YQ		 3083 if (pc - to == 8)
3084 {
3085 /* Condition is true. */
3086 }
3087 else if (pc - to == 4)
3088 {
3089 /* Condition is false. */
3090 dsc->pc_adjust = 4;
3091 }
3092 else
3093 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
1ab139e5
LM		 3094
3095 if (debug_displaced)
3096 debug_printf ("Displaced: [Conditional] pc_adjust after: %d\n",
3097 dsc->pc_adjust);
b6542f81
YQ		 3098 }
3099
1ab139e5
LM		 3100 if (debug_displaced)
3101 debug_printf ("Displaced: %s PC by %d\n",
3102 dsc->pc_adjust? "adjusting" : "not adjusting",
3103 dsc->pc_adjust);
3104
3105
b6542f81
YQ		 3106 if (dsc->pc_adjust != 0)
3107 {
0c271889
LM		 3108 /* Make sure the previous instruction was executed (that is, the PC
3109 has changed). If the PC didn't change, then discard the adjustment
3110 offset. Otherwise we may skip an instruction before its execution
3111 took place. */
3112 if ((pc - to) == 0)
1ab139e5
LM		 3113 {
3114 if (debug_displaced)
3115 debug_printf ("Displaced: PC did not move. Discarding PC "
3116 "adjustment.\n");
3117 dsc->pc_adjust = 0;
3118 }
0c271889 3119
b6542f81
YQ		 3120 if (debug_displaced)
3121 {
1ab139e5 3122 debug_printf ("Displaced: fixup: set PC to %s:%d\n",
b6542f81
YQ		 3123 paddress (gdbarch, from), dsc->pc_adjust);
3124 }
3125 regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
3126 from + dsc->pc_adjust);
3127 }
3128}
3129
3130/* Implement the "displaced_step_hw_singlestep" gdbarch method. */
3131
3132int
3133aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
3134 struct displaced_step_closure *closure)
3135{
3136 return 1;
3137}
3138
95228a0d
AH		 3139/* Get the correct target description for the given VQ value.
3140 If VQ is zero then it is assumed SVE is not supported.
3141 (It is not possible to set VQ to zero on an SVE system). */
da434ccb
AH		 3142
3143const target_desc *
6dc0ebde 3144aarch64_read_description (uint64_t vq, bool pauth_p)
da434ccb 3145{
95228a0d 3146 if (vq > AARCH64_MAX_SVE_VQ)
39bfb937 3147 error (_("VQ is %" PRIu64 ", maximum supported value is %d"), vq,
95228a0d
AH		 3148 AARCH64_MAX_SVE_VQ);
3149
6dc0ebde 3150 struct target_desc *tdesc = tdesc_aarch64_list[vq][pauth_p];
da434ccb 3151
95228a0d
AH		 3152 if (tdesc == NULL)
3153 {
6dc0ebde
AH		 3154 tdesc = aarch64_create_target_description (vq, pauth_p);
3155 tdesc_aarch64_list[vq][pauth_p] = tdesc;
95228a0d 3156 }
da434ccb 3157
95228a0d 3158 return tdesc;
da434ccb
AH		 3159}
3160
ba2d2bb2
AH		 3161/* Return the VQ used when creating the target description TDESC. */
3162
1332a140 3163static uint64_t
ba2d2bb2
AH		 3164aarch64_get_tdesc_vq (const struct target_desc *tdesc)
3165{
3166 const struct tdesc_feature *feature_sve;
3167
3168 if (!tdesc_has_registers (tdesc))
3169 return 0;
3170
3171 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
3172
3173 if (feature_sve == nullptr)
3174 return 0;
3175
12863263
AH		 3176 uint64_t vl = tdesc_register_bitsize (feature_sve,
3177 aarch64_sve_register_names[0]) / 8;
ba2d2bb2
AH		 3178 return sve_vq_from_vl (vl);
3179}
3180
0ef8a082
AH		 3181/* Add all the expected register sets into GDBARCH. */
3182
3183static void
3184aarch64_add_reggroups (struct gdbarch *gdbarch)
3185{
3186 reggroup_add (gdbarch, general_reggroup);
3187 reggroup_add (gdbarch, float_reggroup);
3188 reggroup_add (gdbarch, system_reggroup);
3189 reggroup_add (gdbarch, vector_reggroup);
3190 reggroup_add (gdbarch, all_reggroup);
3191 reggroup_add (gdbarch, save_reggroup);
3192 reggroup_add (gdbarch, restore_reggroup);
3193}
ba2d2bb2 3194
76bed0fd
AH		 3195/* Implement the "cannot_store_register" gdbarch method. */
3196
3197static int
3198aarch64_cannot_store_register (struct gdbarch *gdbarch, int regnum)
3199{
3200 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3201
3202 if (!tdep->has_pauth ())
3203 return 0;
3204
3205 /* Pointer authentication registers are read-only. */
3206 return (regnum == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
3207 || regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base));
3208}
3209
07b287a0
MS		 3210/* Initialize the current architecture based on INFO. If possible,
3211 re-use an architecture from ARCHES, which is a list of
3212 architectures already created during this debugging session.
3213
3214 Called e.g. at program startup, when reading a core file, and when
3215 reading a binary file. */
3216
3217static struct gdbarch *
3218aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3219{
ccb8d7e8 3220 const struct tdesc_feature *feature_core, *feature_fpu, *feature_sve;
76bed0fd 3221 const struct tdesc_feature *feature_pauth;
ccb8d7e8
AH		 3222 bool valid_p = true;
3223 int i, num_regs = 0, num_pseudo_regs = 0;
3224 int first_pauth_regnum = -1, pauth_ra_state_offset = -1;
3225
4da037ef
AH		 3226 /* Use the vector length passed via the target info. Here -1 is used for no
3227 SVE, and 0 is unset. If unset then use the vector length from the existing
3228 tdesc. */
3229 uint64_t vq = 0;
3230 if (info.id == (int *) -1)
3231 vq = 0;
3232 else if (info.id != 0)
3233 vq = (uint64_t) info.id;
3234 else
3235 vq = aarch64_get_tdesc_vq (info.target_desc);
3236
3237 if (vq > AARCH64_MAX_SVE_VQ)
596179f7
SDJ		 3238 internal_error (__FILE__, __LINE__, _("VQ out of bounds: %s (max %d)"),
3239 pulongest (vq), AARCH64_MAX_SVE_VQ);
4da037ef 3240
ccb8d7e8
AH		 3241 /* If there is already a candidate, use it. */
3242 for (gdbarch_list *best_arch = gdbarch_list_lookup_by_info (arches, &info);
3243 best_arch != nullptr;
3244 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
3245 {
3246 struct gdbarch_tdep *tdep = gdbarch_tdep (best_arch->gdbarch);
4da037ef 3247 if (tdep && tdep->vq == vq)
ccb8d7e8
AH		 3248 return best_arch->gdbarch;
3249 }
07b287a0 3250
4da037ef
AH		 3251 /* Ensure we always have a target descriptor, and that it is for the given VQ
3252 value. */
ccb8d7e8 3253 const struct target_desc *tdesc = info.target_desc;
4da037ef
AH		 3254 if (!tdesc_has_registers (tdesc) || vq != aarch64_get_tdesc_vq (tdesc))
3255 tdesc = aarch64_read_description (vq, false);
07b287a0
MS		 3256 gdb_assert (tdesc);
3257
ccb8d7e8 3258 feature_core = tdesc_find_feature (tdesc,"org.gnu.gdb.aarch64.core");
ba2d2bb2
AH		 3259 feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
3260 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
76bed0fd 3261 feature_pauth = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.pauth");
07b287a0 3262
ccb8d7e8
AH		 3263 if (feature_core == nullptr)
3264 return nullptr;
07b287a0 3265
ccb8d7e8 3266 struct tdesc_arch_data *tdesc_data = tdesc_data_alloc ();
07b287a0 3267
ba2d2bb2 3268 /* Validate the description provides the mandatory core R registers
07b287a0
MS		 3269 and allocate their numbers. */
3270 for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
ba2d2bb2
AH		 3271 valid_p &= tdesc_numbered_register (feature_core, tdesc_data,
3272 AARCH64_X0_REGNUM + i,
3273 aarch64_r_register_names[i]);
07b287a0
MS		 3274
3275 num_regs = AARCH64_X0_REGNUM + i;
3276
ba2d2bb2 3277 /* Add the V registers. */
ccb8d7e8 3278 if (feature_fpu != nullptr)
07b287a0 3279 {
ccb8d7e8 3280 if (feature_sve != nullptr)
ba2d2bb2
AH		 3281 error (_("Program contains both fpu and SVE features."));
3282
3283 /* Validate the description provides the mandatory V registers
3284 and allocate their numbers. */
07b287a0 3285 for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
ba2d2bb2
AH		 3286 valid_p &= tdesc_numbered_register (feature_fpu, tdesc_data,
3287 AARCH64_V0_REGNUM + i,
3288 aarch64_v_register_names[i]);
07b287a0
MS		 3289
3290 num_regs = AARCH64_V0_REGNUM + i;
ba2d2bb2 3291 }
07b287a0 3292
ba2d2bb2 3293 /* Add the SVE registers. */
ccb8d7e8 3294 if (feature_sve != nullptr)
ba2d2bb2
AH		 3295 {
3296 /* Validate the description provides the mandatory SVE registers
3297 and allocate their numbers. */
3298 for (i = 0; i < ARRAY_SIZE (aarch64_sve_register_names); i++)
3299 valid_p &= tdesc_numbered_register (feature_sve, tdesc_data,
3300 AARCH64_SVE_Z0_REGNUM + i,
3301 aarch64_sve_register_names[i]);
3302
3303 num_regs = AARCH64_SVE_Z0_REGNUM + i;
3304 num_pseudo_regs += 32; /* add the Vn register pseudos. */
3305 }
3306
ccb8d7e8 3307 if (feature_fpu != nullptr || feature_sve != nullptr)
ba2d2bb2 3308 {
07b287a0
MS		 3309 num_pseudo_regs += 32; /* add the Qn scalar register pseudos */
3310 num_pseudo_regs += 32; /* add the Dn scalar register pseudos */
3311 num_pseudo_regs += 32; /* add the Sn scalar register pseudos */
3312 num_pseudo_regs += 32; /* add the Hn scalar register pseudos */
3313 num_pseudo_regs += 32; /* add the Bn scalar register pseudos */
3314 }
3315
76bed0fd
AH		 3316 /* Add the pauth registers. */
3317 if (feature_pauth != NULL)
3318 {
3319 first_pauth_regnum = num_regs;
34dcc7cf 3320 pauth_ra_state_offset = num_pseudo_regs;
76bed0fd
AH		 3321 /* Validate the descriptor provides the mandatory PAUTH registers and
3322 allocate their numbers. */
3323 for (i = 0; i < ARRAY_SIZE (aarch64_pauth_register_names); i++)
3324 valid_p &= tdesc_numbered_register (feature_pauth, tdesc_data,
3325 first_pauth_regnum + i,
3326 aarch64_pauth_register_names[i]);
3327
3328 num_regs += i;
34dcc7cf 3329 num_pseudo_regs += 1; /* Count RA_STATE pseudo register. */
76bed0fd
AH		 3330 }
3331
07b287a0
MS		 3332 if (!valid_p)
3333 {
3334 tdesc_data_cleanup (tdesc_data);
ccb8d7e8 3335 return nullptr;
07b287a0
MS		 3336 }
3337
3338 /* AArch64 code is always little-endian. */
3339 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
3340
ccb8d7e8
AH		 3341 struct gdbarch_tdep *tdep = XCNEW (struct gdbarch_tdep);
3342 struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep);
07b287a0
MS		 3343
3344 /* This should be low enough for everything. */
3345 tdep->lowest_pc = 0x20;
3346 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
3347 tdep->jb_elt_size = 8;
4da037ef 3348 tdep->vq = vq;
76bed0fd 3349 tdep->pauth_reg_base = first_pauth_regnum;
34dcc7cf
AH		 3350 tdep->pauth_ra_state_regnum = (feature_pauth == NULL) ? -1
3351 : pauth_ra_state_offset + num_regs;
3352
07b287a0
MS		 3353 set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
3354 set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
3355
07b287a0
MS		 3356 /* Advance PC across function entry code. */
3357 set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue);
3358
3359 /* The stack grows downward. */
3360 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3361
3362 /* Breakpoint manipulation. */
04180708
YQ		 3363 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
3364 aarch64_breakpoint::kind_from_pc);
3365 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
3366 aarch64_breakpoint::bp_from_kind);
07b287a0 3367 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
9404b58f 3368 set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step);
07b287a0
MS		 3369
3370 /* Information about registers, etc. */
3371 set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM);
3372 set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM);
3373 set_gdbarch_num_regs (gdbarch, num_regs);
3374
3375 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
3376 set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value);
3377 set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write);
3378 set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name);
3379 set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type);
3380 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3381 aarch64_pseudo_register_reggroup_p);
76bed0fd 3382 set_gdbarch_cannot_store_register (gdbarch, aarch64_cannot_store_register);
07b287a0
MS		 3383
3384 /* ABI */
3385 set_gdbarch_short_bit (gdbarch, 16);
3386 set_gdbarch_int_bit (gdbarch, 32);
3387 set_gdbarch_float_bit (gdbarch, 32);
3388 set_gdbarch_double_bit (gdbarch, 64);
3389 set_gdbarch_long_double_bit (gdbarch, 128);
3390 set_gdbarch_long_bit (gdbarch, 64);
3391 set_gdbarch_long_long_bit (gdbarch, 64);
3392 set_gdbarch_ptr_bit (gdbarch, 64);
3393 set_gdbarch_char_signed (gdbarch, 0);
53375380 3394 set_gdbarch_wchar_signed (gdbarch, 0);
07b287a0
MS		 3395 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
3396 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3397 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
b907456c 3398 set_gdbarch_type_align (gdbarch, aarch64_type_align);
07b287a0
MS		 3399
3400 /* Internal <-> external register number maps. */
3401 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum);
3402
3403 /* Returning results. */
3404 set_gdbarch_return_value (gdbarch, aarch64_return_value);
3405
3406 /* Disassembly. */
3407 set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn);
3408
3409 /* Virtual tables. */
3410 set_gdbarch_vbit_in_delta (gdbarch, 1);
3411
0ef8a082
AH		 3412 /* Register architecture. */
3413 aarch64_add_reggroups (gdbarch);
3414
07b287a0
MS		 3415 /* Hook in the ABI-specific overrides, if they have been registered. */
3416 info.target_desc = tdesc;
0dba2a6c 3417 info.tdesc_data = tdesc_data;
07b287a0
MS		 3418 gdbarch_init_osabi (info, gdbarch);
3419
3420 dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
11e1b75f
AH		 3421 /* Register DWARF CFA vendor handler. */
3422 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch,
3423 aarch64_execute_dwarf_cfa_vendor_op);
07b287a0 3424
5133a315
LM		 3425 /* Permanent/Program breakpoint handling. */
3426 set_gdbarch_program_breakpoint_here_p (gdbarch,
3427 aarch64_program_breakpoint_here_p);
3428
07b287a0
MS		 3429 /* Add some default predicates. */
3430 frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind);
3431 dwarf2_append_unwinders (gdbarch);
3432 frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind);
3433
3434 frame_base_set_default (gdbarch, &aarch64_normal_base);
3435
3436 /* Now we have tuned the configuration, set a few final things,
3437 based on what the OS ABI has told us. */
3438
3439 if (tdep->jb_pc >= 0)
3440 set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target);
3441
ea873d8e
PL		 3442 set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address);
3443
aa7ca1bb
AH		 3444 set_gdbarch_get_pc_address_flags (gdbarch, aarch64_get_pc_address_flags);
3445
07b287a0
MS		 3446 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3447
3448 /* Add standard register aliases. */
3449 for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
3450 user_reg_add (gdbarch, aarch64_register_aliases[i].name,
3451 value_of_aarch64_user_reg,
3452 &aarch64_register_aliases[i].regnum);
3453
e8bf1ce4
JB		 3454 register_aarch64_ravenscar_ops (gdbarch);
3455
07b287a0
MS		 3456 return gdbarch;
3457}
3458
3459static void
3460aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3461{
3462 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3463
3464 if (tdep == NULL)
3465 return;
3466
3467 fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3468 paddress (gdbarch, tdep->lowest_pc));
3469}
3470
0d4c07af 3471#if GDB_SELF_TEST
1e2b521d
YQ		 3472namespace selftests
3473{
3474static void aarch64_process_record_test (void);
3475}
0d4c07af 3476#endif
1e2b521d 3477
6c265988 3478void _initialize_aarch64_tdep ();
07b287a0 3479void
6c265988 3480_initialize_aarch64_tdep ()
07b287a0
MS		 3481{
3482 gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
3483 aarch64_dump_tdep);
3484
07b287a0
MS		 3485 /* Debug this file's internals. */
3486 add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
3487Set AArch64 debugging."), _("\
3488Show AArch64 debugging."), _("\
3489When on, AArch64 specific debugging is enabled."),
3490 NULL,
3491 show_aarch64_debug,
3492 &setdebuglist, &showdebuglist);
4d9a9006
YQ		 3493
3494#if GDB_SELF_TEST
1526853e
SM		 3495 selftests::register_test ("aarch64-analyze-prologue",
3496 selftests::aarch64_analyze_prologue_test);
3497 selftests::register_test ("aarch64-process-record",
3498 selftests::aarch64_process_record_test);
4d9a9006 3499#endif
07b287a0 3500}
99afc88b
OJ		 3501
3502/* AArch64 process record-replay related structures, defines etc. */
3503
99afc88b
OJ		 3504#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3505 do \
3506 { \
3507 unsigned int reg_len = LENGTH; \
3508 if (reg_len) \
3509 { \
3510 REGS = XNEWVEC (uint32_t, reg_len); \
3511 memcpy(&REGS[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3512 } \
3513 } \
3514 while (0)
3515
3516#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3517 do \
3518 { \
3519 unsigned int mem_len = LENGTH; \
3520 if (mem_len) \
3521 { \
3522 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3523 memcpy(&MEMS->len, &RECORD_BUF[0], \
3524 sizeof(struct aarch64_mem_r) * LENGTH); \
3525 } \
3526 } \
3527 while (0)
3528
3529/* AArch64 record/replay structures and enumerations. */
3530
3531struct aarch64_mem_r
3532{
3533 uint64_t len; /* Record length. */
3534 uint64_t addr; /* Memory address. */
3535};
3536
3537enum aarch64_record_result
3538{
3539 AARCH64_RECORD_SUCCESS,
99afc88b
OJ		 3540 AARCH64_RECORD_UNSUPPORTED,
3541 AARCH64_RECORD_UNKNOWN
3542};
3543
3544typedef struct insn_decode_record_t
3545{
3546 struct gdbarch *gdbarch;
3547 struct regcache *regcache;
3548 CORE_ADDR this_addr; /* Address of insn to be recorded. */
3549 uint32_t aarch64_insn; /* Insn to be recorded. */
3550 uint32_t mem_rec_count; /* Count of memory records. */
3551 uint32_t reg_rec_count; /* Count of register records. */
3552 uint32_t *aarch64_regs; /* Registers to be recorded. */
3553 struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */
3554} insn_decode_record;
3555
3556/* Record handler for data processing - register instructions. */
3557
3558static unsigned int
3559aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
3560{
3561 uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
3562 uint32_t record_buf[4];
3563
3564 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3565 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3566 insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23);
3567
3568 if (!bit (aarch64_insn_r->aarch64_insn, 28))
3569 {
3570 uint8_t setflags;
3571
3572 /* Logical (shifted register). */
3573 if (insn_bits24_27 == 0x0a)
3574 setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03);
3575 /* Add/subtract. */
3576 else if (insn_bits24_27 == 0x0b)
3577 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3578 else
3579 return AARCH64_RECORD_UNKNOWN;
3580
3581 record_buf[0] = reg_rd;
3582 aarch64_insn_r->reg_rec_count = 1;
3583 if (setflags)
3584 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3585 }
3586 else
3587 {
3588 if (insn_bits24_27 == 0x0b)
3589 {
3590 /* Data-processing (3 source). */
3591 record_buf[0] = reg_rd;
3592 aarch64_insn_r->reg_rec_count = 1;
3593 }
3594 else if (insn_bits24_27 == 0x0a)
3595 {
3596 if (insn_bits21_23 == 0x00)
3597 {
3598 /* Add/subtract (with carry). */
3599 record_buf[0] = reg_rd;
3600 aarch64_insn_r->reg_rec_count = 1;
3601 if (bit (aarch64_insn_r->aarch64_insn, 29))
3602 {
3603 record_buf[1] = AARCH64_CPSR_REGNUM;
3604 aarch64_insn_r->reg_rec_count = 2;
3605 }
3606 }
3607 else if (insn_bits21_23 == 0x02)
3608 {
3609 /* Conditional compare (register) and conditional compare
3610 (immediate) instructions. */
3611 record_buf[0] = AARCH64_CPSR_REGNUM;
3612 aarch64_insn_r->reg_rec_count = 1;
3613 }
3614 else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
3615 {
85102364 3616 /* Conditional select. */
99afc88b
OJ		 3617 /* Data-processing (2 source). */
3618 /* Data-processing (1 source). */
3619 record_buf[0] = reg_rd;
3620 aarch64_insn_r->reg_rec_count = 1;
3621 }
3622 else
3623 return AARCH64_RECORD_UNKNOWN;
3624 }
3625 }
3626
3627 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3628 record_buf);
3629 return AARCH64_RECORD_SUCCESS;
3630}
3631
3632/* Record handler for data processing - immediate instructions. */
3633
3634static unsigned int
3635aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
3636{
78cc6c2d 3637 uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags;
99afc88b
OJ		 3638 uint32_t record_buf[4];
3639
3640 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
99afc88b
OJ		 3641 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3642 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3643
3644 if (insn_bits24_27 == 0x00 /* PC rel addressing. */
3645 || insn_bits24_27 == 0x03 /* Bitfield and Extract. */
3646 || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */
3647 {
3648 record_buf[0] = reg_rd;
3649 aarch64_insn_r->reg_rec_count = 1;
3650 }
3651 else if (insn_bits24_27 == 0x01)
3652 {
3653 /* Add/Subtract (immediate). */
3654 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3655 record_buf[0] = reg_rd;
3656 aarch64_insn_r->reg_rec_count = 1;
3657 if (setflags)
3658 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3659 }
3660 else if (insn_bits24_27 == 0x02 && !insn_bit23)
3661 {
3662 /* Logical (immediate). */
3663 setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03;
3664 record_buf[0] = reg_rd;
3665 aarch64_insn_r->reg_rec_count = 1;
3666 if (setflags)
3667 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3668 }
3669 else
3670 return AARCH64_RECORD_UNKNOWN;
3671
3672 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3673 record_buf);
3674 return AARCH64_RECORD_SUCCESS;
3675}
3676
3677/* Record handler for branch, exception generation and system instructions. */
3678
3679static unsigned int
3680aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
3681{
3682 struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch);
3683 uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
3684 uint32_t record_buf[4];
3685
3686 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3687 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3688 insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3689
3690 if (insn_bits28_31 == 0x0d)
3691 {
3692 /* Exception generation instructions. */
3693 if (insn_bits24_27 == 0x04)
3694 {
5d98d3cd
YQ		 3695 if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
3696 && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
3697 && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
99afc88b
OJ		 3698 {
3699 ULONGEST svc_number;
3700
3701 regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8,
3702 &svc_number);
3703 return tdep->aarch64_syscall_record (aarch64_insn_r->regcache,
3704 svc_number);
3705 }
3706 else
3707 return AARCH64_RECORD_UNSUPPORTED;
3708 }
3709 /* System instructions. */
3710 else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
3711 {
3712 uint32_t reg_rt, reg_crn;
3713
3714 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3715 reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3716
3717 /* Record rt in case of sysl and mrs instructions. */
3718 if (bit (aarch64_insn_r->aarch64_insn, 21))
3719 {
3720 record_buf[0] = reg_rt;
3721 aarch64_insn_r->reg_rec_count = 1;
3722 }
3723 /* Record cpsr for hint and msr(immediate) instructions. */
3724 else if (reg_crn == 0x02 || reg_crn == 0x04)
3725 {
3726 record_buf[0] = AARCH64_CPSR_REGNUM;
3727 aarch64_insn_r->reg_rec_count = 1;
3728 }
3729 }
3730 /* Unconditional branch (register). */
3731 else if((insn_bits24_27 & 0x0e) == 0x06)
3732 {
3733 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3734 if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01)
3735 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3736 }
3737 else
3738 return AARCH64_RECORD_UNKNOWN;
3739 }
3740 /* Unconditional branch (immediate). */
3741 else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04)
3742 {
3743 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3744 if (bit (aarch64_insn_r->aarch64_insn, 31))
3745 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3746 }
3747 else
3748 /* Compare & branch (immediate), Test & branch (immediate) and
3749 Conditional branch (immediate). */
3750 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3751
3752 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3753 record_buf);
3754 return AARCH64_RECORD_SUCCESS;
3755}
3756
3757/* Record handler for advanced SIMD load and store instructions. */
3758
3759static unsigned int
3760aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
3761{
3762 CORE_ADDR address;
3763 uint64_t addr_offset = 0;
3764 uint32_t record_buf[24];
3765 uint64_t record_buf_mem[24];
3766 uint32_t reg_rn, reg_rt;
3767 uint32_t reg_index = 0, mem_index = 0;
3768 uint8_t opcode_bits, size_bits;
3769
3770 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3771 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3772 size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3773 opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3774 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
3775
3776 if (record_debug)
b277c936 3777 debug_printf ("Process record: Advanced SIMD load/store\n");
99afc88b
OJ		 3778
3779 /* Load/store single structure. */
3780 if (bit (aarch64_insn_r->aarch64_insn, 24))
3781 {
3782 uint8_t sindex, scale, selem, esize, replicate = 0;
3783 scale = opcode_bits >> 2;
3784 selem = ((opcode_bits & 0x02) |
3785 bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
3786 switch (scale)
3787 {
3788 case 1:
3789 if (size_bits & 0x01)
3790 return AARCH64_RECORD_UNKNOWN;
3791 break;
3792 case 2:
3793 if ((size_bits >> 1) & 0x01)
3794 return AARCH64_RECORD_UNKNOWN;
3795 if (size_bits & 0x01)
3796 {
3797 if (!((opcode_bits >> 1) & 0x01))
3798 scale = 3;
3799 else
3800 return AARCH64_RECORD_UNKNOWN;
3801 }
3802 break;
3803 case 3:
3804 if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
3805 {
3806 scale = size_bits;
3807 replicate = 1;
3808 break;
3809 }
3810 else
3811 return AARCH64_RECORD_UNKNOWN;
3812 default:
3813 break;
3814 }
3815 esize = 8 << scale;
3816 if (replicate)
3817 for (sindex = 0; sindex < selem; sindex++)
3818 {
3819 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3820 reg_rt = (reg_rt + 1) % 32;
3821 }
3822 else
3823 {
3824 for (sindex = 0; sindex < selem; sindex++)
a2e3e93f
SM		 3825 {
3826 if (bit (aarch64_insn_r->aarch64_insn, 22))
3827 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3828 else
3829 {
3830 record_buf_mem[mem_index++] = esize / 8;
3831 record_buf_mem[mem_index++] = address + addr_offset;
3832 }
3833 addr_offset = addr_offset + (esize / 8);
3834 reg_rt = (reg_rt + 1) % 32;
3835 }
99afc88b
OJ		 3836 }
3837 }
3838 /* Load/store multiple structure. */
3839 else
3840 {
3841 uint8_t selem, esize, rpt, elements;
3842 uint8_t eindex, rindex;
3843
3844 esize = 8 << size_bits;
3845 if (bit (aarch64_insn_r->aarch64_insn, 30))
3846 elements = 128 / esize;
3847 else
3848 elements = 64 / esize;
3849
3850 switch (opcode_bits)
3851 {
3852 /*LD/ST4 (4 Registers). */
3853 case 0:
3854 rpt = 1;
3855 selem = 4;
3856 break;
3857 /*LD/ST1 (4 Registers). */
3858 case 2:
3859 rpt = 4;
3860 selem = 1;
3861 break;
3862 /*LD/ST3 (3 Registers). */
3863 case 4:
3864 rpt = 1;
3865 selem = 3;
3866 break;
3867 /*LD/ST1 (3 Registers). */
3868 case 6:
3869 rpt = 3;
3870 selem = 1;
3871 break;
3872 /*LD/ST1 (1 Register). */
3873 case 7:
3874 rpt = 1;
3875 selem = 1;
3876 break;
3877 /*LD/ST2 (2 Registers). */
3878 case 8:
3879 rpt = 1;
3880 selem = 2;
3881 break;
3882 /*LD/ST1 (2 Registers). */
3883 case 10:
3884 rpt = 2;
3885 selem = 1;
3886 break;
3887 default:
3888 return AARCH64_RECORD_UNSUPPORTED;
3889 break;
3890 }
3891 for (rindex = 0; rindex < rpt; rindex++)
3892 for (eindex = 0; eindex < elements; eindex++)
3893 {
3894 uint8_t reg_tt, sindex;
3895 reg_tt = (reg_rt + rindex) % 32;
3896 for (sindex = 0; sindex < selem; sindex++)
3897 {
3898 if (bit (aarch64_insn_r->aarch64_insn, 22))
3899 record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
3900 else
3901 {
3902 record_buf_mem[mem_index++] = esize / 8;
3903 record_buf_mem[mem_index++] = address + addr_offset;
3904 }
3905 addr_offset = addr_offset + (esize / 8);
3906 reg_tt = (reg_tt + 1) % 32;
3907 }
3908 }
3909 }
3910
3911 if (bit (aarch64_insn_r->aarch64_insn, 23))
3912 record_buf[reg_index++] = reg_rn;
3913
3914 aarch64_insn_r->reg_rec_count = reg_index;
3915 aarch64_insn_r->mem_rec_count = mem_index / 2;
3916 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3917 record_buf_mem);
3918 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3919 record_buf);
3920 return AARCH64_RECORD_SUCCESS;
3921}
3922
3923/* Record handler for load and store instructions. */
3924
3925static unsigned int
3926aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
3927{
3928 uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
3929 uint8_t insn_bit23, insn_bit21;
3930 uint8_t opc, size_bits, ld_flag, vector_flag;
3931 uint32_t reg_rn, reg_rt, reg_rt2;
3932 uint64_t datasize, offset;
3933 uint32_t record_buf[8];
3934 uint64_t record_buf_mem[8];
3935 CORE_ADDR address;
3936
3937 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3938 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3939 insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29);
3940 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3941 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3942 ld_flag = bit (aarch64_insn_r->aarch64_insn, 22);
3943 vector_flag = bit (aarch64_insn_r->aarch64_insn, 26);
3944 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3945 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3946 reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14);
3947 size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31);
3948
3949 /* Load/store exclusive. */
3950 if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
3951 {
3952 if (record_debug)
b277c936 3953 debug_printf ("Process record: load/store exclusive\n");
99afc88b
OJ		 3954
3955 if (ld_flag)
3956 {
3957 record_buf[0] = reg_rt;
3958 aarch64_insn_r->reg_rec_count = 1;
3959 if (insn_bit21)
3960 {
3961 record_buf[1] = reg_rt2;
3962 aarch64_insn_r->reg_rec_count = 2;
3963 }
3964 }
3965 else
3966 {
3967 if (insn_bit21)
3968 datasize = (8 << size_bits) * 2;
3969 else
3970 datasize = (8 << size_bits);
3971 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3972 &address);
3973 record_buf_mem[0] = datasize / 8;
3974 record_buf_mem[1] = address;
3975 aarch64_insn_r->mem_rec_count = 1;
3976 if (!insn_bit23)
3977 {
3978 /* Save register rs. */
3979 record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20);
3980 aarch64_insn_r->reg_rec_count = 1;
3981 }
3982 }
3983 }
3984 /* Load register (literal) instructions decoding. */
3985 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
3986 {
3987 if (record_debug)
b277c936 3988 debug_printf ("Process record: load register (literal)\n");
99afc88b
OJ		 3989 if (vector_flag)
3990 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3991 else
3992 record_buf[0] = reg_rt;
3993 aarch64_insn_r->reg_rec_count = 1;
3994 }
3995 /* All types of load/store pair instructions decoding. */
3996 else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
3997 {
3998 if (record_debug)
b277c936 3999 debug_printf ("Process record: load/store pair\n");
99afc88b
OJ		 4000
4001 if (ld_flag)
4002 {
4003 if (vector_flag)
4004 {
4005 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4006 record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
4007 }
4008 else
4009 {
4010 record_buf[0] = reg_rt;
4011 record_buf[1] = reg_rt2;
4012 }
4013 aarch64_insn_r->reg_rec_count = 2;
4014 }
4015 else
4016 {
4017 uint16_t imm7_off;
4018 imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
4019 if (!vector_flag)
4020 size_bits = size_bits >> 1;
4021 datasize = 8 << (2 + size_bits);
4022 offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
4023 offset = offset << (2 + size_bits);
4024 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4025 &address);
4026 if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
4027 {
4028 if (imm7_off & 0x40)
4029 address = address - offset;
4030 else
4031 address = address + offset;
4032 }
4033
4034 record_buf_mem[0] = datasize / 8;
4035 record_buf_mem[1] = address;
4036 record_buf_mem[2] = datasize / 8;
4037 record_buf_mem[3] = address + (datasize / 8);
4038 aarch64_insn_r->mem_rec_count = 2;
4039 }
4040 if (bit (aarch64_insn_r->aarch64_insn, 23))
4041 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
4042 }
4043 /* Load/store register (unsigned immediate) instructions. */
4044 else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
4045 {
4046 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4047 if (!(opc >> 1))
33877125
YQ		 4048 {
4049 if (opc & 0x01)
4050 ld_flag = 0x01;
4051 else
4052 ld_flag = 0x0;
4053 }
99afc88b 4054 else
33877125 4055 {
1e2b521d
YQ		 4056 if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2)
4057 {
4058 /* PRFM (immediate) */
4059 return AARCH64_RECORD_SUCCESS;
4060 }
4061 else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2)
4062 {
4063 /* LDRSW (immediate) */
4064 ld_flag = 0x1;
4065 }
33877125 4066 else
1e2b521d
YQ		 4067 {
4068 if (opc & 0x01)
4069 ld_flag = 0x01;
4070 else
4071 ld_flag = 0x0;
4072 }
33877125 4073 }
99afc88b
OJ		 4074
4075 if (record_debug)
4076 {
b277c936
PL		 4077 debug_printf ("Process record: load/store (unsigned immediate):"
4078 " size %x V %d opc %x\n", size_bits, vector_flag,
4079 opc);
99afc88b
OJ		 4080 }
4081
4082 if (!ld_flag)
4083 {
4084 offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
4085 datasize = 8 << size_bits;
4086 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4087 &address);
4088 offset = offset << size_bits;
4089 address = address + offset;
4090
4091 record_buf_mem[0] = datasize >> 3;
4092 record_buf_mem[1] = address;
4093 aarch64_insn_r->mem_rec_count = 1;
4094 }
4095 else
4096 {
4097 if (vector_flag)
4098 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4099 else
4100 record_buf[0] = reg_rt;
4101 aarch64_insn_r->reg_rec_count = 1;
4102 }
4103 }
4104 /* Load/store register (register offset) instructions. */
5d98d3cd
YQ		 4105 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
4106 && insn_bits10_11 == 0x02 && insn_bit21)
99afc88b
OJ		 4107 {
4108 if (record_debug)
b277c936 4109 debug_printf ("Process record: load/store (register offset)\n");
99afc88b
OJ		 4110 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4111 if (!(opc >> 1))
4112 if (opc & 0x01)
4113 ld_flag = 0x01;
4114 else
4115 ld_flag = 0x0;
4116 else
4117 if (size_bits != 0x03)
4118 ld_flag = 0x01;
4119 else
4120 return AARCH64_RECORD_UNKNOWN;
4121
4122 if (!ld_flag)
4123 {
d9436c7c
PA		 4124 ULONGEST reg_rm_val;
4125
99afc88b
OJ		 4126 regcache_raw_read_unsigned (aarch64_insn_r->regcache,
4127 bits (aarch64_insn_r->aarch64_insn, 16, 20), &reg_rm_val);
4128 if (bit (aarch64_insn_r->aarch64_insn, 12))
4129 offset = reg_rm_val << size_bits;
4130 else
4131 offset = reg_rm_val;
4132 datasize = 8 << size_bits;
4133 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4134 &address);
4135 address = address + offset;
4136 record_buf_mem[0] = datasize >> 3;
4137 record_buf_mem[1] = address;
4138 aarch64_insn_r->mem_rec_count = 1;
4139 }
4140 else
4141 {
4142 if (vector_flag)
4143 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4144 else
4145 record_buf[0] = reg_rt;
4146 aarch64_insn_r->reg_rec_count = 1;
4147 }
4148 }
4149 /* Load/store register (immediate and unprivileged) instructions. */
5d98d3cd
YQ		 4150 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
4151 && !insn_bit21)
99afc88b
OJ		 4152 {
4153 if (record_debug)
4154 {
b277c936
PL		 4155 debug_printf ("Process record: load/store "
4156 "(immediate and unprivileged)\n");
99afc88b
OJ		 4157 }
4158 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4159 if (!(opc >> 1))
4160 if (opc & 0x01)
4161 ld_flag = 0x01;
4162 else
4163 ld_flag = 0x0;
4164 else
4165 if (size_bits != 0x03)
4166 ld_flag = 0x01;
4167 else
4168 return AARCH64_RECORD_UNKNOWN;
4169
4170 if (!ld_flag)
4171 {
4172 uint16_t imm9_off;
4173 imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
4174 offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
4175 datasize = 8 << size_bits;
4176 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4177 &address);
4178 if (insn_bits10_11 != 0x01)
4179 {
4180 if (imm9_off & 0x0100)
4181 address = address - offset;
4182 else
4183 address = address + offset;
4184 }
4185 record_buf_mem[0] = datasize >> 3;
4186 record_buf_mem[1] = address;
4187 aarch64_insn_r->mem_rec_count = 1;
4188 }
4189 else
4190 {
4191 if (vector_flag)
4192 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4193 else
4194 record_buf[0] = reg_rt;
4195 aarch64_insn_r->reg_rec_count = 1;
4196 }
4197 if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
4198 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
4199 }
4200 /* Advanced SIMD load/store instructions. */
4201 else
4202 return aarch64_record_asimd_load_store (aarch64_insn_r);
4203
4204 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
4205 record_buf_mem);
4206 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
4207 record_buf);
4208 return AARCH64_RECORD_SUCCESS;
4209}
4210
4211/* Record handler for data processing SIMD and floating point instructions. */
4212
4213static unsigned int
4214aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
4215{
4216 uint8_t insn_bit21, opcode, rmode, reg_rd;
4217 uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
4218 uint8_t insn_bits11_14;
4219 uint32_t record_buf[2];
4220
4221 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
4222 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
4223 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
4224 insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
4225 insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14);
4226 opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18);
4227 rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20);
4228 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
4229 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
4230
4231 if (record_debug)
b277c936 4232 debug_printf ("Process record: data processing SIMD/FP: ");
99afc88b
OJ		 4233
4234 if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
4235 {
4236 /* Floating point - fixed point conversion instructions. */
4237 if (!insn_bit21)
4238 {
4239 if (record_debug)
b277c936 4240 debug_printf ("FP - fixed point conversion");
99afc88b
OJ		 4241
4242 if ((opcode >> 1) == 0x0 && rmode == 0x03)
4243 record_buf[0] = reg_rd;
4244 else
4245 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4246 }
4247 /* Floating point - conditional compare instructions. */
4248 else if (insn_bits10_11 == 0x01)
4249 {
4250 if (record_debug)
b277c936 4251 debug_printf ("FP - conditional compare");
99afc88b
OJ		 4252
4253 record_buf[0] = AARCH64_CPSR_REGNUM;
4254 }
4255 /* Floating point - data processing (2-source) and
4256 conditional select instructions. */
4257 else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
4258 {
4259 if (record_debug)
b277c936 4260 debug_printf ("FP - DP (2-source)");
99afc88b
OJ		 4261
4262 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4263 }
4264 else if (insn_bits10_11 == 0x00)
4265 {
4266 /* Floating point - immediate instructions. */
4267 if ((insn_bits12_15 & 0x01) == 0x01
4268 || (insn_bits12_15 & 0x07) == 0x04)
4269 {
4270 if (record_debug)
b277c936 4271 debug_printf ("FP - immediate");
99afc88b
OJ		 4272 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4273 }
4274 /* Floating point - compare instructions. */
4275 else if ((insn_bits12_15 & 0x03) == 0x02)
4276 {
4277 if (record_debug)
b277c936 4278 debug_printf ("FP - immediate");
99afc88b
OJ		 4279 record_buf[0] = AARCH64_CPSR_REGNUM;
4280 }
4281 /* Floating point - integer conversions instructions. */
f62fce35 4282 else if (insn_bits12_15 == 0x00)
99afc88b
OJ		 4283 {
4284 /* Convert float to integer instruction. */
4285 if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
4286 {
4287 if (record_debug)
b277c936 4288 debug_printf ("float to int conversion");
99afc88b
OJ		 4289
4290 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4291 }
4292 /* Convert integer to float instruction. */
4293 else if ((opcode >> 1) == 0x01 && !rmode)
4294 {
4295 if (record_debug)
b277c936 4296 debug_printf ("int to float conversion");
99afc88b
OJ		 4297
4298 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4299 }
4300 /* Move float to integer instruction. */
4301 else if ((opcode >> 1) == 0x03)
4302 {
4303 if (record_debug)
b277c936 4304 debug_printf ("move float to int");
99afc88b
OJ		 4305
4306 if (!(opcode & 0x01))
4307 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4308 else
4309 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4310 }
f62fce35
YQ		 4311 else
4312 return AARCH64_RECORD_UNKNOWN;
99afc88b 4313 }
f62fce35
YQ		 4314 else
4315 return AARCH64_RECORD_UNKNOWN;
99afc88b 4316 }
f62fce35
YQ		 4317 else
4318 return AARCH64_RECORD_UNKNOWN;
99afc88b
OJ		 4319 }
4320 else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
4321 {
4322 if (record_debug)
b277c936 4323 debug_printf ("SIMD copy");
99afc88b
OJ		 4324
4325 /* Advanced SIMD copy instructions. */
4326 if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
4327 && !bit (aarch64_insn_r->aarch64_insn, 15)
4328 && bit (aarch64_insn_r->aarch64_insn, 10))
4329 {
4330 if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07)
4331 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4332 else
4333 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4334 }
4335 else
4336 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4337 }
4338 /* All remaining floating point or advanced SIMD instructions. */
4339 else
4340 {
4341 if (record_debug)
b277c936 4342 debug_printf ("all remain");
99afc88b
OJ		 4343
4344 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4345 }
4346
4347 if (record_debug)
b277c936 4348 debug_printf ("\n");
99afc88b
OJ		 4349
4350 aarch64_insn_r->reg_rec_count++;
4351 gdb_assert (aarch64_insn_r->reg_rec_count == 1);
4352 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
4353 record_buf);
4354 return AARCH64_RECORD_SUCCESS;
4355}
4356
4357/* Decodes insns type and invokes its record handler. */
4358
4359static unsigned int
4360aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
4361{
4362 uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
4363
4364 ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25);
4365 ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26);
4366 ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27);
4367 ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
4368
4369 /* Data processing - immediate instructions. */
4370 if (!ins_bit26 && !ins_bit27 && ins_bit28)
4371 return aarch64_record_data_proc_imm (aarch64_insn_r);
4372
4373 /* Branch, exception generation and system instructions. */
4374 if (ins_bit26 && !ins_bit27 && ins_bit28)
4375 return aarch64_record_branch_except_sys (aarch64_insn_r);
4376
4377 /* Load and store instructions. */
4378 if (!ins_bit25 && ins_bit27)
4379 return aarch64_record_load_store (aarch64_insn_r);
4380
4381 /* Data processing - register instructions. */
4382 if (ins_bit25 && !ins_bit26 && ins_bit27)
4383 return aarch64_record_data_proc_reg (aarch64_insn_r);
4384
4385 /* Data processing - SIMD and floating point instructions. */
4386 if (ins_bit25 && ins_bit26 && ins_bit27)
4387 return aarch64_record_data_proc_simd_fp (aarch64_insn_r);
4388
4389 return AARCH64_RECORD_UNSUPPORTED;
4390}
4391
4392/* Cleans up local record registers and memory allocations. */
4393
4394static void
4395deallocate_reg_mem (insn_decode_record *record)
4396{
4397 xfree (record->aarch64_regs);
4398 xfree (record->aarch64_mems);
4399}
4400
1e2b521d
YQ		 4401#if GDB_SELF_TEST
4402namespace selftests {
4403
4404static void
4405aarch64_process_record_test (void)
4406{
4407 struct gdbarch_info info;
4408 uint32_t ret;
4409
4410 gdbarch_info_init (&info);
4411 info.bfd_arch_info = bfd_scan_arch ("aarch64");
4412
4413 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
4414 SELF_CHECK (gdbarch != NULL);
4415
4416 insn_decode_record aarch64_record;
4417
4418 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4419 aarch64_record.regcache = NULL;
4420 aarch64_record.this_addr = 0;
4421 aarch64_record.gdbarch = gdbarch;
4422
4423 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4424 aarch64_record.aarch64_insn = 0xf9800020;
4425 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4426 SELF_CHECK (ret == AARCH64_RECORD_SUCCESS);
4427 SELF_CHECK (aarch64_record.reg_rec_count == 0);
4428 SELF_CHECK (aarch64_record.mem_rec_count == 0);
4429
4430 deallocate_reg_mem (&aarch64_record);
4431}
4432
4433} // namespace selftests
4434#endif /* GDB_SELF_TEST */
4435
99afc88b
OJ		 4436/* Parse the current instruction and record the values of the registers and
4437 memory that will be changed in current instruction to record_arch_list
4438 return -1 if something is wrong. */
4439
4440int
4441aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4442 CORE_ADDR insn_addr)
4443{
4444 uint32_t rec_no = 0;
4445 uint8_t insn_size = 4;
4446 uint32_t ret = 0;
99afc88b
OJ		 4447 gdb_byte buf[insn_size];
4448 insn_decode_record aarch64_record;
4449
4450 memset (&buf[0], 0, insn_size);
4451 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4452 target_read_memory (insn_addr, &buf[0], insn_size);
4453 aarch64_record.aarch64_insn
4454 = (uint32_t) extract_unsigned_integer (&buf[0],
4455 insn_size,
4456 gdbarch_byte_order (gdbarch));
4457 aarch64_record.regcache = regcache;
4458 aarch64_record.this_addr = insn_addr;
4459 aarch64_record.gdbarch = gdbarch;
4460
4461 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4462 if (ret == AARCH64_RECORD_UNSUPPORTED)
4463 {
4464 printf_unfiltered (_("Process record does not support instruction "
4465 "0x%0x at address %s.\n"),
4466 aarch64_record.aarch64_insn,
4467 paddress (gdbarch, insn_addr));
4468 ret = -1;
4469 }
4470
4471 if (0 == ret)
4472 {
4473 /* Record registers. */
4474 record_full_arch_list_add_reg (aarch64_record.regcache,
4475 AARCH64_PC_REGNUM);
4476 /* Always record register CPSR. */
4477 record_full_arch_list_add_reg (aarch64_record.regcache,
4478 AARCH64_CPSR_REGNUM);
4479 if (aarch64_record.aarch64_regs)
4480 for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
4481 if (record_full_arch_list_add_reg (aarch64_record.regcache,
4482 aarch64_record.aarch64_regs[rec_no]))
4483 ret = -1;
4484
4485 /* Record memories. */
4486 if (aarch64_record.aarch64_mems)
4487 for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++)
4488 if (record_full_arch_list_add_mem
4489 ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr,
4490 aarch64_record.aarch64_mems[rec_no].len))
4491 ret = -1;
4492
4493 if (record_full_arch_list_add_end ())
4494 ret = -1;
4495 }
4496
4497 deallocate_reg_mem (&aarch64_record);
4498 return ret;
4499}
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