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Commit | Line | Data |
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43e3346e | 1 | /* |
ff90606f | 2 | * ASPEED SoC family |
43e3346e AJ |
3 | * |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * Jeremy Kerr <jk@ozlabs.org> | |
6 | * | |
7 | * Copyright 2016 IBM Corp. | |
8 | * | |
9 | * This code is licensed under the GPL version 2 or later. See | |
10 | * the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
13 | #include "qemu/osdep.h" | |
da34e65c | 14 | #include "qapi/error.h" |
4771d756 | 15 | #include "cpu.h" |
43e3346e | 16 | #include "exec/address-spaces.h" |
c7c3c9f8 | 17 | #include "hw/misc/unimp.h" |
00442402 | 18 | #include "hw/arm/aspeed_soc.h" |
43e3346e | 19 | #include "hw/char/serial.h" |
03dd024f | 20 | #include "qemu/log.h" |
0b8fa32f | 21 | #include "qemu/module.h" |
ece09bee | 22 | #include "qemu/error-report.h" |
16020011 | 23 | #include "hw/i2c/aspeed_i2c.h" |
ea337c65 | 24 | #include "net/net.h" |
46517dd4 | 25 | #include "sysemu/sysemu.h" |
43e3346e | 26 | |
ff90606f | 27 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 |
d783d1fe CLG |
28 | |
29 | static const hwaddr aspeed_soc_ast2400_memmap[] = { | |
30 | [ASPEED_IOMEM] = 0x1E600000, | |
31 | [ASPEED_FMC] = 0x1E620000, | |
32 | [ASPEED_SPI1] = 0x1E630000, | |
33 | [ASPEED_VIC] = 0x1E6C0000, | |
34 | [ASPEED_SDMC] = 0x1E6E0000, | |
35 | [ASPEED_SCU] = 0x1E6E2000, | |
118c82e7 | 36 | [ASPEED_XDMA] = 0x1E6E7000, |
514bcf6f | 37 | [ASPEED_VIDEO] = 0x1E700000, |
d783d1fe CLG |
38 | [ASPEED_ADC] = 0x1E6E9000, |
39 | [ASPEED_SRAM] = 0x1E720000, | |
2bea128c | 40 | [ASPEED_SDHCI] = 0x1E740000, |
d783d1fe CLG |
41 | [ASPEED_GPIO] = 0x1E780000, |
42 | [ASPEED_RTC] = 0x1E781000, | |
43 | [ASPEED_TIMER1] = 0x1E782000, | |
44 | [ASPEED_WDT] = 0x1E785000, | |
45 | [ASPEED_PWM] = 0x1E786000, | |
46 | [ASPEED_LPC] = 0x1E789000, | |
47 | [ASPEED_IBT] = 0x1E789140, | |
48 | [ASPEED_I2C] = 0x1E78A000, | |
49 | [ASPEED_ETH1] = 0x1E660000, | |
50 | [ASPEED_ETH2] = 0x1E680000, | |
51 | [ASPEED_UART1] = 0x1E783000, | |
52 | [ASPEED_UART5] = 0x1E784000, | |
53 | [ASPEED_VUART] = 0x1E787000, | |
54 | [ASPEED_SDRAM] = 0x40000000, | |
55 | }; | |
56 | ||
57 | static const hwaddr aspeed_soc_ast2500_memmap[] = { | |
58 | [ASPEED_IOMEM] = 0x1E600000, | |
59 | [ASPEED_FMC] = 0x1E620000, | |
60 | [ASPEED_SPI1] = 0x1E630000, | |
61 | [ASPEED_SPI2] = 0x1E631000, | |
62 | [ASPEED_VIC] = 0x1E6C0000, | |
63 | [ASPEED_SDMC] = 0x1E6E0000, | |
64 | [ASPEED_SCU] = 0x1E6E2000, | |
118c82e7 | 65 | [ASPEED_XDMA] = 0x1E6E7000, |
d783d1fe | 66 | [ASPEED_ADC] = 0x1E6E9000, |
514bcf6f | 67 | [ASPEED_VIDEO] = 0x1E700000, |
d783d1fe | 68 | [ASPEED_SRAM] = 0x1E720000, |
2bea128c | 69 | [ASPEED_SDHCI] = 0x1E740000, |
d783d1fe CLG |
70 | [ASPEED_GPIO] = 0x1E780000, |
71 | [ASPEED_RTC] = 0x1E781000, | |
72 | [ASPEED_TIMER1] = 0x1E782000, | |
73 | [ASPEED_WDT] = 0x1E785000, | |
74 | [ASPEED_PWM] = 0x1E786000, | |
75 | [ASPEED_LPC] = 0x1E789000, | |
76 | [ASPEED_IBT] = 0x1E789140, | |
77 | [ASPEED_I2C] = 0x1E78A000, | |
78 | [ASPEED_ETH1] = 0x1E660000, | |
79 | [ASPEED_ETH2] = 0x1E680000, | |
80 | [ASPEED_UART1] = 0x1E783000, | |
81 | [ASPEED_UART5] = 0x1E784000, | |
82 | [ASPEED_VUART] = 0x1E787000, | |
83 | [ASPEED_SDRAM] = 0x80000000, | |
84 | }; | |
ff90606f | 85 | |
b456b113 CLG |
86 | static const int aspeed_soc_ast2400_irqmap[] = { |
87 | [ASPEED_UART1] = 9, | |
88 | [ASPEED_UART2] = 32, | |
89 | [ASPEED_UART3] = 33, | |
90 | [ASPEED_UART4] = 34, | |
91 | [ASPEED_UART5] = 10, | |
92 | [ASPEED_VUART] = 8, | |
93 | [ASPEED_FMC] = 19, | |
94 | [ASPEED_SDMC] = 0, | |
95 | [ASPEED_SCU] = 21, | |
96 | [ASPEED_ADC] = 31, | |
97 | [ASPEED_GPIO] = 20, | |
98 | [ASPEED_RTC] = 22, | |
99 | [ASPEED_TIMER1] = 16, | |
100 | [ASPEED_TIMER2] = 17, | |
101 | [ASPEED_TIMER3] = 18, | |
102 | [ASPEED_TIMER4] = 35, | |
103 | [ASPEED_TIMER5] = 36, | |
104 | [ASPEED_TIMER6] = 37, | |
105 | [ASPEED_TIMER7] = 38, | |
106 | [ASPEED_TIMER8] = 39, | |
107 | [ASPEED_WDT] = 27, | |
108 | [ASPEED_PWM] = 28, | |
109 | [ASPEED_LPC] = 8, | |
110 | [ASPEED_IBT] = 8, /* LPC */ | |
111 | [ASPEED_I2C] = 12, | |
112 | [ASPEED_ETH1] = 2, | |
113 | [ASPEED_ETH2] = 3, | |
118c82e7 | 114 | [ASPEED_XDMA] = 6, |
2bea128c | 115 | [ASPEED_SDHCI] = 26, |
b456b113 | 116 | }; |
43e3346e | 117 | |
b456b113 CLG |
118 | #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap |
119 | ||
b456b113 CLG |
120 | static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) |
121 | { | |
122 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
123 | ||
54ecafb7 | 124 | return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]); |
b456b113 CLG |
125 | } |
126 | ||
ff90606f | 127 | static void aspeed_soc_init(Object *obj) |
43e3346e | 128 | { |
ff90606f | 129 | AspeedSoCState *s = ASPEED_SOC(obj); |
b033271f | 130 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
dbcabeeb | 131 | int i; |
811a5b1d CLG |
132 | char socname[8]; |
133 | char typename[64]; | |
134 | ||
54ecafb7 | 135 | if (sscanf(sc->name, "%7s", socname) != 1) { |
811a5b1d CLG |
136 | g_assert_not_reached(); |
137 | } | |
43e3346e | 138 | |
54ecafb7 | 139 | for (i = 0; i < sc->num_cpus; i++) { |
ece09bee | 140 | object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), |
54ecafb7 | 141 | sizeof(s->cpu[i]), sc->cpu_type, |
ece09bee CLG |
142 | &error_abort, NULL); |
143 | } | |
43e3346e | 144 | |
9a937f6c | 145 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); |
1b0ad567 | 146 | sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu), |
9a937f6c | 147 | typename); |
334973bb | 148 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", |
54ecafb7 | 149 | sc->silicon_rev); |
334973bb AJ |
150 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), |
151 | "hw-strap1", &error_abort); | |
152 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), | |
153 | "hw-strap2", &error_abort); | |
b6e70d1d JS |
154 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
155 | "hw-prot-key", &error_abort); | |
7c1c69bc | 156 | |
1b0ad567 PMD |
157 | sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic), |
158 | TYPE_ASPEED_VIC); | |
e2a11ca8 | 159 | |
75fb4577 JS |
160 | sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc), |
161 | TYPE_ASPEED_RTC); | |
162 | ||
72d96f8e | 163 | snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); |
1b0ad567 | 164 | sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl), |
72d96f8e | 165 | sizeof(s->timerctrl), typename); |
e2a11ca8 | 166 | |
f7da1aa8 | 167 | snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); |
1b0ad567 | 168 | sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), |
f7da1aa8 | 169 | typename); |
e2a11ca8 | 170 | |
811a5b1d | 171 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); |
1b0ad567 | 172 | sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc), |
811a5b1d | 173 | typename); |
26d5df95 CLG |
174 | object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", |
175 | &error_abort); | |
7c1c69bc | 176 | |
54ecafb7 | 177 | for (i = 0; i < sc->spis_num; i++) { |
811a5b1d | 178 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); |
1b0ad567 | 179 | sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]), |
811a5b1d | 180 | sizeof(s->spi[i]), typename); |
dbcabeeb | 181 | } |
c2da8a8b | 182 | |
8e00d1a9 | 183 | snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); |
1b0ad567 | 184 | sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc), |
8e00d1a9 | 185 | typename); |
c6c7cfb0 CLG |
186 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), |
187 | "ram-size", &error_abort); | |
ebe31c0a CLG |
188 | object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), |
189 | "max-ram-size", &error_abort); | |
013befe1 | 190 | |
54ecafb7 | 191 | for (i = 0; i < sc->wdts_num; i++) { |
6112bd6d | 192 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); |
1b0ad567 | 193 | sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]), |
6112bd6d | 194 | sizeof(s->wdt[i]), typename); |
f986ee1d | 195 | } |
ea337c65 | 196 | |
d300db02 | 197 | for (i = 0; i < sc->macs_num; i++) { |
67340990 CLG |
198 | sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), |
199 | sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); | |
200 | } | |
118c82e7 EJ |
201 | |
202 | sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), | |
203 | TYPE_ASPEED_XDMA); | |
fdcc7c06 | 204 | |
811a5b1d | 205 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); |
fdcc7c06 | 206 | sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio), |
811a5b1d | 207 | typename); |
2bea128c EJ |
208 | |
209 | sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), | |
210 | TYPE_ASPEED_SDHCI); | |
211 | ||
212 | /* Init sd card slot class here so that they're under the correct parent */ | |
213 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | |
214 | sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), | |
215 | sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); | |
216 | } | |
43e3346e AJ |
217 | } |
218 | ||
ff90606f | 219 | static void aspeed_soc_realize(DeviceState *dev, Error **errp) |
43e3346e AJ |
220 | { |
221 | int i; | |
ff90606f | 222 | AspeedSoCState *s = ASPEED_SOC(dev); |
dbcabeeb | 223 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
7c1c69bc | 224 | Error *err = NULL, *local_err = NULL; |
43e3346e AJ |
225 | |
226 | /* IO space */ | |
54ecafb7 | 227 | create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], |
d783d1fe | 228 | ASPEED_SOC_IOMEM_SIZE); |
43e3346e | 229 | |
514bcf6f JS |
230 | /* Video engine stub */ |
231 | create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], | |
232 | 0x1000); | |
233 | ||
54ecafb7 | 234 | if (s->num_cpus > sc->num_cpus) { |
ece09bee | 235 | warn_report("%s: invalid number of CPUs %d, using default %d", |
54ecafb7 CLG |
236 | sc->name, s->num_cpus, sc->num_cpus); |
237 | s->num_cpus = sc->num_cpus; | |
ece09bee CLG |
238 | } |
239 | ||
2d105bd6 | 240 | /* CPU */ |
ece09bee CLG |
241 | for (i = 0; i < s->num_cpus; i++) { |
242 | object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); | |
243 | if (err) { | |
244 | error_propagate(errp, err); | |
245 | return; | |
246 | } | |
2d105bd6 CLG |
247 | } |
248 | ||
74af4eec | 249 | /* SRAM */ |
a2e9989c | 250 | memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", |
54ecafb7 | 251 | sc->sram_size, &err); |
74af4eec CLG |
252 | if (err) { |
253 | error_propagate(errp, err); | |
254 | return; | |
255 | } | |
d783d1fe | 256 | memory_region_add_subregion(get_system_memory(), |
54ecafb7 | 257 | sc->memmap[ASPEED_SRAM], &s->sram); |
74af4eec | 258 | |
e2a11ca8 CLG |
259 | /* SCU */ |
260 | object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); | |
261 | if (err) { | |
262 | error_propagate(errp, err); | |
263 | return; | |
264 | } | |
54ecafb7 | 265 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); |
e2a11ca8 | 266 | |
43e3346e AJ |
267 | /* VIC */ |
268 | object_property_set_bool(OBJECT(&s->vic), true, "realized", &err); | |
269 | if (err) { | |
270 | error_propagate(errp, err); | |
271 | return; | |
272 | } | |
54ecafb7 | 273 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_VIC]); |
43e3346e | 274 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0, |
2d105bd6 | 275 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); |
43e3346e | 276 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1, |
2d105bd6 | 277 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); |
43e3346e | 278 | |
75fb4577 JS |
279 | /* RTC */ |
280 | object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); | |
281 | if (err) { | |
282 | error_propagate(errp, err); | |
283 | return; | |
284 | } | |
54ecafb7 | 285 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); |
75fb4577 JS |
286 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, |
287 | aspeed_soc_get_irq(s, ASPEED_RTC)); | |
288 | ||
43e3346e | 289 | /* Timer */ |
2ec11f23 CLG |
290 | object_property_set_link(OBJECT(&s->timerctrl), |
291 | OBJECT(&s->scu), "scu", &error_abort); | |
43e3346e AJ |
292 | object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err); |
293 | if (err) { | |
294 | error_propagate(errp, err); | |
295 | return; | |
296 | } | |
d783d1fe | 297 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, |
54ecafb7 | 298 | sc->memmap[ASPEED_TIMER1]); |
b456b113 CLG |
299 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { |
300 | qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); | |
43e3346e AJ |
301 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); |
302 | } | |
303 | ||
304 | /* UART - attach an 8250 to the IO space as our UART5 */ | |
9bca0edb | 305 | if (serial_hd(0)) { |
b456b113 | 306 | qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); |
54ecafb7 | 307 | serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, |
9bca0edb | 308 | uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); |
43e3346e | 309 | } |
16020011 CLG |
310 | |
311 | /* I2C */ | |
545d6bef CLG |
312 | object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err); |
313 | if (err) { | |
314 | error_propagate(errp, err); | |
315 | return; | |
316 | } | |
16020011 CLG |
317 | object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err); |
318 | if (err) { | |
319 | error_propagate(errp, err); | |
320 | return; | |
321 | } | |
54ecafb7 | 322 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); |
16020011 | 323 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, |
b456b113 | 324 | aspeed_soc_get_irq(s, ASPEED_I2C)); |
7c1c69bc | 325 | |
26d5df95 | 326 | /* FMC, The number of CS is set at the board level */ |
95b56e17 CLG |
327 | object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err); |
328 | if (err) { | |
329 | error_propagate(errp, err); | |
330 | return; | |
331 | } | |
54ecafb7 | 332 | object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], |
6da4433f CLG |
333 | "sdram-base", &err); |
334 | if (err) { | |
335 | error_propagate(errp, err); | |
336 | return; | |
337 | } | |
26d5df95 | 338 | object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); |
7c1c69bc CLG |
339 | if (err) { |
340 | error_propagate(errp, err); | |
341 | return; | |
342 | } | |
54ecafb7 | 343 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); |
dcb83444 CLG |
344 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, |
345 | s->fmc.ctrl->flash_window_base); | |
0e5803df | 346 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, |
b456b113 | 347 | aspeed_soc_get_irq(s, ASPEED_FMC)); |
7c1c69bc CLG |
348 | |
349 | /* SPI */ | |
54ecafb7 | 350 | for (i = 0; i < sc->spis_num; i++) { |
dbcabeeb CLG |
351 | object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); |
352 | object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", | |
353 | &local_err); | |
354 | error_propagate(&err, local_err); | |
355 | if (err) { | |
356 | error_propagate(errp, err); | |
357 | return; | |
358 | } | |
d783d1fe | 359 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, |
54ecafb7 | 360 | sc->memmap[ASPEED_SPI1 + i]); |
dbcabeeb CLG |
361 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, |
362 | s->spi[i].ctrl->flash_window_base); | |
7c1c69bc | 363 | } |
c2da8a8b CLG |
364 | |
365 | /* SDMC - SDRAM Memory Controller */ | |
366 | object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); | |
367 | if (err) { | |
368 | error_propagate(errp, err); | |
369 | return; | |
370 | } | |
54ecafb7 | 371 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); |
013befe1 CLG |
372 | |
373 | /* Watch dog */ | |
54ecafb7 | 374 | for (i = 0; i < sc->wdts_num; i++) { |
6112bd6d CLG |
375 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); |
376 | ||
2ec11f23 CLG |
377 | object_property_set_link(OBJECT(&s->wdt[i]), |
378 | OBJECT(&s->scu), "scu", &error_abort); | |
f986ee1d JS |
379 | object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); |
380 | if (err) { | |
381 | error_propagate(errp, err); | |
382 | return; | |
383 | } | |
384 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | |
54ecafb7 | 385 | sc->memmap[ASPEED_WDT] + i * awc->offset); |
013befe1 | 386 | } |
ea337c65 CLG |
387 | |
388 | /* Net */ | |
d300db02 | 389 | for (i = 0; i < nb_nics && i < sc->macs_num; i++) { |
67340990 CLG |
390 | qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]); |
391 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", | |
392 | &err); | |
393 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized", | |
394 | &local_err); | |
395 | error_propagate(&err, local_err); | |
396 | if (err) { | |
397 | error_propagate(errp, err); | |
398 | return; | |
399 | } | |
400 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | |
54ecafb7 | 401 | sc->memmap[ASPEED_ETH1 + i]); |
67340990 CLG |
402 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
403 | aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); | |
ea337c65 | 404 | } |
118c82e7 EJ |
405 | |
406 | /* XDMA */ | |
407 | object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err); | |
408 | if (err) { | |
409 | error_propagate(errp, err); | |
410 | return; | |
411 | } | |
412 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, | |
54ecafb7 | 413 | sc->memmap[ASPEED_XDMA]); |
118c82e7 EJ |
414 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, |
415 | aspeed_soc_get_irq(s, ASPEED_XDMA)); | |
fdcc7c06 RG |
416 | |
417 | /* GPIO */ | |
418 | object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); | |
419 | if (err) { | |
420 | error_propagate(errp, err); | |
421 | return; | |
422 | } | |
54ecafb7 | 423 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); |
fdcc7c06 RG |
424 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, |
425 | aspeed_soc_get_irq(s, ASPEED_GPIO)); | |
2bea128c EJ |
426 | |
427 | /* SDHCI */ | |
428 | object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err); | |
429 | if (err) { | |
430 | error_propagate(errp, err); | |
431 | return; | |
432 | } | |
433 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | |
54ecafb7 | 434 | sc->memmap[ASPEED_SDHCI]); |
2bea128c EJ |
435 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, |
436 | aspeed_soc_get_irq(s, ASPEED_SDHCI)); | |
43e3346e | 437 | } |
ece09bee CLG |
438 | static Property aspeed_soc_properties[] = { |
439 | DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0), | |
95b56e17 CLG |
440 | DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, |
441 | MemoryRegion *), | |
ece09bee CLG |
442 | DEFINE_PROP_END_OF_LIST(), |
443 | }; | |
43e3346e | 444 | |
ff90606f | 445 | static void aspeed_soc_class_init(ObjectClass *oc, void *data) |
43e3346e AJ |
446 | { |
447 | DeviceClass *dc = DEVICE_CLASS(oc); | |
448 | ||
ff90606f | 449 | dc->realize = aspeed_soc_realize; |
469f3da4 TH |
450 | /* Reason: Uses serial_hds and nd_table in realize() directly */ |
451 | dc->user_creatable = false; | |
4f67d30b | 452 | device_class_set_props(dc, aspeed_soc_properties); |
43e3346e AJ |
453 | } |
454 | ||
ff90606f | 455 | static const TypeInfo aspeed_soc_type_info = { |
b033271f CLG |
456 | .name = TYPE_ASPEED_SOC, |
457 | .parent = TYPE_DEVICE, | |
b033271f CLG |
458 | .instance_size = sizeof(AspeedSoCState), |
459 | .class_size = sizeof(AspeedSoCClass), | |
54ecafb7 | 460 | .class_init = aspeed_soc_class_init, |
b033271f | 461 | .abstract = true, |
43e3346e AJ |
462 | }; |
463 | ||
54ecafb7 | 464 | static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) |
43e3346e | 465 | { |
54ecafb7 | 466 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); |
b033271f | 467 | |
54ecafb7 CLG |
468 | sc->name = "ast2400-a1"; |
469 | sc->cpu_type = ARM_CPU_TYPE_NAME("arm926"); | |
470 | sc->silicon_rev = AST2400_A1_SILICON_REV; | |
471 | sc->sram_size = 0x8000; | |
472 | sc->spis_num = 1; | |
473 | sc->wdts_num = 2; | |
d300db02 | 474 | sc->macs_num = 2; |
54ecafb7 CLG |
475 | sc->irqmap = aspeed_soc_ast2400_irqmap; |
476 | sc->memmap = aspeed_soc_ast2400_memmap; | |
477 | sc->num_cpus = 1; | |
478 | } | |
479 | ||
480 | static const TypeInfo aspeed_soc_ast2400_type_info = { | |
481 | .name = "ast2400-a1", | |
482 | .parent = TYPE_ASPEED_SOC, | |
483 | .instance_init = aspeed_soc_init, | |
484 | .instance_size = sizeof(AspeedSoCState), | |
485 | .class_init = aspeed_soc_ast2400_class_init, | |
486 | }; | |
487 | ||
488 | static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) | |
489 | { | |
490 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | |
491 | ||
492 | sc->name = "ast2500-a1"; | |
493 | sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); | |
494 | sc->silicon_rev = AST2500_A1_SILICON_REV; | |
495 | sc->sram_size = 0x9000; | |
496 | sc->spis_num = 2; | |
497 | sc->wdts_num = 3; | |
d300db02 | 498 | sc->macs_num = 2; |
54ecafb7 CLG |
499 | sc->irqmap = aspeed_soc_ast2500_irqmap; |
500 | sc->memmap = aspeed_soc_ast2500_memmap; | |
501 | sc->num_cpus = 1; | |
43e3346e AJ |
502 | } |
503 | ||
54ecafb7 CLG |
504 | static const TypeInfo aspeed_soc_ast2500_type_info = { |
505 | .name = "ast2500-a1", | |
506 | .parent = TYPE_ASPEED_SOC, | |
507 | .instance_init = aspeed_soc_init, | |
508 | .instance_size = sizeof(AspeedSoCState), | |
509 | .class_init = aspeed_soc_ast2500_class_init, | |
510 | }; | |
511 | static void aspeed_soc_register_types(void) | |
512 | { | |
513 | type_register_static(&aspeed_soc_type_info); | |
514 | type_register_static(&aspeed_soc_ast2400_type_info); | |
515 | type_register_static(&aspeed_soc_ast2500_type_info); | |
516 | }; | |
517 | ||
ff90606f | 518 | type_init(aspeed_soc_register_types) |